3.

9 NETWORKED EMBEDDED SYSTEMS

Each specific 1o device may be

interfaced
connected to
others using specifie intcríaces: for example. an 1o device
LCD controller. keyboard controlleror print controller using specific interface.
connects and is to an
Bus cornmunication simplifies the number of connections and provides a common protocol for intenconnecting
different or same type of 10 devices.
Any device that is compatible with a system's 1O bus can beadded to the system (assumings appropriate
device driver program is available), and a device that is compatible with a particular1Obus can be
integrated
into any system that uses that type of bus. This makes systems that use 10 buses very flexible. as opposedto
direct intereonnections between the processor and cach 10 device. and it allows system support to many
different 10 devices (depending on the needs of its users), and it also allows users to change the IO devices
that are altached to system as their needs change.
The main disadvantage each bus has fixed bandwidth that
of an 10 bus (and buses in general) is that a
must
be shared by all the devices, which eonnect to the bus. Even worse, eld nstr nts
( length and
transmision line elfects) cause buses to have less bandwidth than using the same number of wires to connect
just two devices. Iissentially. there is a trade-off between interface simplicity and bandwidth sharing. Assume
that bandwidth of a bus is 200 Mbps. If the bus conmmunicates two devices simultaneously then it does so by
100 Mbps communication by each.
10 devices communicate with the processor through an 10 bus, which is separate from the menmory bus
that the processor uses to comumunicate with the memory system. Embedded systems connected intermally on
the same 1C or systems at very short, short and long distances, and can be networked using the followings
ypes of 1O buses, each funetioning according to specilic prutocols.
1. Using a serial 10 bus allows a computer or controller or embedded system to interface neiwork with a
wide range of 10 devices without having to implement a specific intcrface for each I0 device. When
 Input and Output Devices
Input and output devices allow the computer
system to interact with the outside world by
moving data into and out of the system. An
input device is used to bring data into the
system. Some input devices are:
.Keyboard
Mouse
Microphone
.Bar code reader
Graphics tablet
An output device is used to send data out ofi
the system. Some output devices are:
.Monitor
. Printer

.Speaker
Input/output devices are usually called /0
devices. They are directly connected to an
electronic module inside the systems unit
called a device controller. For example, the
speakers of a multimedia computer system
are directly connected to a device controller
called an audio card (such as a
Soundblaster), which in turn is connected to
the rest of the system.
ilo
Sometimes secondary memory devices like
the hard disk are called 1/0 devices (because
they move data in and out of main memory.)
What counts as an 1/0 device depends on
context. To a user, an 1/0 device is
something outside of the system box. To a
programmer, everything Outside of the
processor and main memory looks like an
I/0 devices. To an engineer working on the
design of a processor, everything outside of
the processor is an 1/0 device.
A computer that is dedicated to running aa
program that controls another device is an
embedded system. An embedded system is
usually embedded inside the device it
controls. Usually they run just one program
that is permanently kept in a special kind of
main memory called ROM (for Read Only
Memory). More processor chips are sold per
year for embedded systems than for all other
purposes.
 3.1 IO TYPES AND EXAMPLES
communication means that over givenline or channel
port for serial communication. Serial
A serial port is a clock. A serial port
periodic intervals generated by a

one bit can communicatc and the bits transmit at

communication is over short or long distances. bits can

communication means that multiple
communication. Parallel
A
parallel port is a port for parallel within the same

over a set any given

of parallel lines at instance. A parallel port communicates
Onunicate a meter.
distances of at most less than
DOard, between 1Cs or wires over very short (Section 3.4) by using a
features and sophistication
A or parallel port can provide certain special
Seral
processing element. communication but without
mobile communication is serial
Forts can interconnect by wireless. Wireless or
wireless network, and transmission
network as well as long-range
wires, can be over a short-range personal The carrier modulates the serial bits before transmission in air
area

takes place by using carier frequencies. the serial bits back.

Sections 3.5 and 3.13]. A receiver demodulates and retrieve
1O types: () Synchronous serial
Serial and parallel ports of IO devices can be classified into following
serial UART
serial (ii) Asynchronous serial UART input (iv) Asynchronous
nput (1) Synchronous output
Parallel port input (vii) Parallel port
Output (y) Parallel port one bit input (vi) Parallel one bit output (vii)
as output; for example, a modem.
output. Some devices function both as input and

3.1.1 Synchronous Serial Input

The part 1 in Figure 3.1(a) shows a synchronous input serial port. Each bit in each byte byte
and each received

is in synchronization. Synchronization means separation by a constant

interval or phase difference [part 2 in
the is received at input in period 8 T. The bytes
Figure 3.1(a)]. If clock period equals T, then each byte at port
are received at constant rates. Each byte at the input port separates by
8 T and data transfer rate for the serial
with the serial bits, also sends the clock pulses
linebits is 1/T bps [I bps 1-bit per second]. The sender, along
=

with
SCLK (serial clock) to the receiver port pin. The port synchronizes the serial data-input bits
clock bits.
The serial data input and clock pulse-input are on same input line when the clock pulses either encode or
modulate serial data input bits suitably. The recciver detects clock pulses and receives data bits after decoding
or demodulating
When a separate SCLX input is sent, the receiver detects at the middle, positive or negative edge of the
lock pulses that indicate whether data-input is I or 0 and saves the bits in 8-bit shift register. The processing
element at the port (peripheral) saves the byte at a port register from where the microprocessor reads the byte.
Synchronous serial input is also called master output slave input (MOSI) when the SCLK is sent from the
sender to the receiver and slave is forced to synchronize sent inputs from the master as per the master clock
inputs. Synchronous serial input is also called master input slave output (MISO) when the SCLK is sent to the
sender (slave) from the receiver (master) and the slave is forced to synchronize sending the inputs to master as
per the master clock's outputs
Synchronous serial input is used for interprocessor transfers, audio inputs and streaming data inputs.
 Devices and Communication Buses for Devices Network
****

Slate
10 11 12 3 14 15 16 17 1
10-17 L ITM
00-DT Serial
Input Time ASAMGROU
Port L Serid in Bits
**

Clock (Optional)
.

State
00010203040506 O7

Serial 00-07
Output Time
Port
Serial Output
O0-0 Bits
Cloct (Optional)

Half Duplex Serial In'Out

10-07
Ful Duplex
00-0 10-C7 and O0-07
At dfferent Timo Slols D0-D7 Serial In'Out
00-07 0UP
C o2H
Cok(Optiona
(a)
ECALL Ko....
CS
DTE
DCD
DCE
10 OR 11 Date 3/4at.
DSR
AO DTR Time
A1 RIS UART Serial
A2
CTS Bits for Data n a different
TxD RxD SlartI Bit Phase or

RxD TxD Frequency

for State 1
DO-D7 k P-Bit and
(Optional)
State 0
All Integrated in an Stop Bit
Embedded System
(c)
Fig. 3.1 (o) Input serial port, Output Serial port, Bi-directional half-duplex serial port, and Bi
directional full-duplex serial port (b) Handshaking signals at COM port in computer and
(c) a UART serial port bits

3.1.2 Synchronous Serial Output

The part 3 in Figure [Link]) shows a synch1ronous
output serial port. Each bit in each byte is in synchronization
with a clock. The bytes are sent at constant rates (part 4 in
Figure 3.1(a)). If the clock period equals T, then the
data transfer rate is 1T bps. The sender sends either the clock at SCLK
pulses or the scrial data
pin and output
clock pulse-input through same output line when the clock pulses either suitably modulate or encode tic
serial output bits.
 3.1.3 Synchronous Serial Input-Output
Each bit in each byte synchronizes
The rart 5 in l4a) shows a sychronous serial input-output port.
Figue as shown in parts (2) and (4)
w ith the cllxk input and output.
The bytes are vent or received at constant rates
the erial
the cock pulses suitabl; ndulate or encode
in Figure luai| The 1Os are on same 1O line when
3, rate is |/ Tbps. The proesing
input and output, respectively.
If period cquals T, then the data transfer
the clock from which the mucroprocessor
or
(eripheral) ends and receives the by te at port register to
a
cleent at the prt
writes or reads the byte.
master input slave output (MISO) and
master output slave
Synchronous serial input/outputs are also called
input (MOS), respectively.
data. The bits are re:ad from or written on magnetic
They are used for interprocessor transfers and streaming lO ports.
icdia such as a hard disk or on optical nedia such as a CD by using devices with serial synchronous
port when input and output lines separate.
are
The part 6 in Figure 3.1(a) shows the 10 synchronous

3.1.4 Asynchronous Serial input

bit is
shows the serial port line, denoted by RxD (receive data). Each RxD
asynchronous input
Figure 3.1(b)
received in each byte at ixed intervals but each received byte is not in synchronization. The bytes can separate
3. Ife), on the right side, shows the starting point of receiving
.hy variable mtervals or phase dilferences. Figure
irom I to (0 for a period T. When a sender shilts after every
h e bits for each byte, indicated by a l1ne transitiva
11 T. The time of 2Tis due to use
clch perind T. then a byte at the port is received at input in period I)T or
and end of each
of additional bits at the start An iddition time of 1T is taken when a P-bit is sent before
byte.
the stop bit.
be received
The bit transler rate (for the serial line bits) is (1/1) baud per second but different bytes may
at varying intervals. The word °Baud'
is taken from a Geman word for raindrop. Bytes pour from the sender
sender does not sed the clock pulses along with the bits.
like raindrops at irregular imtervals. The
The receiver bits at the intervals
detects n Irom thhe middle of the lirst indic:ating bit. n 0, 1,... I0 or
of T
=

0 and saves the bits in an 8-bit shift register. The prvessing

11. finds out whether the data-input is I or
at a port register, Iromm where he microprcessor re:ads the byte.
element at the port (peripheral) saves the byte
is also called UART if the serial input is according to the UART protecol
input
Asynchronous serial input
(Section 3.2.3). Asynchronous serial input is used for keypad and modem inputs.

3.1.5 Asynchronous Serial Output

denoted by TxD (transmit data). Each bit in each
Figure 3.1(b) shows the asynchronous output serial port line,
is not in synchronization (it is separated by a variable
byte is sent at fixed intervals but cach output byte the bits for each byte,
interval or plrase dillesece). The Figure 3.l(¢) sluows the starting point of sending
0 for T. The sender port cof TxD does not send clck
which is indicated by a line transition from I uo a period
pulses along witl1 thhe bits.
the nniullle of the stut indicating bit,
The sender ransnts bytes al the minimum inteivals of n T. Bits start from
wheten=0, 1,.., 10or ll and semds the bits through a 10- or I1-bit shitt register |ligure 3. l(«)). Tne precessing
elenent at the port (periplieral) sends the byte at a port register to where the nierorucessor writes the byte.
 3.2 SERIAL COMMUNICATION DEVICES
3.2.1 Synchronous, lIso-synchronous and Asynchronous Communications
from Serial Devices

Synchronous Communication When a byte (character) or frane (a collection of bytes) of data is

received or transmitted at constant time intervals with unilorm phase differences, the comnmunication is called
synchronous. Bits of a data Irame are sent in a lived maIxImuni time interval. Iso-synchronous is a special
case when the maxinum time interval can be varied.
An cxample of synchronous serial communiCation is tr:ames sent over a LAN, l'rames of data communicate,
with the time interval between each Irane renaining constant. Another example is the inter-processor
communication in a nultiprocessor system. Table 3.2 gives a synchronous device port bits.
Figure 3.1(a) part 2 showed the serial 1O bit format and serial line states as a function of time. Two
characteristics of synchronous communication are as follows:
1. Bytes (or frames) maintain a constant phase dillerence. t means they are synchronous, that is, in
synchronization. There is no permission for sending cither the bytes or the frames at random tine
intervals; this mode therefore does not provide for handshaking during the communication interval.
[Handshaking means that the source and destination first exchange the signals between the1 belore
they communicate the data bits.] The naster is the one whose clock pulses guide the transmission aund
slave is the one which synchronizes the bits as per the master clock.
2. A clock ticking at a certain rate must always be there to serially transmit the bits of all the bytes (or
frames). The clock is not always implicit to the synchronous data reccivet. The transmiter generaly
transmits the clock rate information in the synchronous communication of the data.

8
[Link] Stairea wuT tamota

Devices and Communication Buses for Devices Network

Table 3.2 Synchronous device port bits

[Link]. Bitsat Pon Compulsory or

Explanation
Optional
Sync code bits or bi- Optional A few bits (cach separated by interval AT)
sync code bits or frame as Sync code for frame synchronization or
start and end signaling signaling precedes the data bits . There may
oIIS be inversion of code:bits after each framc.".
Flag bits at start and end arc also used-in
certain protocols
Data bits m frame bits or 8 bits transmit such that each
L
Compulsory
bit is at the line for tümec AT or each frame is
atthe line tor timc m.AT4.

5. Clock bits Mostly not optional Either on a sepaurate clock line or on a single
line such that the clock information is also
embedded with the data bits by an appropriate
encoding or modulation
Reciprocal of AT is the transfer rale in dit per second (bps).
m may be a large number. t depends on the protocol.

Figure 3.2 gives ten methods by which synchronous signals, with the clocking information, are sent.
) There aretwo separate lines for the data bits and clock. The parallel-in serial-out (PISO) and serial-in
paralle-out (SPO) are used for transmiting and recciving the signals for data, respectively. (Gn There is a
common line and the clock information is encoded by modulating the clock with the stream of bits. (ii) Thecre
are preceding and succeeding addiional synchronizing and signaling bits. There are five comnon methods of
encoding the clock infomation into a serial stream of the bits: (a) Frequency Modulation (FM (6) Mid Frequency
Modulation (MFM) (c) Manchester coding (d) Quadrature amplitude modulation (QAM) (e) Bi-phase coding.
The synchronous receiver separates serial bits of the message as well as synchronizing clock.

Synchronization Ways

Separate DataEBits Embeddedd

Clock Pulses
Along with the
Modulated Clock Information
or Encoded with a Data
a Bits with Clock Bit Frame Before
Information Transmitting

PISO SIPO
(Transmit) (Receive) Synchronization Bi-Sync
Code Bits
Preceding a
Coding

Data Bit-Frame
FM MFM QAM Bi-Phase Manchester (sync Code)
In-between frames
Signaling Bits
Fig. 3.2 Ten ways by which the synchronous signals with the clocking information transmit from a
master device to slave device
 136 .Embedded Systems

Asynchronous Communication When a byte (characters) or frame (a collection of bytes) of data is

received or transmitted at variable time intcrvals, communication is called asynchronous. Voice data on the
line is sent in asynchronous mode. Over a telephone line the communication is asynchronous. Another cxample
is keypad communication.
An cxample of mode of asynchronous communication is R$232C communication between the UART
devices (Scection 3.2.2).
UART communication (Section 3.2.3) for asynchronous data is used for the transfer of infomation between
the keypad or keyboard and computer.
Two characteristics of asynchronous communicalion arc as follows:
1. Bytes (or frames) need not maintain a constant phase difference and are asynchronous, that is, not in
synchronization. Bytes or frames can be sent at variable time intervals. This mode therefore facilitates
in-between handshaking between the serial transmitter port and serial receiver port.
2. Though the clock must tick at a certain rate to transmit bits of u single byte (or frame) serially, it is
always implicit to the asynchronous data receiver. The transmitter does not transmit (neither separately
nor by encoding using modulation) along with serial stream of bits any clock rate information in
asynchronous communication. The receiver clock is thus not able to maintain identical frequency and
constant phase difference with the transmitter clock.
When a device sends data using a serial communication frame, it may not be as simple as shown in
Figures 3.1(a) and (b) or as given in Table 3.2. It can be complex and has to be as per the protocol, which is
followed by transmitting and receiving devices during communication between them.

Example 3.1
An IBM personal computer has two COM ports (communication ports), COMI and COM2. These have
8 bytes at 10 addresses Ox3F8 and Ox2F8.
Figure 3.1(b) showed COM port handshaking signals besides TxD and RxD. When a modem connects,
it detects a carrier signal on the telephone line. A modem sends data carrier detect DCD signal at time o
A modem then communicatcs data set reaidy (DSR) signal at time t, when it receives the bytes on the line.
The receiving end responds at time h by data tcminal ready (DTR) signal. After DTR, request to send
(RTS) signal is sent at time ly and the recciving end responds by clear to send (CTS) signal at time ty
After the response CTS, the data bits are transmitted by modem from t, to the receiver terminal at
successive intervals [Figure 3.1(c)]. Between two sets of bytes sent in asynchronous mode, the
handshaking signals RTS and CTS can again be exchanged. This explains why the bytes do not
remain synchronized during asynchronous transmission.

A communication system may use the following protocols for synchronous or asynchronous transmission
from a device port: R$232C, UART, HDLC, X.25, Frame Relay, ATM, DSL and ADSL. These are protocols
for networking the physical devices in tclecommunication and computer networks. Ethernet and token ring
arc protocols used in LAN networks. There are a number for protocols for serial communication. RS232C,
UART and HDLC are described in Sections 3.2.2 to 3.2.4.
The protocols in embedded network devices such as bridges, routers, embedded Intemet appliances use
bridging, routing, application and web protocols. Intemet enabled embedded systems use application protocols
-
HTTP (hyper text transfer protocol), HTTPS (hyper text transfer protocol Secure Socket Layer), SMTP
Simple Mail Transfer Protocol), POP3 (Post office Protocol version 3). ESMTP (Extended SMTP), TELNET
(Tele network), FTP (ile transfer protocol), DNS (domain network server), IMAP4 (lntemet Message Exchange
Application Protocol) and Bootp (Bootstrap protocol) and others (Section 3.11).
 3.3 PARALLEL DEVICE PORTS
The parallel port of devices transfers number ofbits over the wires in parallel. Parallel wires capacitive effect
reduces the length up to which parallel communication can be done. High capacitance results in delay for the
bits at the other end undergoing transition from 0 to l orirom I to 0. High capacitance can also result in noise
and cross talk (induced signals) between the wires. Therefore, parallel port carries the bits upto short distances,
generally within a circuit board or IC.
Figure 3.4(a) shows the parallel input, output, and bi-directional device ports. Figure also shows a device-
interfacing circuit with the processor and system buses. Parailel port inputs I0 to 17. may be to a keypad
controller. Parallel port outputs 00 to 07 may be output bits to LCD display output controller.
are the input and
BR, and BRo
output data buffers at bi-directional 1O port.
A device port connects to the address bus signals, A; and A, through a port address decoder. IORD and
IOWR are additional control signals for a port device read and write, respectively, in case of an 80x86
processor, which has 1O mapped 10s. The memory read and write signals, RD and WR are used in the
processor with memory mapped IOs [Section 2.2.2].

17 [Link] Cdllieu WIUI LdiIE

144 .tc Embedded Systefms

CS-Port Select
BA-Buffer Register
for Input An Input Port
BR-Buffer Register
for Output CSBR 10-17

Keypad

IORD
Port
An Output Port
Addresses
Decoder BR
00-07
Processor LCD Display
OWR
An O Port

CS BR. I00-107 Modem

MessagesS
or
ORD
Note: Touch Screen
APort can have 1 or 2
or more addresses allotted for it and
OWR
a few address Bus bits at Input
(a)

cs 1Strobe Request
Control ORD
Input
Signals 2
OWA Port Ready

DO-07
Data Bus
Bufer Full

2 output
Acknowledge

Interrupt
Request (b)
Fig. 3.4 (a) Parallel input port, output port, and a bi-directional port for connecting the device
(b) The handshaking signals when used by the I0 ports

CvNmanlo
 A

35WIRELESSDEVICES
Wireless devices have become very common in recent years for serial transmission of bits.
Wireless devices use infrared (IR) or radio frequencies after suitable modulation of data bits. IrDA
(Section 3.13.1), Bluetooth (Section 3.13.2), WiFi, 802.11 WLAN (Section 3.13.3) and ZigBee
(Section 3.13.4) have become popular protocols for wireless communication of data bits from a source to the
receiver.
An IR source communicates over a line of sight and the receiver phototransistor is used for detecting
infrared rays. Example of applications of IR communication includes handheld TV remote controllers and
robotic systems. IR devices use IrDA protocol.

25 [Link] SCdlieu wIUI LdiID

Radio frequencies communicate over short and long distances. The transmitter and receiver use antennae
to transmit and receive signals and modulator and demodulators to cay the data bits using RF frequencies.
Mobile GSM wireless devices use 890-915 MHz, 1710-1785 MHz, or 1850-1910 MHz bands.
Mobile CDMA wireless devices use 2 GHz carrier frequencies. Bluetooth and ZigBee wireless devices
(Sections 3.13.2 and 3.13.4) use 2.4 GHz or 900 MHz frequencies.
The number of frequency bands is limited, while a large number of devices may need to communicate
Therefore, tinme and frequency division multiplexing are used. An innovative method is radio frequency
hopping over a wider spectrum, as in Bluetooth devices. The transmitted carrier frequencies hop among
different channels at a given hopping rate. The transmitter modulates the data bits as per protocol specifications.
The receiver tunes to these hopped carier frequencies at a given hopping rate and in the same hopping
sequence as the ones used by the transmitter. The recciver demodulates and detects the data bits as per physical-
layer protocol used for transmitting.

Several wireless devices network use FHSS or DSSS transmitters and receivers. Popular protocols are
IrDA,Bluetooth, 802.11 and ZigBee.
 3:6 TIMER AND COUNTING DEVICES
Most embedded systems need a timing device.

3.6.1 Timing Device

A timer device is a device that counts the regular interval (ST) clock pulses at its input. The counts are stored
and incremented on each pulse. It has output bits (in a count register or at the output pins) for the period of
counts. The counts multiplied by interval 8T gives the time. The (counts-initial counts) x 8T interval gives the
time interval between two instances when the present count bits are read and the initial counts are read. It has
an input pin (or a control bit in a control register) for reseing to make all count bits = 0. It has an output pin
(or a status bit in status register) for ouiput when all count bts equal0 after reaching the maximum value,
which also means timeout on the overflow.

3.6.2 Counting Device

A counting device is a device that counts the input for events that may occur at irregular or regular intervals.
The counts gives the number of input events or pulses since it was last read.

Blind Counting Synchronization A counting device may be free running (blind counting) device
a
with a prescaler for the clock input pulses and for comparing the counts with the ones preloaded in a compare
register. The prescalar can be [Link] p= 1,2, 4, 8, 16, 32, , by programming a prescaler register.
Tt divides the input pulses as per the programmed value of p. It has an output pin (or a status bit in the status

register)orfor output when all count bits equal 0 after reaching the maximum value, which also means after
overflows after p x 2 x8T interval. It can have an input pin (or a control
timeout on overflow. The
bit for
counter
in control register) enabling an output when all count bits equal
count preloaded in the compare
register Atthat instance, a status bit or output pin also sets in and an intermupt can occur for event of comparison
This processor interrupts at preset instances or after preset intervals
equality.
with
device is useful for the alarm
to another event from another
or
respect source.
 The counting device may be the free running (blind counting) device with a prescalar for the cloek input
pulses, for comparing the counts with the ones preloaded in a compare register as well as for capluring counts
on an input event. This device functions are similar to the above, but there is an addition input pin for sensing
an event and for saving the counts at the instance of that event. At this instance, a status bit can also set in and
a processor interrupt can occur for the capture event.
The above device is usesul for alarm generation and processor intemupts at the preset times as well as for
the processor to use
noting the instances of uceumences of the events and processor interupts for requesting
the captured counts on the events. Alarm generation can be synchronized with the input capture events.
Writing counts into the compare register does this. Counts in the register are set equal to capture register
counts plus additional counts, which define the interval after which an alam is to be generated.

A blind counting free runing counter with prescaling. compare and capture registers has a number of
applications. It is useful for action or initiating a chain of actions, and processor intern1pts at the preset
instances as well as for noting the instances of accurrnces of the events amd processor interupts for
requesting the processor to use the captured counts on the events for future actions.

3.6.3 Timer cum Counting Device

Adiner cum counting device is a caunting elevice that has two fumctions. (1) t counts the input due to theevents
at imegular instances and (2) It counts the cloek input a status bit in the
pubses at regular intcrvals. An
input or

tining device register comros the mote as timer er cnter. The connts gives the mumber of input events or
pulses since it last read. t has
was output pin
an hit in
repister) for
t n a stats output when all count bits
status
cqual O after reaching the masimum value, which also meanv timeomt or uverflow internupts to tlhe processor
Table 3.5 lists twelve uses of a timer device. I also esplaius the meaning of each use.

Table 3.5 Uses of Timer Device

[Link]. Applicatims and Explanation

Real Time Clock Ticks (functioning as systenm heart beats). Real time cleck is a clock that once the
system stats it, does noI stop and c:an't be reset. Its count value caun't be reloaded. Real time endlessly
flows and never reurns!) Real Time Clock is set for ticks using prescaling bits and rate-sct bits in

ppropriate control registers. Section 3.8 gives the details.

Initiating an event after a
preset delay time. Delay is as
per couwnt-value loaded.

3. Initiating an cvent (or a pair of events or a chain ofevents) after a comparison betwcen the preset
ime with counted value. Preset time is loaded in a Compare Regisier. [It is similar to presetting an
alarm.]
Capturing the count-value at the timer on an event. The informalion of time (instance of thc event)
4
is thus stored at the capture register.

5. Finding the time intcrval between two cvents. Counts are captured at cach event in the capture
register and read. The intervals are thus found outL. A service routine does the counts read on interrupt.

6. Wait for a message froma queue or mailbox or semaphore for a preset time when using an RTOS.
There is a predefined waiting period before RTOS lets a task run without waiing for the message
(Section 7.4)
(Contd)
 SR Conce
atuilion of processor for
9ntemupt means venl. Alhich învites the
hlare evet
Sonme actian on 1he hard nlare 6r sof1
an memupt
a device or port genardtes
oa

lhun a device or port s ready

,

.
Alhen it conmpletes the assiqned
action, t qenercrtes an merrup. 7his
inlarrupt i called hard hlaie interrapt detected, etther proce
Candihon îs
3. hihen sofB run-time ecepfion
nlare
Rs called
Sor hlo sl» înstruction generates
or
an lerrapt. This tnterrypt
Softuare nterrupt or thap * excephon.

the vouthe
or proqram, htbich fs runntnq
i n responge to the"nterrupt,
and an TsR is eneculed.
at present ge+ îolerupled
seturcssR
I. An SR call cue bo interapt encutes an eve Eveot Can Orear at any
moment and event occurences are asunchronou
[Link] call s evenl -baseed chversíon rom he Qurent Squerce af insthucion
to the anoler Sequence o îmstruckons. Tht: sequencea inetructiors execetes
till the returm înstruction.
3. Event canbe a ceikte
a
port event or slw cumputatonal eceptional
Canchfion ddeted by tlo n ceiectec by poram khich Tro

the ecepton.

29 [Link] Scanned by CamScanner

5
e n event ean be siqnallecd by sho inteirupt nstructioo sAn Uialin
cevice ciivung functions Creat c 1, openC ).cle.
Service mechoniem existi în a
Syetem o call the cRa
5 An Toierrpt
fom mulliple Sourtes.
cattution
to TsR may or ma not take place on mchinq the
6. Diversion
oany mshuction in the presently running ouhne.

nterryot wSourcesw
be om nternat cevîces or erernal phenphercls
*Hacdhlare Sources can
[Link] to
Which întemupt the onqoing Toutine and there by Cause

Coresponding 9sp
Softuare Soures for itcrupt are telated tob
G processor ttecting Compulational enor or an leal op-code duing
exccution 0
G7) evecution f an sa înstruction to Caute rscssor oterupt
o0 qpinq roufine.
in the
There may be Come alher Special types af &ouces provicled
Sustem are
 4. Hard hlare Snterupts Retatcd to 9meunal devîces
Hlw mierrapt whíich can îmerrapl an onqing
Soutices
There are no o
micro Condroller or înternal devîces ho
program. These are
procescor or

Specidae
receîver post, Apc start oj Conversion
E:-farallel port, vART Serfal
ADC end 3 . Sunchronout
recéver byte Completdo,ete.
to E1ternal Devîces-
Hord Ware anterrupi relaBed
havd ware rterrpt souree a nterrupting an
There canbe esternal Veclon [Link]
Pproqiam prov+des ihe sR aress or
that also
on gping
or interrul -ype Infamation through the dta bua.

E:- ANTR in 8o86 and 8orr6.

30 [Link] Scanned by CamScanner

to Etternal Devices a
alhare nterrupti Related
-

3. C w

are
Erternal had hlare interupi nlth theîr 1sR Vector acklhess
an on qoing program
process or m+cro Contoller Specffic mtenupt of
-

esternal teruption Sauce doesnol end ntemupt -4pe ot 1se addkess.

re lacled inermtian
cycles clo«k Unmaskable
e-Non maukable pin, hHhio fast few (Mfr]GNToGNT1,
declarable pin beut otheuose maskable, Maukade pîn
. Sotware &rror Related tlardWare terup

These Cao be the ftware - enar related henupti qeneraled by is

procersor hardnare. Each [Link] hos Speafe înstruckion [Link]
a

desfqned for That sel only.

*An sllegpl Cade Cinchructian m the sto) %an înstruction hlhich do4
not Correspnd to any nshuction n Hhs set. Nthenever the [Link]

fetches dlcqal code an mterrupt Certain processors The

occurs în
eor related îmlerupt are also called haid hlare -qenerattd softhlare
aps (or otware ezceptionc)
E-Ovisio y dete cüon (or hap) by
ero
haud klaie, Orer fb4 by b.
tnder -lo by hho, 9lgal opcete bs Hlo.

5. Soft htare nchuetsn - Related

w
Sctevrapli
wMw
scuces
wm

can aso handle Specific computational enors or run firme

A proqram
kome Conclikionc. processorA povide tor aftare
Condr Hone or iqnalling
înshuctions related b the trapes, ignalk o eceptine

() There Ore ce taîn seftuare mchruetionu for interruphng

and theo
civertinq to the ask alko called the Siqnal handler. These are Ued
raukine rom an onqoing routine or fak
for Snqraling to ansther
a thread.
OT) tuare mstructiuns are for trapping some vun-time
also ted
eror Conch Ron ond executinq eceptioral hondlers on Cabching he
exceptions.
 NTERRUPT SERVIcING ( HONDLGNG) MECHANTSM

xEach system kau on înterrupt Sevicinq Chandting) Mechanicm.

The 0s alo provides for mechanicm for îmterrupt handling
G Ontcrrupt yector
* iterupt Vector îs a memory amhecs to Which the processor Vectors.
* The processor thansfers the proqram Crunter to the interupt Vector
es addrese on an rleirupt
Using his address, the processor kevvices that înterupt by executing
Cernesponding sR.
mechanmcm.
Vectornng îa a
prr The
provitiona în mterrupt hondling
-

The Variaus mechnicm are a llowa:

Processor Vecfoving to the SsR - VECTADDR

wwwm
address 1SR_VECTADDR
tnterrupt, a procescor Vectora to a rew
o n an
the nstruction
Counler), Which hau
*gmans that the Pc (proqiom stack or in Sme
4hat addiess on
address o neut înstructtm, Save The
and the processor load
cPU reqiste, called mk regfster
9sR-Nec1DDR înto the R to
the saved addest
Cro prevides
The Stach eínter regster af he stack
Chable etun rom he isR Using
the
provides for on o the jollosing wlays of Usirq
A procesor
mechanísm.
SsR-VECTeDDR ko»td adcdhessînq
Proces cor Vector Addtess
w

devices ike the on-chp

timer and Alb Corwerer.
Clen ha interval
4. A Aource or
Coteller, ench nternal device demupt
micro
Gn a gfven address. Each external
Source
qroup has a Seperate TSR -VECTADDR
internappiny haa Seperala isR VECTADDR

32 [Link] Scanned by CamScanner

[Link] sorte patesoy acliledre, a software insthuetion, Jor enample iN

explic ily aluo dejines he tope o inteapt and the typ of deined
lhe 9sR-v erapde ahis meckonicm 1ecults h the hovdling of n ne
Cxceplien Inndling rauine o IcRA a n idenapt ypes.
3. Sin nRM pioceasoi avchileclure the Safkwae însthetion Sali desnst
cpli
cky efine the yp o idenopt da geeratirg dblferent Yeci
address and nskead there by î a Common sp-VECTADDR fo kach

eception o Sqnal orrap qeneratrd Uinq culi însfhuection.

C . [Link] thOvin ncomnV.d Arlroee
 A qoup 9nterrupt Souices havinq
m ww
Common YectorAcblress
A Souce qroup în The haid hare may have the Same Isr-vEcADDe
J
There aie two types of handling mechanisms în processor hadWare.
The procescor anding mechanitm provi des fr fekhing its the Pt cither.
h e aeR inctructien at the sR -vECTADDR 0r
Gi)The SsR addiess tom the byles at the 9sR -VecTADDR

Soterrypr Vecfor Tabe-Splem uftware deciqner must proide Jor

address
specifyinq the byles at each
isR- VEC1ADDR

*The bytes are or either isR shnt

cade or sump mshuction to the 2«R

to the fall code

arst [Link] sR shat cade With call
the 9sR or Jor fetching the bytes indinq he 9cR acdress

classificatien eanteupt
Jotlices în a suslom.
There are three types f nderupt Pc and etror
enor în a

4. Non- maikale Eamples ore RAM pa

:

2ero. These must

be ericed
Sinterupts ke division by Which Sewlee may
Maukable
thase
olemups are or
. Maskable : GsRa b eecuted hat
disable to let kigh rihy
be temperonly
Uninterupted.

33 [Link] Scanned by CamScanner

Jew clack cycles ofler

klheo defined o othin
3. [Link] onky
resek: Fan eample, an eulernal inteuu , xSR@ itemapl în 6eHeu.
Ra inttenupk is non- makade cnly when defined co Arthin few
Cleck Cyele ofler eot ctt s tetet

Multiple wSntevrupta
Mulliple
w wm w
inteuupt Callu each ewance o
Sources,
When Thre are multiple înterrupt bit
qoup) is Tdentifiable rom
a
Scurce (or Cource
Grmenupt 4ron a

in the status reqister andlo

in he îPR (anterrupt -perdin
vesistor)
Succesio) Caue hígner priofnty
There can be lerupt Se ice cals m
sources activat în sucession. Then
retun som hic
TnrtCrupt
isR.
prioty' sR Gs to Jower príorhy pereinq
Uhder stand tuwo mterrupt Servfce mechants ms
Let us procestor

or the Coue mullple Toderuj

between routihe cliversion
processos do net piovicle for
o-
4. erlain
itevrupls and pesumu 1hat all înderuptG f priofity|
to hichcrpriofy mauleed tnl the
routîne are
greater than fhe precenlly ranninq
ercd of the outine.
derion to higher
permat în- etuen routineOrder
a. Certaîn protescns to prevent diverstoo
priouny [Link] procesco1 provicle ,n ffoning
 routtne
greaterhan the precently ranning
erd of the 1outine. divesion to higher
a Certaîn potessors permi in - hetween routine diversiro
scors piovicle ,în Order to prevent
prionty nterrupts. These prote as llous There
îs provifoning dor
mechanicm
n beteern , a levels [Link] yroces
mauktg o all slenupli by
a píîmany
nelectiye diversion by proviAtoninq mnq
G1 alo provicians
level
he merrupt envicelectvelyby secondary btk.

34 [Link] Scanned by CamScanner

Haid hlare Aergnecd priortiec

here aéigoed phioiry Order by havdlulare

s

*ARM pavides or too types of external îmenupt surees(rxquest)

GRaA and F1Qs ( Jast oterrupt eauerk)
n Cder of terrupt Vecor addrecs
*8o51 prowicles Jo pidity Oder
douen address ha highest and hiqher ha the Jouoer prronity.
Orcder accading to int*
Inttrup in Cxg6 are acfqned pYiorrty
and a25
mupt-fypes rterrupt of type 'o* ha hiqhect prionty
haa Jouwest ossigned pirty.
Divect Memory lccessA
wwW

& Used to transfer lata blo hard dik sustem memay.

The DMA
amount data from a peñphe
Nhen the ab's are needed or large
adoiecs îo the &ystem o1 Jauge amount
-

ral device to the memay

the %'s, the mcriupt baud
clata to be transferred by
-

mechantcm s not sulable.

malli- byte data set or a tust ol data ar
A DMA facilitata a
erternal device and Suskem or
a block o deta tiancjer blw the
blw two surtem.,
Grhroller) data hansfcr Occuns effMe+etlm
DMACPMA
The Devhce
blo the To Dev+ces
and Sustem mernory.
DMAC
nterconnecfiong Uhq the
xThe folousing -chotau the blo he pracescon
shus the buca and Controlqnals
Gt alco
OMAC and data transfeing o device.
emary
 From deccder

Memny e l e c t
PRCESSOR RD/

RAM

h a t lable
Ao-A5
Ackrowledge
D-P

Bui hold
Requect
DEVICE
To SEND

DMA
one or et CR RECEVE
controller okhestes FROM
a DMA
(DMAC), operatiON Slo BUs RAM

From
DMA
equest pMAdge
Ackroiledge decader
prt select

buses not acesible by processor dernal addrear and

System
aet+ve.
data buses cduing acknowledge
ignals betwcen the protessar, memory
FqThe busu and Contrd
and oata -
lo cdevîce.
hansfeing
DMA Coroler
to the CPU and the
CPU ackna
*The DMAc Sonds a hold request
buses are ree to Use
-oldgea thal t Seysten memny
the

aie Usually upporttd

în DMA Operat+ons.
Thiee mocles
then releaue 1o bus hold on the
al a fime and
C) STngle ttancfer
Suslein bus after each hanfer.
and releaxe ot
then the 9o beu
time
Bust tans-fer aB
a
7)
bus Aturst may be ofa few abhyles.
ho on the skem the
the releaue of the 9o bus hold m
C7) Bulk trancfer and
Syrtem bu4 Only afbr the transfer s Cowpletcd.
Ose DMAC
ww
lhenever a dMa request is made to the OMAC or the Tlo's,
the Drnc îs fis tnitialized. ît * piocqrammed or
4) read or Nite
() mode (bytee, bunst bulk) ol DMA thanier
or

byterto be ttadetered and

() Total No.
(y) stavting memy address
* Whenever a DMA request by the
erjernal derîce s nmade o the
MAC at
the DM4 transfera by
DMAC, The CPU s equesied at the erd to the
the stan tb inriate the DMa
and notidy
end of the DM by DMAC.
TN DrmadrmrmniAfnto-malliple Channels.
 A devfce may have multile
A sylem ho no of physical devîces,
diver.
each cevice functim requres a
unctims
device are au tllows.
în a
*ELamples of multiple functions
(G)A fmer device perfoms timînq Functions
a well au Counting
al» pertams the delay funetion
and perfodic Cyatt
une [Link]
Calls.
transmf as uwell as receive
6F ) A transeiver device well as
modsnu deice ha tansrontling au
Ct?) Voice- dala fon
for Voice, fax a well data.
as
receiving unctiona
a

fatures (Grtertace) to tbe

*Thecrets hoolbuing a stuare
layer
)The dier provides
dete: Wben runnîng an applieadion
opplication and actual thl taarlates
the dedces are Ued.A drver provides a routine
The o a delice unction the applcatien.
E-For maíling &ulem blo dayers, Netuok idertace Caid ed
37 [Link] Scanned by CamScanner

GFThe diver -acilitales he e device ht eerutinq andie 3sR:

or -lunetico can them
lhe
Cimple Commands rom a lak
availade fo aiting the cales,
device. Once a diver -unclion tt
neecd to knod anything amut
the applicntion developrr docs nol
the mechaniom,oddress, rgislersbit and laqs
Ued hy the
cdevice
Set to tick every to, oooL4.
EThe System clock s to be
level lanquane are Ucel în hich
Geneic device díver Juncl ons în high
*
Qpen, close,
read, krike,
evel language proqvam.
The funclims are

tcten ,acept elc.

Understarding
proqramminq m atsembly needa
an
* Device driver LsR
addretseA o the
buses and the
t h e processor, &ystem and alo
ceice regîsker în the Specèfic hardare.
Wtinq phyeîcal device Diving GsRA n a yrfem
Vatual Device diers
Pncllel pont drîver.c în a Sytte
> Seríal pmt criverc tn a Syctem
evice dñvers for 2nternal proqrammable Tming devices
Cinui anternals au device divers and Netuonk functims.
 Toqtming n embedded c
vm
* hlhenever the Convential 'e' lanquaqe and t eutensioms are
Embec
Syctem»,7t & refened
a
dded
Used oProgramming embe

cproqram.
Dek fop applicatie) devebpmen Uing
"e'
language de a partiular
oDeuktop
platfamer
cornputers Cuntain NEinq mem ery n the ronge
i
Mgb
and storage mem t h e range oergaytes.
Embedded sstemt are iited in wkich both stsrage and
lor king mernory recource.c.
38
[Link] Scanned by CamScanner

'vla 'Embecdoled e':

*'c% a Hall struckured bll defhed and standardieed generaf
purpece programming Janguage uth erden+ve kit manipulafdn
Suppt
'c'ofer a Combintien o the teaturea o he level danguage
Ond ascemaly and helps o hard lare access proqramminq a
hlell a buiness packaqes
developmerki
The Convemimal 'e' danguage follouh ANe tandard Gund- and t
Tncopouates orou brary tie Jor dlvernt cpratinq yebems
N
A plat arm (os) tpecefie aplicatien, knouun au Cempiler is Oxed
the Caonver sin o program hlitten îm'e' to the target

processor Specific binaryrle

Hence platfrro pecife development
Concdered a Subet Converntional 'e'
Embeded 'e' Canbe a

lanquage all 't'nshucttms and încGpaates a few

* Embeddkd e'suppri
Harget proressor Specttre Junchions/hsthuctions.
The Gmplementatfian taxget processor /controler speite fanefions
well oa 1he
deptnds up the procescor fcantroller oa
nstruchons on

unpported Cras Cormpiler for the part cutas Embedded

'e'bnquage.
the
A Cofruare proqram Galled cross - Comprler ' s Used for
to targeF prore
Conversonoproqrama ttten o Embedded '
ctan/ Cintroler apecijie fnchuelfons. (mackne larguage)
Thectandard ANs1'e' ltbray mplementaion îs aluays
tarlored t the target procesSor Codtraller liaan tles n
Embedded 'e'