Advanced Microprocessor
Architecture
Asst. Prof. Sunil K. Vithlani
Email id: [email protected]
BOOK
• Text Book:
1. Microprocessors and Interfacing: Programming and hardware
(Second Edition) - By: Douglas V. Hall
2. Parallel Computers – Architecture and Programming – By: V.
Rajaraman & C. Siva Ram Murthy
• Reference Book:
1. 8086 Programming and Advance Processor Architecture - By:
M. T. Savaliya
8086 micro processor
History of Microprocessors
8086 Overview
• Introduced in 1978.
• Total 40 Pins.
• Address Bus of 20 bit can access up to 220 memory locations (1 MB).
• Address ranges from 00000H to FFFFFH
• Data Bus of 16 bit.
• Consumes Low Power (i.e. 360 mA on 5v).
• Clock Frequencies of 5,8 &10 MHz.
• Contains About 29000 Transistors.
• It has more than 20,000 instructions.
• Provides fourteen 16-bit registers.
• 8086 is designed to operate in two modes, Minimum and Maximum.
8086 Architecture
8086 Internal Architecture
1. BIU (Bus Interface Unit).
2. EU (Execution Unit).
• BIU contains Instruction queue, Segment registers,
Instruction pointer, etc.
• EU contains Control circuitry, Instruction decoder, ALU,
Pointer and Index register, Flag register, etc.
Bus Interface Unit (BIU)
1. It provides a full 16 bit bidirectional data bus
and 20 bit address bus.
2. It sends address of memory or I/O.
3. It fetches instruction from memory.
4. It reads/writes data from port/memory.
5. It supports instruction queuing.
6. It makes 8086’s interface to the outside world.
7. The BIU uses a mechanism known as an instruction stream queue to implement a pipeline
architecture.
8. If the BIU is already in the process of fetching an instruction when the EU request it to read or
write operands from memory or I/O, the BIU first completes the instruction fetch bus cycle before
initiating the operand read / write cycle.
9. The BIU also contains a dedicated adder which is used to generate the 20bit physical address.
Execution Unit (EU)
1. It is responsible for decoding and executing all
instructions.
2. It extracts instructions from the top of the queue in
the BIU.
3. During the execution of the instruction, the EU tests
the status and control flags and updates them based
on the results of executing the instruction.
4. If the queue is empty, the EU waits for the next
instruction byte to be fetched and shifted to top of the
queue.
5. The EU accesses the queue from the output end. It
reads one instruction byte after the other from the
output of the queue.
6. It tells BIU from where to fetch instructions or data,
decodes instructions & execute instructions.
8086’s Fourteen 16-Bit Registers
ES Extra Segment
BIU registers
(20 bit adder) CS Code Segment
SS Stack Segment
DS Data Segment
IP Instruction Pointer
AX AH AL Accumulator
BX BH BL Base Register
CX CH CL Count Register
DX DH DL Data Register
SP Stack Pointer
BP Base Pointer
EU registers
SI Source Index Register
16 bit arithmetic DI Destination Index Register
FLAGS
Instruction Queue
• It is of 6 Bytes.
• To increase the execution speed, BIU fetches as many as six
instruction bytes ahead to time from memory.
• It operates on the principle first in first out (FIFO).
• Then all bytes are given to EU one by one.
• This pre-fetching operation of BIU may be in parallel with
execution operation of EU.
• It improves the execution speed of the instruction.
Registers of 8086
• Intel 8086 contains following registers:
• General Purpose Registers
• Pointer and Index Registers
• Segment Registers
• Instruction Pointer
• Status Flags
Registers of 8086
• General Purpose Registers
• Each of these 16-bit registers are further subdivided into two
8-bit registers.
AH AL BH BL CH CL DH DL
AX BX CX DX
• Pointer & Index Register
• Following four registers are under this category:
1. Stack Pointer (SP)
2. Base Pointer (BP)
3. Source Index (SI)
4. Destination Index (DI)
Registers of 8086
• Segment Register: There are four segment registers in Intel 8086:
00000
1. Code Segment Register (CS)
2. Data Segment Register (DS)
3. Stack Segment Register (SS)
4. Extra Segment Register (ES) Code segment (64KB)
• The memory in an 8086/88 based system is organized as segmented Data segment (64KB)
memory.
• A segment register points to the starting address of a memory Extra segment (64KB)
segment.
• The maximum capacity of a segment may be up to 64 KB.
Stack segment (64KB)
• The CPU 8086 is able to address 1Mbyte of memory.
• The Complete physically available memory may be divided into a
number of logical segments.
FFFFF
Code segment (CS)
• It is a 16-bit register containing address of 64 KB segment
with processor instructions.
• The processor uses CS segment for all accesses to instructions
referenced by instruction pointer (IP) register.
• CS register cannot be changed directly.
• The CS register is automatically updated during far jump, far
call and far return instructions
Data segment (DS)
• It is a 16-bit register containing address of 64KB segment
with program data.
• By default, the processor assumes that all data referenced by
general registers (AX, BX, CX, DX) and index register (SI,
DI) is located in the data segment.
Stack segment (SS)
• It is a 16-bit register containing address of 64KB segment
with program stack.
• By default, the processor assumes that all data referenced by
the stack pointer (SP) and base pointer (BP) registers is
located in the stack segment.
• SS register can be changed directly using POP instruction.
Extra segment (ES)
• It is a 16-bit register containing address of 64KB segment,
usually with program data.
• By default, the processor assumes that the DI register
references the ES segment in string manipulation
instructions.
• It is possible to change default segments used by general and
index registers by prefixing instructions with a CS, SS,DS or
ES prefix.
Concept of Segmented Memory
Advantages of Segmented memory Scheme
• Allows the memory capacity to be 1Mb although the actual addresses to be
handled are of 16 bit size.
• Allows the placing of code, data and stack portions of the same program in
different parts (segments) of the memory, for data and code protection.
• Permits a program and/or its data to be put into different areas of memory each
time program is executed, i.e. provision for relocation may be done.
• The segment registers are used to allow the instruction, data or stack portion of
a program to be more than 64Kbytes long. The above can be achieved by using
more than one code, data or stack segments.
Instruction Pointer
• The Instruction Pointer (IP) in 8086 acts as a Program Counter.
• It points to the address of the next instruction to be executed.
• The IP always references the Code segment register (CS).
• The value contained in the instruction pointer is called as an
offset because this value must be added to the base address of the
code segment, which is available in the CS register to find the 20-
bit physical address.
• The value of the instruction pointer is incremented after
executing every instruction.
• This is done during the Fetch Cycle.
20 –bit Physical address calculation
IP
4 CS 3052 0000
Inserting a hexadecimal 0h
Code segment
30520
with the CSR or shifting the CSR
four binary digits left
(offset)
30520h(CS) Segment Address shifted four times left
+0000h(IP) Offset Address
30520h Physical Address
4251F
Important Questions
• Can we start segment from any address in the 8086 memory
map?
• The segment can be started from only the addresses having
lower four bits 0.
• Such addresses are
00000h,
00010h,
00020h,….,
FFFF0h which are 16 bytes a part.
Segment and Address register combination
• CS:IP
• SS:SP SS:BP
• DS:BX DS:SI
• DS:DI (for other than string operations)
• ES:DI (for string operations)
Questions
1. If DS=1000h, SS=2000h, BX=1000h, BP=2000H, then
instruction mov AL,[BP+1000H] will move the data from
which physical memory location?
2. In 8086, starting address of memory segment can be
00009H. State true/false and justify.
3. Two different logical addresses can point to the same
physical address in 8086. State true/false and justify.
Status Flags
• Status Flags determines 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
the current state of the
accumulator.
OF DF IF TF SF ZF AF PF CF
• They are modified
automatically by CPU
after mathematical
Carry Flag
operations.
Undefined Parity Flag
• This allows to determine
the type of the result. Auxiliary Carry Flag
• 8086 has 16-bit status Zero Flag
register. Sign Flag
• It is also called Flag Trap Flag
Register or Program
Interrupt Flag
Status Word (PSW).
Direction Flag
• There are nine status
flags and seven bit Overflow Flag
positions remain unused.
Flag Register (PSW)
• 8086 has 9 flags and they are divided into two categories:
1. Condition Flags
• CF- Carry Flag It is set if carry out of MSB.
• PF- Parity Flag It is set if result has even parity.
• AF- Auxiliary Flag Used for BCD.
• ZF- Zero Flag It is set if result is 0.
• SF- Sign Flag It is set if result is negative.
• OF- Overflow Flag It is set if signed result is out of the range.
2. Control Flags
• TF - Single step Trap Flag It is to be set if single step mode (debugging) is needed.
• IF - Interrupt Flag It is to be set, for allowing or prohibiting interruption request.
• DF – Direction Flag
• If set, string instruction automatically decrements the address (string data transfers proceed
from high address to the low address.
• If cleared then the index registers will be auto-incremented
Flag Register (PSW)
Pin Diagram of 8086
Min Max
Mode Mode • AD15-AD0: These are the time multiplexed
memory I/O address and data lines.
• A16/S3,A17/S4,A18/S5,A19/S6: These are the
time multiplexed address and status lines.
• When ALE is high the multiplex bus contain
the address bits and when it is low the
multiplex bus contain data and status bits.
• The S4 and S3 combination indicates which
segment register is
S4 Pin S3 Pin Indication
0 0 ES
0 1 SS
1 0 CS or None(0000h)
1 1 DS
• S5 reflects the contents of the IF flag.
• S6 is always held at 0 and S7=1, indicates
that an 8086 is controlling the system bus.
Pin Diagram of 8086
Min Max
Mode Mode • BHE (Bus High Enable)/S7: The bus high enable is
used to indicate the transfer of data over the higher
order (D15-D8) data bus as shown in table.
BHE Pin A0 Pin Indication Data pins used
0 0 Write/Read a word at an AD15 – AD0
even address
0 1 Write/Read a byte at an AD15 – AD8
odd address
1 0 Write/Read a byte at an AD7 – AD0
even address
1 1 None None
• TEST: This input is examined by a ‘WAIT’ instruction.
If the TEST pin goes low, execution will continue, else
the processor remains in an idle state (wait state).
• CLK: Clock Input: The clock input provides the basic
timing for processor operation and bus control
activity.
• MN/MX: The logic level at this pin decides whether
the processor is to operate in either minimum or
maximum mode.
Memory Interfacing with 8086
1. Read a byte from even
address
• MOVE AL, BYTE PTR [0000h]
• Here A0=0, so enable even
address bank.
• BHE=1, disable odd bank.
• Data will be placed on D0 – D7
• One Machine Cycle
Memory Interfacing with 8086
2. Read a word from even
address
• MOVE AX, WORD PTR [0000h]
• Here A0=0, so enable even
address bank.
• Data will be placed on D0 – D7
• BHE=0, enable odd bank.
• Data will be placed on D8 – D15
• One Machine Cycle
Memory Interfacing with 8086
3. Read a byte from odd
address
• MOVE AL, BYTE PTR [0001h]
• Here A0=1, so disable even
address bank.
• BHE=0, enable odd bank.
• Data will be placed on D8 – D15
• One Machine Cycle
Memory Interfacing with 8086
4. Read a word from odd
address
• MOVE AX, WORD PTR [0001h]
• Here A0=1, so disable even
address bank.
• Address: ds:0001 (Lower byte)
• BHE=0, enable odd bank.
• Data will be placed on D8 – D15
and copied in AL
• Address: ds:0002 (Higher Byte)
• A0 = 1, so enable even address
bank
• Data will be placed on D0 – D7
and copied in AH
• two Machine Cycle
Common Signals in Both Mode
Name Function Type
AD0-AD15 Address/ data bus Bidirectional
A16-A19 / S3-S6 Address/status Output
BHE /S7 BHE (BUS High Enable) Output
MN/MX Mode Control Input
RD Read control Output
TEST It is examined by the "WAIT" Input
instruction.
READY Wait state control Input
RESET System Reset Input
NMI Non-maskable interrupt Input
INTR Interrupt Request Input
CLK System Clock Input
Vcc +5V Input
GND Ground Input
Operating Modes Of 8086
• 8086 microprocessors can be configured to work in either of the
two modes:
1. Minimum mode
• Pull MN/MX to logic 1
• Typically smaller systems and contains a single microprocessor
2. Maximum mode:
• Pull MN/MX logic 0
• Larger systems with ore than one microprocessor.
Minimum Mode signals
Pin No. Name Function
24 INTA Interrupt Acknowledgement
25 ALE Address Latch Enable
26 DEN Enable Transreceiver, - used to
separate data from the address/data
bus.
27 DT/R Decides the direction of data flow
through the transreceiver.
When it is high, data is transmitted
out and vice-a-versa.
28 M/IO Memory or I/O operation
29 WR Write control
30 HLDA Acknowledge of HOLD
31 HOLD External devices are requesting to
access the address/data buses.
Maximum Mode signals
QS1 and QS0 :
• These are queue status signals and are available
at pin 24 and 25.
• These signals provide the status of instruction
queue
QS0 QS1 Status
0 0 No operation
0 1 First byte of opcode from the queue
1 0 Empty the queue
1 1 Subsequent byte from the queue
Lock:
• When this signal is active, it indicates to the other
processors not to ask the CPU to leave the system
bus.
• It is activated using the LOCK prefix on any
instruction and is available at pin 29.
Maximum Mode signals
S0,S1,S2:
• These are the status signals that provide the
status of operation, which is used by the Bus
Controller 8288 to generate memory & I/O
control signals.
• These are available at pin 26, 27, and 28.
Following is the table showing their status
S0 S1 S2 Status
0 0 0 Interrupt acknowledgement
0 0 1 I/O Read
0 1 0 I/O Write
0 1 1 Halt
1 0 0 Opcode fetch
1 0 1 Memory read
1 1 0 Memory write
1 1 1 Passive
Maximum Mode signals
RQ/GT1 and RQ/GT0:
• These are the Request/Grant signals used by the
other processors requesting the CPU to release
the system bus.
• When the signal is received by CPU, then it
sends acknowledgment. RQ/GT0 has a higher
priority than RQ/GT1.
Maximum Mode Connections
Minimum Mode Memory Read Cycle
Minimum Mode Memory Read Cycle
Minimum Mode Write Cycle
