sation - Switching Power Dissipation, Short Circuit Power Dissipation, Leakage Power Dissipation, Glitching Power Dissipation, Short Channel Effects -Drain crower end Punch Tough, Sorfae Scattering, Velo Saturation, Impact Ionization, Hot LEARNING OBJECTIVES ‘ ign Induced Barrier Electron Effect. Need of Low power circuit de: Switching power dissipation and Short circuit power dissipation in CMOS circuits Expression for short circuit power dissipation in CMOS logic gates Leckage power dissipation, Reverse diode leakage current and Sub threshold leakage current Glitch power dissipation, and concept of short channel effects Drain-induced barrier lowering, punch through, velocity saturation, surface scattering phenomena: in short-channel effect No 9°09 4 9 Impact ionization and hot electron effect INTRODUCTION wnt challlenge in VLSI design due to decreasing feature size and increasing chip Power contumption has been a promis denitty and operation frequency. The IC's high power consumption hinders their usage in portable systems. It also causes overheating, lowering performance and chip life. The need for portable communication and computer devices has raised the need to optimize chip power consumption. Therefore, low-power dasign Is a vital technology in today's semiconductor Industry. ‘SPECTRUM ALL-IN-ONE JOURNAL FOR ENGINEERING STUDENTSLOW POWER VLSI DESIGN [JNTu. HY! ER, by yy PART-A SHORT QUESTIONS WITH SOLUTIONS What is the need of Low Power VLSI? Model Papar-t, Qi(a) at. Ans: Power consumption has in VLSI design due to decreasing feature size and increasing ‘and operation frequency. The IC’s high power inders their usage in portable systems.\It also formance and chip life. been a prominent ohallenge chip density consumption hi causes overheating, lowering per ‘The need far portable communication and computer devices has raised the need to optimize chip power consumption. “Therefore, low-power design is a vital technology in today’s semiconductor industry : (Q2. What are the sources of power dissipation in conventional CMOS digital circuits? Ans: In standard CMOS digital circuits, the average power dissipation can. be divided into three types, which are as follows: 1. Dynamic (switching) power dissipation, 2. Short-circuit power dissipation, and 3. Leakage power dissipation. 4. Glitching power dissipation. This is a special case of, Q3. | Whatis Glitch and Glitch power dissipation? * Model Paper, 119) Ans: Gliteh Alitch is any unwanted pulse at the output of a digital circuit. In other words, a glitch is a small spike that happens at the output of a digital cireuit before the output reaches its steady state. _ Glitch Power Dissipation Giitching power dissipation is the power consumed by the glitches. In other words, glitch power dissipation is the power dissipated in the intermediate transitions during the evaluation of the logic function of the circuit. Q4. "What are two most significant leakage current components observed in a MOSFET? Ans: Model Paper-2,a1() ‘The two most, significant leakage current coriponents 1, Reverse Diode leakage Current a; Reverse diode leakage current is one pf. significant leakage current components ta BF ng intly to leakage power dissipation, yy" the pn-junction between the drain and the het transistor is reversely binsed, reverse diode il occurs. In other words, reverse saturation extracted from the power supply by the revere, + drain junction. fi 2. Sub Threshold Leakage Current ‘Sub-threshold current js a type of leakage curren, [Link] CMOS circuits This current is produce the diffusion of carriers between the source and QS. What are short channel effects? List fiy different short channel effects. "eo Papers ay Short-channel effects are a’set of events'that-ccag when the MOSFET"s channel length gets closer to the widh of the space charge tegions of the source and drain junctions ny Ans: List of five different short channel effects are 1. Drain-induced barrier lowering and punch tows 2. Surface scattering 3. Velocity saturation’ 4, Impact ionization 5..__ Hot electron effect. 6. What are adverse effects caused by hot cause! by hot electrons effect. Model Paper associated with hot cartier efit pass: A shift in threshold vol@8s jeakage curen’s Ans: ‘A few of the adverse affects ‘om MOSFET behavior encomy reduction in transconductance, additional I instabilities and excess noise. through z Q7. _ Whatare the methods to reduce pune! effect? Ans: lode Paper reduced by incre ‘The punch through effect can b the dégree of doping in the transistor and’ soutce depletion regions would case, and no parasitic current path will form: 0 to reduce the-effect of punch through are, use of sP# constrained dopant implantations, such as (a), Halo or pocket implantations and 1. The body (bulk). ‘a is yinimized be mini os ial observed in a MOSFET transistor are, (WARNING: XeroxPhatacojving of is book io CRIMINAL act: Anyoo found guilty LIABLE to (6) Delta doping. «UNIT-1, (Fundamentals) | PART-B\ ESSAY QUESTIONS WITH SOLUTIONS : 4.4 Nezo ron Low Power Cincurr Design What is the need of Low power circuit design? as. Explain. An “There has been a lot of progress in low-power design ser the last few Years to Keep power consumption (and heat ever ation) to a minimum in very-high density VLSI chips. sn driving force behind the development of high-density Tus chips is portable devices such as smart phones, tablets, uh memory devices, handheld mobile telephones, personal Jfaital assistants (PDAS), and laptop computers. Because of dieer-decreasing feature size and increase in chip density, ‘ver consumption has become a big issue in high-density Fri design’ The use of integrated circuits in portable systems je constrained due to their excessive power dissipation. Porable devices need very low power consumption (and dissipation) along with high chip density and high throughput. Thus, low-power digital integrated circuit design has evolved asa highly active and quickly emerging field of CMOS design. In high-performance digital systems, such as micro- processors, digital signal processors (DSPs), and other Epplications, the chips have high clock frequencies. Ifthe clock fequency of the chip increases, then the power dissipation of the chip, and thus the temperature, will increase linearly. ‘To control the temperature‘levels, the chips need specialized and costly packaging and cooling arrangements, which would result in a further escalation of the system cost. An alternative solution to this issue isthe use of a low-power VLSI design. ‘Another problem that indicates the need for low- power design isthe reliability of VLSI chips. There is indeed 2 significant connection between the peak power dissipation of digital circuits and the reliability of VLSI chips, such as electron migration and hot-carrier induced device degradation, Further, the thermal stress generated by heat dissipation on the chip is the'main reliability problem. Therefore, to enhance the reliability of VLSI chips, their power consumption is reduced Using low-power design fechniques. 4.2. Sources of Power Dissipation-SWITCHING Power Dissipation, SHoRT Circuit PowER Consider the circuit illustrated in Figure (1) that demonstrates how dynamic power dissipation occurs during switching. In this circuit, a two-input NOR gate is used to operate two NAND gates, which are connected together by interconnection lines. The total capacitive load atthe output of the NOR gate is composed of three. components: 1... The output capacitance of the NOR gate itself, 2. The total intereonnect capacitance, and 3. Thé input capacitances ofthe gates that are being driven, Power consuming transition at the ‘output node, H Figure (1): NOR Gate Driving NAND Gates ‘The output capacitance of the NOR gate denoted as C,,., is primarily made up of junction parasitic capacitances, which are formed by the drain diffusion areas of the MOS transistors, in the circuit and contribute to the overall capacitance of the NOR gate. The interconnect lines that connect the gates together make contributions to the total interconnect capacitance and is denoted 85 Cyescnang? THE input capacitances denoted a5 Copy, are primarily caused by the gate oxide capacitances of the transistors that are linked to the input terminal. ‘[Link] Logic Gate in Generic Form As illustrated in figure (2), a CMOS logic gate that undergoes an output transition can be described by the nMOS network, pMOS network, and the total load capacitance linked to its output node, Figure (2) illustrates the generic (basic) form of a CMOS logic gate. Dissipation, Leakace Power Dissipation, | v.—{ 1.5 | Gureino Power Dissipation. m2 = Power consuming 8. Explain switching power dissipation in CMOS | Ve] Netork | transition or me | oe output node "Ans: Model Paper, 230) Me . Switching power dissipation is also known as dynamic Caan + BC, +2C, | Power dissipation. ‘The switching power dissipation occurs || Ys] nMOS ae cian > whenever thee isa switching in the output of the CMOS logie |”, __ network _ 8. nother words, power dispaton occurs when the ut _ Ips ofa CMOS logic gate makes a transition (HIGH-LOW | LOW-HIGH, CMOS. circuits generate dynamic’ power = _ dissipation by the charging and discharging of capacitances. Figure (2: Genoric form of a CMOS Gate ‘SPECTRUM ALL-IN-ONE JOURNAL FOR ENGINEERING STUDENTS, aaan 4 LOW POWER VLSI DESIGN LINTU-HYDERABAn, iynami i i jodie waveform with preferably yoy dissipation of the CMOS logic gate, driven by a peri preterbly ae and Pieces ts ‘etermuned by calculating the energ} needed to charge up the output node (V.,) to Yoo id are 4 the total output load capacitance to ground. Mathematically it is expressed as, anne Pas 4 lia Va -Gont Heat oh ona Ca Hea] L v0: ‘The equation ae 4 dynamic power consumption in CMOS logic circuits is obtained by simniite fei in equation (1). s Pat FG bo ‘islar gy Pog = Cont VBS =) ales m i f the. uation (3), itis clear that, the average dynamic power dissipation is related to the square of the power supply ie So, lowering the [Link] the power source will reduce power consumption significantly. The average dynany, power dissipation is exactly proportional to the load capacitance C,,, henge lowering C,,, will also decrease power dissipation Q10. Explain how switching power dissipation gets affected by reducing the power supply voitagé’V,_. Ans: ‘The expression for dynamic power dissipation ‘P" is given as, P= CeVipf * Where, - Cy Total output load capacitance Yoo - Power supply voltage J Frequency of transitions at the output From eauation (I), iti clear that, the average dynamic power dissipation is related to the square of the'power supply voltage Vpo. So, lowering the voltage of the power source will reduce Power consumption significantly. However, the inevitable aL Figure (1) ’ itt al yom < pitches. In other words, glitch Powe jissipation is the Po com i i cuit, The power consumed is directly ‘umption. Glitch ion is the power. ! cation ofthe Tope Function of re aie to the numberof transitions atthe input O° iate; these unnecessary transitions increase PO oisually amounts to about 20% of the overal| Port a vmption ofthe chip, and even 7076 some typical poe binational adder. For instance, consides ‘he Fetal eiruitustrated in figure “The OR gate produces 3 ¢ it nse of the output conta ng and one falling. This is 9 glith ‘with a combined width of fa gate is equal to the num ing signals at the gate’s Glitching power dissipatis ssipaed in the intermediate transitions during I cases, such as ber of arriving si “differential path ‘The transient respo rae The numberof edges in the transient response ‘at the output o h ri ani umber of ansitions) The maximum Sot ne vival time of signals atthe inputs of a B16 'S called iar ind sas the maximum width ofthe posible ilitch atthe circuit output: ered ad Figure (2) One ofthe earliest methods to reduce glitch powe! Wa path balancing. ste inputs, glitches are produced. The concert ‘behind this approach is to avoi eso that at any specified gate in the digital evel the signals arrive at ip ot the digital circuits illustrated in igures @) 2% (a, In Bgure (3), the signals arrive atthe gates at tltehes, Restructuring the circuit, as seen in Figure (4), prevents the occurrence of glitches.” AD .ces in the arrival times of signals at jancing the delays of the ibed with the Due to differen id glitch generation by ball yput at the same time. This is descr {ferent times, causing gure (3) 4.3 Swot Guanes Errects - Drain Inpuceo BARRIER Lowerine AND Punch THROUGH, SURFACE SCATTERING, Hor Exectron Errect % we ite Vetociry SATURATION, ImPpacT FONIZATION, | What are short channel effects? Explain in brief about the problems caused by short channel effects. ‘Mode! Paper-2, 23(b) Ans: ‘cur when the MOSFET’s channel length gets closer to the width of ~Short-channel effects are a set of « set of events that oce we regions of the'source ang drain junctions. Under this condition, a limitation is imposed on electron drift characteristics in the channel ar rodeo ote tS a - nd ieahold voltage is modified due to the shortening channel length. As a cons Peering pe no ne cn roel ee sacs, ate en a en oacriaastanes eee erect ©)" SPECTRUM ALL-IN-ONE JOURNAL FOR ENGINEERING STUDENTS AA oy——— = LOW POWER VLSI DESIGN IJNTY 144, The reduced threshold voltage makes it harder to totaly switch off the transistor. Electrostatic inary source and drain causes the gate to become inefficient due tothe DIBL effect. The current drive is reduced by yeh The power sipation is icressed bythe leakage curren. nteased surface seatering reds charge cane output current. Aside from these considerations, impact ionization and ot carier effects damage MOSFET pen the transistor to behave differently from long-channel devices. mm, Q18. Explain the “drain-induced barrier lowering” short-channel effect. Ans: : wing, Drain-nduced barrier lowering (DIBL) isa shor- Vs y, ily Lat IR —F Qo n* [Inversion layer vo w Depletion c : region = 7 ea Figure (1) ‘The following isthe physical explanation why transverse ilds cause scattering and effect lateral current flow. In MOShy carriers travel via a thin inversion layer nearer the silicon surface (figure (1)), where they are subjected to numerous so vents withthe surface, especially when itis microscopically “rough”. When the channel length becomes smaller bécause or expansion of the depletion layer into the channel region, the longitudinal electric field component E, increases, and the surf ‘mobility becomes field-dependent. Because the carrier transpor is confined within the narrow inversion layer, and the sua scattering (that isthe collisions suffered by the electrons that are accelerated toward the interface by E.) causes reduction of mobility, the electrons move with great difficulty parallel to the interface, so that the average surface mobility, even for sm ‘values of £, is about half ofthe bulk mobility. Experiments have demonstrated that the mobility of electrons and holes in sili ‘can be expressed mathematically as, pet - 1+ @E gy) te Where, E,qis an effective transverse electric field, by, is the mobility without the transverse field effect, and ‘vis a factor between | and 2. ‘The above equation has a physical origin, and can be derived using Mathiessen's rule. If wO represent mobility of ca due to low transverse fields and j, represent mobility of extra scattering caused by the vertical field. Presuming that the li ‘scattering enhances with effective field, we have, Aetydi tye 7 dG t wey iy * Keg This gives us the equation we want. Q22. Explain about impact ionization and hot electron effect. Ans: : Modal Papers. 08 The issue of hot electrons has continued to increase as technologies scale down because the dinensions of the device scaled down proportionally faster than voltage. This results in higher field strengths and thinner gate oxides in the devices ‘The High fields cause electrons flowing through the channel to gain enough energy to become “hot”, The hot ex can cause impact ionization, that is, they strike the silicon atoms (in the drain) and ionize them. A consequence of this oi generation of extra holes dislodged from the drain. This causes an increase in drain current ag well as a subsiate cute “a made up of ionization-generated holes that flow towards the substrate (he transistor's most negative point), Some of produced by impact ionization can also get heated up and be injected into insulator WARNING: Xerox/Phidtotopying of this book is CRIMINAL det. Anane found ily LIABLE to face LEGAL, proceedings. 3 al‘pay gain sufficient energy 10 overcome The potential ot electrons enter the gate-oxide layer and will prod r effect of hot carriers is that they face, and get injected ino the insulator. nother words, the he atic of these effects is illustrated in figure (). Figure (1) ‘The holes and electrons entering into the oxide layer cause many i6SUSS including electron and bole ‘trapping, interface state generation, and generation of ‘bulk and “border” aps in the oxide layer. ‘These pt “hot carrier effets,” and they constitute & significant reliability challenge for MOSFETS. ‘A few of the adverse affects associat ts on MOSFET behavior ‘encompass: A shift in ted with hot carrier effec voltage, reduation in transconductance, additional leakage currents instabilities ‘and excess noise gINEERING STUDENTS >" cowenndwis ;OURNAL FOR EN aad {gpecTRUM ALLIN-ONE JLow POWER VLSI DESIGN EINTU-HY Dy ] Ry 14 (IMPORTANT QUESTIONS 7 \ ai. Explain switching power dissipation in CMOS circuits. Ans: Refer Q9. : lop, 2. Explain how switching power dissipation gets affected by reducing the power Supply voitag. ~ Ans: Refer Q10. - Inpetns Q3. Derive the expression for short circuit power dissipation in CMOS logic gates. i Ans: Refer Q12. a ‘@4. Explain Reverse diode leakage current. iS Ans: Refer. QI4. lay a5. Explain Glitch power dissipation. ey Ans: Refer Q16. ie @6, Explain the “drain-induced barrier lowering” ‘short-channel effect. S Ans: Refer QI8. : , wild Q7. Explain the phenomena of “punch through” in ‘short-channel effect. "Ans: Refer Q19. sect } @8. Explain in brief about velocity saturation in short-channel effect. Ans: Refer Q20. — Q9. Explain surface scattering phenomena occurring in short-channel effect. Ans: Refer Q21. . tet Q10. Explain about impact ionization and hot electron effect. ‘port is Ans: Refer Q22. WARNING: i 5 JG: Xerox/Photocopying ofthis book. @ CRIMINAL act. Anyone found guity is LIABLE to face LEGAL procam Ve UNIT Low Power DESIGN APPROACHES AND f Wh SwitcHEep CAPACITANCE MINIMIZATION *\ s2sce APPROACHES : Syllabus LOW POWER DESIGN APPROACHES Low Power Design through Voltage Scaling - VICMOS circuits, MTCMOS circuits, Architectural Level Approach Pipelining and Parallel Processing Approaches. SWITCHED CAPACITANCE MINIMIZATION APPROACHES Level Measures, Circuit Level Measures and Mask level Measures. LEARNING OBJECTIVES Low power design through voltage scaling System Operation of VICMOS and MTCMOS circuits Concepts of pipe lining and parallel processing, approaches aces minimization at system level, circuit level and mask level INTRODUCTION Te requirement of low-power design must be met along with equally demanding goals of chip density and high throughput. ence digital systems. The methods which are used to achieve low power consumption in We discuss system level considerations such as pipe lining and hard ware replication 9°99 9 4 ed copacita Swit Its @ major isve in high perform this uit at circuit or transistor level. (porate procesing) ‘SPECTRUM ALLIN-ONE JOURNAL FOR ENGINEERING STUDENTS:* LOW POWER VLSI DESIGN [JNTy HYDERa, -A SHORT QUESTIONS 'H SOLUTIONS List out the observations on switching power reduction. at. Ans: | “ The switching power consumption is expressed as, Naf moes P, -[ Len GK [Yooh a (On observing the equation, the average power consumption can be reduced by reducing, 7 1. Power supply voltage, V. =) 2. Voltage switching in internal and output nodes 3. Node transition factor 4___Load capacitance. : Q2. Draw the circuit diagram of VICMOS inverter, : Ans: : oda Paso ‘The circuit diagram of a variable threshold CMOS inverter is as shown in figure, _ 0.2 V in Active Mode v, . [7-92 V in Active Mode 4V in stand-by Mode [0.6 V in stand-by Mode K ‘Substrate Bias Control Circuit 0.2 V in Active Mode : { 0.6 V in stand-by Mode = OV'in Active Mode ~2V in stand-by Mode Figure + : Q3. Draw the general structure of MTCMOS. 2 Model Paper2, ai) Ans: ‘The circuit diagram of multiple-threshold CMOS inverter is as shown in figure, and. high-V, prevents subthreshold a pMos leakage in [Link] mode Mos Logic with | . high-speed operation with Jow power consumption Prevents subthreshold leakage in stand-by modea yu 2 (Cow Power Design Approaches and Switched Capacitance Minimization Approaches) 17 {Give te dela expressions ofa CMOS im ‘The delay expressions of a CMOS invereter are, Gua [2% Von ~Ys 1 “aetna “ Ce a -V foo" Yep!) 2 tut Foo Watts ‘ete a I ° & When MTCMOS technique in used? . Model Paper-t, f(b) Multiple Threshold CMOS (MTCMOS) is the technique used to decrease the ‘subthreshold current leakages and power jsinton nthe iit operating in stand-by mode jg Whats pipeting approach? Model Paper-2, Q1(b) Ast ‘he pipelining approach is method of applying a data stream in a regular manner to 8 ProseSSnK circuit in’order to pre resus in a sequential order. The supply volage can be lowered swith the pipelining approach, which saves power Gr, Whatis parallel processing approach? ps ai Model Paper 01) panel processing approach, ike pipelining, can bé used to reduce power dissipation by lowering the supply voltage. inrades-off area for lower power dissipation. Iti also known as hardware replication. the same circuit to perform the same computation on multiple data sets Parallel processing is the use ‘of multiple copies of simultaneously. Q8, What is meant by switching activity? Ans: ‘The switching activity refers to switching of circuit from on "Ge. What are the methods used for optimization of switchig activity? 1 logic 1 to logic 0 and vice-versa. “The various methods that are used to optimize o reduce the switching activity in a CMOS circuit ae, 1. Algorithmic optimization 2. Gliteh reduction 3 Gated ¢lock signals it. Whatare the various techniques used to reduce the switched capacitance or parasitic capacitance in circuit? Ans: Mode! Paper3, Q1(g) Switched capacitance or parasite capacitance is one ofthe main factors causing power dissipation in a cireit. This ‘pictance can be optimized using Various techniques at various levels. They are, L System Level: The technique used at system level to optimimize the parasitic capacitance is limiting the usage of shared "esourees among varios devices. Cireut Level: The technique used at circuit evel to optimimize the parasitic capacitance is changing the logic style to (esign a cireuit or network. Mask levels The technique used in mask level or physical design level to optimimiz the parasitic capacitance is minimiz. ing the dimensions of the transistors inthe circuit. “SPECTRUM ALLIN-ONE JOURNAL FOR ENGINEERING STUDENTS “=LOW POWER VLSI DESIGN WNTy.; “HYD, (PART-B) Essay QUESTIONS WITH SOLUTIONS” ~ 2.1 Low-Power Desion AppRoAcHES: , t 2.4.1 Low-Power Design Through Voltage. Se Q11. Explain the influence of voltage scaling on power dissipation and propagation delay, Ans: , Noting The average dynamic switching power dissipation is proportional to the square root of the power sm expressed as, ' se Pat deaV3p (01) Pa, 27 Oma Bp Sean . So, reducing V;,, will drastically reduce the power consumption. The influence of power supply voltage scaling on power consumption and delay can be observed from propagation delay expressions of CMOS inverter circuit, the fa [4% cna pe yw ed S, oe ‘ tran ptt | Pe al §, Yoo ~ Yr) | Yoo - ro] “%~. From the equations, it is observed that decrease in pawer supply voltage reduces the dynamic (switching) power dss or but increases the propagation delay. Figure (1) represents the influence of voltage scaling on power dissipation and propagation delay, B oof g ae a jes oe 50 oF 0.0 10 # 10 20 30 40. 50 60 7.0 : Power supply voltage Vig (V), Figure (1k Normalized Variation af Propagation Delay and Average Switching Power Dissipation as a Function of Vag <°” - Siee/t speed Of the circuit also depends on power supply, it also affects the power dissipation, & —‘Omobserving equation (1), it can be assumed that at a constant switching frequency or transition factor, Sumplon f reduced as quadcati function when Vp is reduced, the power® wi 4 Ifthe CMOS circuit is operated continuously at its highest frequency allowable by its propagation delay, ther frequency will decrease as propagation delay increases on power supply feduction. Figure (2) illustrates the propagation delay for various values of ¥,and Vp. 4 Ifthe threshold voltage, Vis Sealed down, then it can compensate for the propagation delay when supply voto duced. (GRRL WARNING: xeroxPhotacopying ofthis hook isa CRIMINAL oct, Anyone found guy is LIABLE to face LEGAL proceeioo®a2. Ans: 2 (Low Power Design Approaches and Switched Capacitance Minimization Approaches) 140 120 100 Normalized delay 4ob > | 20 00 10203040 50 80 Power supply voltage Vo(V) Figure (2) the delay value by factor 2 at Yap = 2+ From figure (2), the scaling of threshold value, V, from 0.8 to 0.2 reduces mnt leakages Despite of reduction in delay scaling of treshold voltage leads to smal noise margins and s ibthreshold curre in CMOS circuits Explain briefly about Variable Threshold CMOS wrewosy< circuits. Model Paper2, 4 ‘Variable Threshold CMOS (VTCMOS) circuits are designed to overcome the drawbacks of low threshold voltage valued circuits such as subthreshold leakage and power dissipation. Figure illustrates the variable threshold CMOS with substrate bias conto} circuit 02 V in Active Mode y, -02V in Active Mode 2V | 4 in stand-by Mode 0.6 V in stand-by: ote ‘ ‘Substrate Bias Me Control Circuit [Link] Active oe 06 Vinstand-by Mode “= { OV in Active Mode *|—2V in stand-by Mode Figure ‘ Ina conventional CMOS circuit ll substrate terminals of nMOS transistors ae connected with ground, whereas that of MOS transistors with power supply voltage, Voy-Fot& MOS transistor, the threshold voltage depends on substrate vot- Co : In VICMOS method, the transistors are designed wit tors are produced using a variable substrate bias control circuit. “The self-substrate bias circuit controls the body bias to achieve different threshold voltages. Us inverter is operating inactive ode then Vy of MOS transistor is 7,,~ 0 and of pMOS transistor Vay Vow In active mode, a neatly zero bias is applied. In this mode, the transistors are not affected by back-gate effect. I, operates atlow power supply and threshold voltages with high switching speed and low power dissipation. prsiei is operating in stand-by mode, the substrate bias control circuit provides low Vy for nMOS and high Vy for aes ‘SPECTRUM ALL-IN-ONE JOURNAL FOR ENGINEERING STUDENTS ith very ess threshold voltages and substrate voltage ofthese transis-LOW POWER VLSI DESIGN Lunry applied to increase threshoi deeper reverse body J Instandby m are affected by back-gate effect resulting in high threshold voltages, 7, and y & _ Imthis mod ae exponentially with increasing threshold voltages, the power dissipation d oe Asi — leakage current ae the threshold voltages can be regulated automatically in order to re i rin : Using Te process variations, This technique is referred as Self-Adjusting Threshold vnasiae on) re VTCMOS technique is ficient in designing CMOS circuits with reduced subthreshold o icheme, 4 + ae threshold values in the range of Vo low Vit requires a twin-well or triple-well CMs, pron dently control voltage in different parts of chip. oe & Italso requires a substrate bias generator tb generate the rquired substrate bias. 13. Explain in deta about Multiple Threshold CMOS (MTCMOS) circuits with necessary circu a Ans: Mode & Mulple Threshold CMOS (MTTCMOS) isthe technique used to decrease the subthreshold current leakages Son dissipation in the circuit operating in stand-by mode. : » This technique uses two transistors with two or more different threshold voltages as shown in figure. Be Stand-by ed prevents subthreshold : leakage in stand-by mode Mos . : Logie with’ | high-speed operation with Tow, low power consumption Stand-by Jf high-V; prevents subthreshold nMOS leakage in stand-by mode > In active mode, the transistors with high threshold voltage ¥, [Link] and the transistors with low threshold vola ‘operates with very less power dissipation and propagation delay. > In stand-by mode, the transistors with high threshold voltage, V,, turns OFF and the transistors with low threshold volta turns ON and the path for conducting subthreshold current leakages (originating from low threshold circuits) are cuto Advantage ‘ * Itis very simple to use and apply when compared to VICMOS. Disadvantages * In this technique, all the stand-by transistors connected in series increases the total cireuit area. > ‘This method also introduces parasitic capacitance and delay in the circuit. ~ Pipelining and Parallel Processing Approaches l i 5 ber Ok (The pipelining techniques and paralle} processing are two of the most common approa ompensate for performance loss caused by a lower supply voltage with a constant threshold voltage. 7 ‘ Q14. Explain the pipeling approach. : ' / Ra {eam Y ten 7 x Model Paper? i is ie to ‘The Pipelining approach is a method of applying.a data stream in a regular manner to a processing circuit in ode produce results in a ‘Sequential order. The supply voltage can be lowered with the pipelining approach, which saves power WARRING: octets SBMA se es od ii HBLE we edn pce a ~~ aFigaie (I) shows the single functional block that imp! timing diagram. Each ofthe input and output vectors i sam its : SUG CLRLALA volage of Vay the ical path in tis Togic block allows to ; Rees Register (8) Timing Diagram Figure (1) The dynamic power ‘consumption of this block is given by, Praance™ Cua Vo0 Sous ae Where, C., isthe total capacitance, It includes, ‘the capacitance switched in the input register array ‘The capacitance ‘switched to implement the logic function & The capacitance switched in the output register array. Now, Consider an n-stage pipelined structure witha eritical path ‘Rewister Stage 1 Register ‘Stage 2 ° that is only 1/n ofits original length as shown in figure (2). ‘Stage Wags est y= Ty a te = (a Fanetional Block Diagram ” oe are ae (b) Timing Diagram) «> i Figure Wea fl > SPECTRUM ALL-IN-ONE JOURNAL FOR ENGINEERING STUDENTS © aay win:i. a LOW POWER VLSI DESIGN [UNTy HY, YD, Here, two cases arise. : 1. Without considering the capacitance of pipelining registers 2. Considering the capacitance of pipelining registers. 1, Without Considering the Capacitance of Pipelining Registers During a single clock period, the amount of capacitance that canbe charged or discharged is reduced ¢ considering the capacitance of pipelining registers. As a result ifthe same clock speed is preserved, the votag oo to aV where a is a positive number less than 1. ea Without considering the capacitances of pipeline registers, the power dissipation of the pipelined structur : igi G Pyetg = HX SEB x foe oY? ‘nating oP AAs areslt the pipelined structure's power dissipation is times lover than it was before. The propagation structures is assumed to be equal, to calculate the value of a. On the basis ofthis, that the fllowihg must be vat naV-¥,) = a(V- v,F Considering the Capacitance of Pipelining Registers In figure (2), the logic function FONPUT) has been divided up into N stages, and a total of (W ~ 1) register amy ‘been added to the original input and output registers to make the pipeline. All registers are clocked atthe Same ras, With a lower supply voltage and the same functional throughput as the single-stage structure, the dynanic consumption of the N-stage pipelined structure can be approximated by, P, [Cea Y= DG l-VBDinew Sour et Where . C, ~The capacitance switched by each pipeline register. Then, the power reduction factor achieved in a N-stage pipeline structure is, 4 [Grtat +N A) Cg V Bp new rx Coonar-V Bo Sex C, Vi =f Sete —1y]Yooaew [df Pipelining approach has small overhead area to implement this architectural change. For the single-stage struct" transformed into a pipeline, it is necessary to add (V— 1) register arrays in total. In order to save power, this technique area . However, it increases latency from one to N clock cycles. Q15. Explain the parallel processing approach. Ans: volt Parallel processing-approach, like pipelining, can be used to reduce power dissipation by lowering the supP!Y trades-off area for lower power dissipation. It is also known as hardware replication. est! eo" ‘ Paraliel processing is the use of multiple copies of the same circuit to perform the same computation on wultipl@ simultaneously. Consider the -parallel system in figure (1), which has V identical copies of the same function units exch © plements the logic function F(INPUT). N times more capacitance is added. The clock frequency must be: me J times in order to maintain the same level of performance. Since the N capacitors (NC,,.,) have more time !° © discharge, the supply voltage can be decreased by a factor a. @ 1) | WARNING: XeroxiPhétdetifjhb at this Book is'a’CRIMINAL act"Anyone found guilty is LIABLE‘to faes LEGAL proceod ; 1 ofhes) 2 yniT-2 Lew Power Design Approaches and Switched Capacitance Minimization Approaches) 3 7 Logic Funetion F (input_l) Input CLK_I fy) Logie Input Function F (Input_1) CLK 2 fy/N) Logic Function Input. F (Input_1) CLK _N G/N) Figure (1) : 1 the registers ofthe WV processing DIOCKS f°00' the input vee~ tried clock signal is used. Since the c1O$s ‘signals to cach nsecutive sme that the input vectors arrive at the same rate, All ors ate loaded into a new register for each N-cor ‘each register per (V7.4) clock eycles, the N’consecutive input vee ao Assut tors. In order to load input register are biased by the Toys ‘each input register is clocked at factor of N since ‘new clock period inputs. fe Asaresult, ower feauency Coax tevtical path delay equals the ot ; ; asso of the parallel structure (neglecting the dissipation of the mule se ai he loge blocks operating af 2 clock frequency of It is given by, tor is increased by @ lowered until the computation time for each input ve ‘ivy, The power supply voltage can De 4 Tre total dynamic power dissip er) is equal to the ae srihe power dissipated by the input regis Uay/N) and the ating ata clock frequency Off. curput register ope Preset = Coae VB once 2M + Coe VB 200 Fo | | Cog 2. . , Ponsa” (1+ GEE] Sunt VB Fe - a) Ignoring the additional overhead, associated input routing capacitance the ‘output routing capacitance dind the capacitance roavction achievable in a N-block parallel implementation is, ofthe output multiplexor structure, the amount of power = @) ith architecture-driven voltage scaling assuming zero threshold Jning power reduction realizable wit ‘huge is given by, i . att, : Frew 2 8 Without 5 os = considering the capacitances of paralle-protessin ina a ne capacitances parale-protssng estes, the power dissipation ofthe m-parllel system can’ *Sressed as, L nciveute,, . -..@ Pret = Mowat) ap SPECTRUM ALLIN-ONE JOURNAL FOR ENGINEERING STUDENTS:Se 24 LOW POWER VLSI DESIGN Linyy, Figure @) illustrates the timing diagram of igure (I). It shows that the parallel implementation He, cycles, jut like in the N-stage pipelined implementation. Maia CLK: . - “ny Input X Tapa 2 CLK 2.2 ate. Figure (2: Timing ‘Switcneo Capacitance Minimization Approacnes - System Lever Measures, Cincutt Levei M, ano Mask Level Measures any Explain briefly about the estimation of switching activity. ‘The switching activity refers to switching of circuit from one logic Ito logie 0 and vice-versa In switching power dissipation, the power consumption or dissipation of CMOS circuit depends on switching es factor which in turn depends on Boolean function of the logic gate. 3 ‘To illustrate the concept of switching activity consider a 2 input CMOS NOR2 gate. If P, and P, are signal probabilities, where P,represents the probability of occurrence of logic 0 and P, repesi probability of occurrence of logic 1 at the output; then the probability of occurrence of power consuming transitions output is the product of these two probabilities ie., P, and P, Iths four possible state (00, 01, 10,'T1) for inputs x and y. From the truth table. ‘The probability of occurrence of power constuming transition at the output of NOR gate is, 3.1 33° = PyPy Poot oa 76 Figure (1) reprederits the state transition diagram ofa CMOS NOR 2 gate. 3/4 x 3/4 = 9116 34x 1/4 = 3/16 Vax va= 1116 7 Vax3/4= 3/16 igure (1) = Generally,-the probability. of occurrence of power consuming transition at the output of an n-input ‘eMOS Ios function of n, and is given as, : NESS oe (erox/Phatocopying ofthis book is @ CRIMINAL act: Anyone found guilty is LIABLE to face LEGAL proceedin® dg 1 Pos Sy WARNINGi ) ‘ce Minimization Approaches) NOR, NAND and NOR gates, 030 ‘Tea for XOR/XNOR gate ‘Transition probability Output transition probability 0.10 for NAND/NOR gate 0.05 0.00 2 3 4 3 6 Number of inputs Figure (2) A ‘ble to estimate the ted, then it is not poss ut transition is the jformly distribut gouty fa NOR gate has two inputs which are independent and not un probability of power consumin gccurrence of logic 0 and 1 with same probabilities. Then, the fanction of input probability distributions. a ‘where, ‘The probability of occurrence of logic I at input A= P,,, ‘The probability of occurrence of logic 1 at input B = Po Then, ‘The probability of occurrence of logic 1 at output is, P=U-P,-Pid > : ~@ From equation (2), the probability of occurrence of power consuming transition at output is given #5, Pj = PyPy rr PDP P, 1-(1=P,,) (1 Pye) AP.) Pa) . 3) ition gs a function of input probability. ‘Therefore, equation (3) represents the disttibutions and this distribution is shown in figure (3). probability of power consuming output transi Figure (3) ; : complex to evaluate the switching’ activity in multi > level feedback [Link]. So, a designer prefers CAD tools to estimate the switching: Tore, from equation (3) it ean be observed that, itis litle e ireuits involving sequential components, of any network. ‘SPECTRUM ALL-IN-ONE JOURNAL FOR ENGINEERING STUDENTS dansaay 25 ' r fn (Low Power Design Approaches and Switched Capacitan igure 2) illustrates the probability of power consuming output Transition as a'function of number of inputs for KOR.LOW POWER VLSI DESIGN [UNTy. HYD, 26 17. What are the methods used for optimization of switching activity? Explain them briefly a ‘The various methods that are used to optimize or reduce the switching activity in a CMOS circuit are, 1. “ Algorithmic optimization 2. Glitch reduction . 3. Gated clock signals 1. Algorithmic Optimization _ of data transmission. > ‘There are few methods such as Digital Signal Processing (DSP) which is applicable only for certain Applications for general purpose processing. P ° ‘One of the algorithms that ‘minimizes switching events is Vector Quantization (VQ). If this algorithm Employ: 5, salty eect algorithm instead of full earch algoritim, then it ean also optimize the nuntas nn memery a ‘multiplications and additions by a factor of 30, * * Glitches are the fast signal transitions caused due to the cairy of| Propagation delays from one block tothe oth ‘These glitches results in critical races or dynamic hazards, ‘ Iinput signals of a gate does not transit from ground to Yoo at the same time, it results in dynamic hazards I signals transit partially, it results in partial hazards. Ifthe input signals transit from ground to Kp. at the same tn no glitches occur in the output, : e ‘* The main reasof behind the occurrence of hazards is improper balance in the Jengths of paths between gates in amt ‘This leads to the improper timing or propagation delays in transmitting signals between logic blocks. Gated Clock Signals : ‘Using of gated clock signals or conditional clock Signals is another way of reducing switching activity in the netwo! % Ina network, if a particular logic block is not used for a clock cycle, then disabling the clock signal for that pt block reduces jhe switching activity. % _Imorderto design a clock gating strategy for a circuit, the flow of signals and interconnections among the blocks at ‘operations have to be analysed carefully. Q18. What are the various techniques used to reduce the switched Capacitance or parasitic capacitt™ a circuit? Explain briefly. Ans: ? wos! Switched capacitance or parasitic capacitance is one of the main faciors causing power dissipation in a cit** capacitance can be optimized using various techniques at various levels. They are, 1. «System level 2. Circuit level and 3. Mask level» 1. System Level The technique tsed ar Syste level to‘optimimize the parasitic capacitan among various devices. ©7L8Y WARNING: xeroxiPhotdcapling of this book is « CRIMINAL act. ‘Anyone found gut is LIABLE to face LEGAL ant JRO naam, Power Desi yntr-2 (Low sign Approaches and Switched Capacitance Minimization Approaches) 27 a0 are (1) illustrat . - Figure (1) i ‘es various modules using @ single bus to access CPU resources. It is a global bus structure for data sisson between multiple modules, yA. yA yh yh «Tay Ay Ay Ay Figure (1): Single Global Bus Structure for Connecting « Large Number of Modules on @ Chip since a single bus is shared among various modules, a large bus capacitance o¢curs due to following rea (i) Usage of same bus by large number of drivers and receivers. (ii) Parasitic capacitance of the long bus line. Inorder to access the bus, high amount of power is consumed to drive this large capacitance of the bus. ‘Te parasitic capacitance or switched capacitance can be optimized by dividing the single global star bus into small multiple buses as shown in figure (2). t e wT sons, Bus Interface igure (2) These multiple small buses regulate the data transmission among various tance while accessing the bus. 2 Circuit Level : The technigee used at circuit level to optimimize the parasitic capacitance is changing the logic style to design a circuit or Te tecnigue used at irl eve 0 OP erase in oad capacitance inthe ie ithe usage of age number of transistors. One tthe vo minimize this load capacitance is to use transfer gates pass-transistor logic in the place of CMOS gates, it has several limitations, in order to generate output driving capabilities in a propagation delay and power dissipation. ntrol signals which in tir fequires two inore Complérhentary modules and also reduce the switching eapaci- Even though it reduces the load capacitance, (@)Pass-gates require inverters atthe output (ii) Usage of inverters results in increase of total area, Gil) We uses dual-rail logic to generate complementary co MMOS-pass transistors. : All hese disadvantages overcome the advantage of pass-trnistor, So, a trade off must be maintained /among required 1. tnd thequed pur onssor a be on ay cas sk Level The technique used in mask level or physical sions ofthe transistors in the circuit. ‘Though small-sized transistors in a logit ‘etwork. Therefore, a trade-off must be . oo SPECTRUM ALLIN-ONE JOURNAL FOR ENGINEERING STUDENTS. 2/35 -ceptable range. 1 design level tooptimimize the parasitic capacitance is rainimizing the dimen- «circuit reduce the power consumption, it affects the dynamic performance of the. ‘naintained between power consumption and dynamic performance in mask level. =LOW POWER VLSI DESIGN [JNTU-Hyp, S St 28 a1. Explain the influence of voltage scaling on power dissipation and propagation delay, Ans: Refer QIl. 2. Explain briefly about Variable Threshold CMOS (VTCMOS) circuits. Se Ans: Refer Q12. Je Threshold CMOS (MTCMOS) circuits with necessary circuit anys @3. Explain in detail about Multip! Ans: Refer QU3. Qs. Explain the pipeling approach. és a Ans: Refer QI4 y'9 Qs. Explain the parallel processing approach. et Ans: Refer QUS. wi tC 6. isd bad benipaed wee used to reduce the switched capacitance or parasitic capacitan, Ans: Refer Q18. = ae ‘WARNING: Xerox/Photocopyinarot thip ipa: is a CRIMINAL act, Any ope found guilty is ABLE to faceEGAL proceedios-sacl (UNIT - [Link] Low-PowER | ApDERS ; atiuicn LOW-YOLTAGE LOW-POWER ADDERS ‘carry Look- Ahead Standard Adder Cells, CMOS Adder’s Architectures ~ Ripple Carry Adders, Low-Power Design ‘Techniques ~Trends of Introduction, iques Adders,, Carry Select Adders, ‘Technology and Power Supply Voltage, Carry Save Adders, Low-Voltage Low-Voltage Low-Power Logic Styles TIVES LEARNING OBJES Need of Low-voltage Low-power Adders stondord cel, schematic configurations of Fl codders asi operation of pple carry adder ands performance evatuation,glitsing problem esc heory ond operation of cary eok-heae odder bit Carry Look-Ahead adder, IM adder ‘ond carry save adder (CSA) Operation of 16+ ) and its performence eval jotion relative to RCA ent logic styles 99ogqgqggqg Impl INTRODUCTION it. The fundamental arithmetic lers before designing o circv! ry and fundamental function. General:purpose systems 1 many Vist design peradigms. siice each Pi , must be done correctly. Finally, Je dve to this new signed-digit mmbers. Iris extremely crucial to conduct thorough research on odd eperations would be incomplete his o necessor rocessors 11 higher bit jved logic: stem, which ithout addition, whic a it heavily, os it appears lt very important operation that jigh-speed adition is possi rithmetic representations of like rely positions, this is @ posed adders. Hi ere both carefully chosen or cond opplication-specific Pr rust transmit « carry signal fo 2! nds with mutiple-vol the chapter ef number 575 umber system and the residue giana 2H ONE JOURNAL FOR ENGINEERING STUDENTS”LOW POWER VLSI DESIGN UNTUAyp, (PART-A) SHORT QUESTIONS WITH SOLUTIONS Q1. Whatis standard adder coll? ne An: Meigg A mtn tne nts nd tng Oc yen 9, We have two types of standard adder cells, a oti 1 Hall adder s a 2 ‘Pulladder Me ‘This means the half adder and full adder are used as building blocks in the design of ‘complex adder structure, Q2. What is the need of Low-voltage Low-power Adders? Expla Ans: . ‘The fundamental mathematical caléulations cannot be performed without doing addition, addition is an ing operation. Also, subtraction, multiplication, division, and address computation all depend on the addition cone d addition is regarded as an indispensable component ofthe arithmetic unit, Hence, Low-voltage Low-power Adder Q3. How carry propagation time can be minimized for ripple carry adder. , Ans: : Mair ‘The cary propagation time of ripple carry adder can be minimized by using various designs of improved fay Standard el. ‘The use of fastest full gdder standard cell inthe construction of ripple carry adder minimizes the cary yrs time. Designing ripple carry adder using the 10-T FA model instead of TFA model exhibits 44% more speed. ale 1 ‘model performs better than the TFA model over the entire power supply range. . Q4. What is an ELM adder. a Ans: - Model Pte An ELM adder is a variation of the basic Carry Look-Ahead adder algorithm. The algorithm of ELM addition encoaps 1 binary tree of basic processors that run in O(log n) time. The ELM algorithm was developed using the idea of carry py and generate. The ELM adder directly calculates the sum bits in parallel, which allows it to lower the numberof nis connections, QS. What is carry save adder (CSA) and how is it obtained. * Ans; “ MdetPa? Camry Save Adder (CSA) isin fact a Ripple Carry Adder (RCA) with its carries saved instead of propast# words, Carry Save Adder is obtained by slight modification of the Ripple Carry Addet, that is, the carrier is saved ba full adder instead of propagating it to next full aidder block. Figure (1) illustrates the block diagrams of both RCA and comparison. The Carry Save Adder performs concurrent addition of multiple inputs. bout bj lb) Lh) Lo | rH fil cael ba |b Pree ep [PEAT pear ris (e) RCA (w)csa Figure (1): Block Diagram WARNING: XeroxiPhotocopying of this book is @ CRIMINAL act. Anyone found guity is LIABLE to face LEGAL proceeina _eeeeeeeeerereeee! nIT-3 (Low-Voltage Low-Power ‘Adders) cae 5 Explain static and ‘dynamic logic styles. Model Paper3. 12 caleulated when cycle. Dynamic gates are amie. The output oF static logic families every clock ns ‘There are two types of CMOS logic circuits: static and 4) _ put changes, whereas the output of dynamic logic gates is © erent from state gates because they are clocked and perform in the Distinguish between Transmis: culated only once PEF 1. nt he differences between transmission function full adder and 10 Transistor pol adder are tabulated belors n Function Full Adder (TFA) 10-Transistor Full adder ( T FA) TFA encompasses 16 transistors 7 ro. FA encompasses 10 ‘transistors When the voltage of thy Power supply is set t0 3.3 V.| 2 When the voltage of the power supply is set 10 3.3 V, the.) - the critical path delay of the TFA measures 0.12 ns. critical path delay of the 10-transistor FA measures 0.086 .| ns _ | ata voltage of 3.3 Vand a clock rape Ot 2 f3.3 V and a clock frequency of | GHz, the the TPA dissipates around 170 }W. To-ransisoe FA consumes an SYSTSE® of 81 nW of power Wy carry look-ahead adder is developed? ans? inthe dase ofa ripple cay adds the si anddelay associated ‘wth the logic circuit increase linet swith input operands. natn input increases, the size and flay of the adder inreases In order 2 rercome this drawback, the carry look er has been developed. 8, What are the different logic stvies ‘ised in the implementation ‘of KOR/XNOR gate. Ans: : Five different logic styles are explicitly used for implementation of XOR/XNOR gate. They are, 1. Fall static CMOS Complementary Passtransistor LOBic (cPL) Logic (DPL) i Double Pass-transistor Dual-rail Domino dynamic logic Single-rail Domino dynamic logic:sa LOW POWER VLSI DESIGN junr, Yi | ‘Dy PART-B ESSAY QUESTIONS WITH SOLUTIONS” 3.4. Intropuction, Stanparo Apver CeLts Q10. What Is the need of Low-voltage Low-power Adders? Explain, 2 Ans: ‘The fundamental mathematical calculations cannot be performed without doing addit operation. Perhaps the general-purpose system and application-specific provessors use the addi also itisused extensively in many VLSI systems. Furthermore, subtraction, mulipliation division wel one depend on the addition operation. Hence, addition is regarded as an indispensable component ofthe ares

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