ode e incieital syqqe TtEF et ea gee Seine Pt another, Fa ity Eng, » Encoders, in digital logiouse® Ne OulpUL. So ar is what latch e There are variety of binary codes A of these codes are BCD, excess -3, pep B (ten its required to convert from tops GOT) T4180 * that purpose code converters are E ret STE USCA to set priority for various actly da Converter a 1, + BCD to Binal nab inpat | {active low) PREvious Years QUESTIONS ee ABCD+ABCD+ABCD+ABCD \" =, = Vg XT 0011 0010 O11 O10! 4 NY, — Ve +ABCD+ ABCD + ABCD oy 1001 1000 1100 a = L6.2,7,5,9,8,12 bees \7 > L m(23,5,7,8,9,12) aoe % De 8 Find the output of folowing decoder cireuitas shown in Fig. 2017) ' the principle of decoder ata time only one . £(A,B,C,D) ABIo+ABI,+AB1,+ABl, iter Dy or Dy of see een he value of 2, tha c ee = a weans either Do or Dy of second decoder will be hish. We =ABC+ABD+ABC+ABCD eae f will RB c(p+b)+A8(c+2)p Therefore output of AND gate will always, (RTU, 2017] In second decoder A, will always be zero while Ay ice. LSB may be 0 or 1 will depend upon the value of Z, that are oring the Dp and D, by OR gate therefore f will always be I. i +ABC(D+D)+aneD24 7) use A and C as select ee IR-TD. Dec. 2016) Ans, RA. B,C) = Em, 1, 4,7) B % Implement Bx I mux. (ABCD) = Lm UyFA tL I213,14,15) mre, The following, tople Junction wa " oR Implement the following logic using onty » me MUX: FA, B, GD) = 2m ly 3,4 12,13, Wey, Z Ans. The truth table for the given four variable funcyom given below and its implementation using an 8:1 muy") three select inputs A, B and C are shown in figures, ‘The inputs A, B and C are connected to the dag ines Sp, S,and Sq . From the truth table we obserye For both values of ABC = 000, ABC=001 and ag 101, F=D. So Dy, Dyand Ds are connected toy For both values of ABC=010,F =D. So connected to B. For both values of ABC=011 and ABC=109, »_ So Dyand Dy are connected to 0. For both values of ABC=110 and ABC=111, p, Dgand Dy are connected to 1. a | Sa Sy So ae ef of ete ft [iy | eo ote ty [ty [es ofits [ta [es ottli |e [ ep ro rte [eT [ey re re [epee] 2 | ree rlite [yyy te Lili {ite tipsct minterm. £310 8 line deo? A ( table of yn Thera i eh wld ES 8 line decoder wi struct 6 i iagram also, From the truth table, the Boolean expres WRU. 20177 output line is as follows. information represented inbinany Torn Suge lbee form. This is obtained by known as decoder, line decoder. is shown in fig 1 BG: Y, = ABC The logic diagram of these Boolean expressions can be implemented AND and NOT gates as shown in fig.3 A B Decoder output i, i c ter, Binary to gray in applications of decoder are splay, digital to analog converters converter etc, The mair demultiplexing, digi 7B Decod Fig. 3 Logie diagram of 3:8 decoder Fig. 2:3:8 DecoderImplement 9 6 x 64 de coder using 3 x # tine decoders : The 6 « 64 decoder will hav ‘ output tines 1g eeOer Will have & inputs Hines and x decoders with « 0 | — {apart tines, cight output tines and ane [0 | ~ enable input Eis considered as foun in 0 to input D of the decoders ns shone 0 — Dao inane’ ATE active high enable inputs, so when | —y t cur gtied o input D, the first decoder (De- Dyyealt i [es Setenabled and last ~4 decoder (D, ~ Dy) will hedignes i pe igen, Lis applied. the rst 4 decoder (Dy -D,) Banda | Will get disabled and last-4 decoder (D,-D,) willow | Le -oe Enable snp} on¢[ sro} a0] 38 Fig. 4: Total 3:8 = 9 Decoder 8 Implement a full subtractor usin multiplexer. SS an ep Dy two 4:1 (RU. 2017 or Band B, i full subtractor B and B, in Heat lines S, and Sp tespectin Form the truth table o! Form to ed vo the recta Aan tens (D)andbOTON Osa from the truth table or as / oo reas thal of tn cq 237) By = Em(1,233+ sign table for difference (D): Design tab ee a A Input to MUX = piterneeD)—A A A A Fie 7 Design table for borrow (B): Do Dy DP; Dd, ale ala Input wo MUX-2 (Borrow BJ — A Fig. Implementing the circuit of full subtractor using te multiplexers. AR Das Linea. MUX-1 }—Ditterence ss, Borrow Losi! aa Fig. : Full Subtractor using Teo? 1 Multiplexersin demutineser, @ mudtiplever ZU. bee. 2016) exer is used in tudio signalson fro noe Multiplexer je uate, COMDULEE System ofa 1 da.a signals ground system sinele source 16 soanty: De*Uiplexers are ug Multiple destin! ed to connect peta the Fallowings "PI* €estinationsThcae at sonnet Communications. vstem : Multiple = both are used in Community eAee ane res the Cupar ae pte g eee = ais fom the multiplexer wean rer end converss them cig "Arithmetic Logie t the ar Fe ena? Put tothe Demat ame the demultiplexer is eon tole gine 5 ? The serial to parallel Free reform parallel data. In this methor sency ere Eton teen input 8)ihe|De-amutiipleverats cin, and 2 counter is attached to the demultiplexer 1 /p to sense the data signal all data signals are stored, the, be read out in parallel Maltiplexer : Multiplexer is a device that has multiple and a single line output. The select lines determine input is connected to the output, and also to increase it of data that can be sent over a network within Hime. Itis also called adata selector, The single pole multi-position switch is a simple ‘of non-electronic circuit of multiplexer. Multiplexers In analog applications, 1 vd dig! ipable of handling Ee ' alti and transistor swatches, whereas in digital 4 nal inultiptexers are built from standard logic 6 tultiplexeris used for di ‘muhiplexer Muttiptesee Types Multipleers ant ultiplener (2 impteme) tal application’, classified into for ultiplerer (I selee select lines) iplerer G select | ouput Fig-Muttiplen sate level schematic uf a 1-1 8 component realis, ) Signals A, B,C, D a aly one 8 ty EAE ‘nt the expression, UX and no ippticatic iniseal ations relays ws, He je when t eyed alii! appl jo up 4 decoder © @ 110-16 decoder. ind A are available. Using other gate, P= (A,B, CD) = BC+ ABb+ AéD IR.TU. Dec. 2016) Ans.(a) Fig. 1A decoa7.12, 14, 1) hha wang, Kod2 ses Hs DOD A oi nde ndogD KROOA KT f= Lm(1, 5,6, 7, 12,14, 15) a. ement the following expression: @ y= ABC using 2 input NAND onty a y= Im (0, 2, 3, 6, 8, a, ‘muttiptexer Gy y= (i) 16 * 1 mux using Ans.) ¥ = ABC = ABC =D=4 & [ re Gi) y = Em (0, 2, 3, 6, 8, 9, 12, 14) Since the given Boolean function has four variables. To implement it using 2 multiplexer 16:1 MUX is needed when type-0 method is used. The truth table of the given function is 12, 14) using 2 (2, 3,9, 11) using 4 10 16 line decoder 2 1 mute TU, Jan 2016) ly 1 1 {1 1 In type-0 method, th with minterms to logic 1 logic 0 as shown in fig. Logint Logie t ylowps S 5S, 5 AB COD Select inputs Fig. using 4 to 16 line decoder is shown in fig. (iii) The implementation of the function y = Em(2, 3.5ign a 4 bit Binary to Gray code converter andy dans the logic dlagrame [TU 2015) OR Design and implement a convert ‘ abit binary to gray code PTH 2009, 2008] reuit that changes data) jother type of binary Ans. presented in one type of binary code to an code. —rB, G G, | |4- bit eray G, | [code output 4-vit |] B, inary input] —>] B, | Ba____S24 Fig. : Block Diagram of 4-ble Binary to Grey Code Conventer Tic web to Teegment decoder isalso.a code converter. The block diagram of a 4 bit binary to gray code converter is shown in figure. Ithas four inputs (B, B, B, B,) representing 4 bit binary numbers and four outputs (G, G; G, Go) representing 4 bit gray code. The truth table is shown in table. Table : Truth Table ‘Binary inputs Gray code outputs] Bele |B] oG | G& |G |G | ofo,oj,o]o 0 0 oO] ofofolt1]{o 0 0 i o fo titolo Oo 1 1 ofofiti1y{o O 1 Oo] Oo 1 [0 0 [0 1 190] of1fot1|o 1 | 1] ofr fr fo [0 a) ra of1trT1 yo r 0 | r{ofofo lt 1 Oe) 1{-o [ofr] T Oo rtof1 fol i Tot a a i a 1 1 oo 1 0 11.01 a 1 0 ese Ce a 1 0 Oi eats Ieiersias]st 1 0 o | 0] From the truth table, the logic expressions for the gray code outputs can be written as: (8,9, 10, 11, 12, 13,14, 15) -m(4 5.6, 7, 8,9, 10, 11) 1 = Z(2s 3,4, 5, 10, 11, 12, 13) Gy=Z,,(15 2, 5,6, 9, 10, 13, 14) Design a Binary to Gray code converter. : ‘al. Univ. 2007, 2001)alo oth u 10 From the above K. Ba BBX 00 ra oo] 0 0 ° From the above K-map_G, BBS oof o}o}olo o1 10 (©) K-map for G, By @K-maphorG, Fig. 1: Kemap BOB, 2, @B, Dinary 1 way Cade n for K-map simplificatio rom the above k-map Go = lly +B, = 4 Now the above expressions be imple, 5 Ex-OR pates as shown in figure be! 6 —@-—@$_ +=) >— 5,4 oI b, ———_ eer?" ig. 2 s Logie Dlogram of Able Binary 10 Gry Code Cg, Q.13 (a) Design a excess - 3 to BCD cade using 4 bit adder. = (6) Design a full adder using mip, " SantsExces 23 to BCD Code Convertor ences GayBxcess - 3 to BCD C nvertor way ‘Alor The excess-3 number can be convenes t! umber by adding 2’s complement of 3 into exces, as shown in the Fig, (Binary) AR ae Saree itl eee Fie. The truth table for Excess-3 to BCD code ex is as shown in the Table 1 Table: Truth table for Excess 310 BCD Convene ‘Kemap simplification For, © [& [5 [& [8] 15, ofoli|i o]0 ofijolo ojo oli folr oft o}ifilo o}a ofidada 1{o 1}ololo iio rjojo}r vi rfo}ilo via rtofala ono Lilitolo olo=D 0.2.4.7) Coa (ABC) = D,0.5.6.7) The S and C_, functions have 3 variables. Hence they can be implemented using a multiplexer with two select inputs and four data inputs. The implementation table is shown below: Fors ForC_, DB] Dd] v.] p,]} 1 | 0] 9, | 0. >| ol S| [».] clololo ofr] 2| s|e 4 @|o| ce. (tr leo, o{c. [cu | Procedure for Implementation of tie Faacuccs 3 = ole fk jee Ose Fig. : Full Adder using 4:1 MUX‘Rah. Univ. 2004) Deseri ibe encoders and decoders with suitable diagram, a IRT.U, 2013) Se gc ca eee celiac conversion of bangih’ decoder, encoder also provides the Encoder perfommau, ifrmation from one form to another information inne he &PPOsite function ofa decoder. Its gives 5 than Guta eacemPact form. Encoder has more input PUL Lines. Ira, BES OF Say output lines are less than the 1h, 7 input lines and n output lines. Fromm Activated at a time and gives an Putput lines. The block diagram of eae ig.1. Encoder is a digital or combinational sireuit that com coded ou Encode converts an active signal into coded output signal, used 10 reduce the number of bits needed {0 information. A practical use of encoders n in a digital system. Encoding is formation is 10 be stored for later use ie Tequired to be stored. alae] Encoder [—7—* nip 1__,] i Fig. 1: Block Diagram of Encoder __ Decoder : Sometimes, digital information represented in binary form must be converted into some other form. This is obtained by multiple inputs-multiple outputs logic circuit known as decoder. The most commonly used decoder is n to 2" line decoder. The block diagram of (n : m) decoder is shown in fig.1. Ithas n input lines and m= 2" output lines. “ines” Decoder [—J—*mguiru L | Fig. 2: Block Diagram of a : m Decoder Ina decoder, m output lines are greater than n input lines. But when input lines are equal to output lines then it is known asa converted, It converts one form of bit binary information into another form of m bit binary information. For example BCD to excess-3 code converter, binary to gray code converter etc. In other case when m output lines are less than 2° then this type of decoder is known as function specific decoder. For example, BCD to decimal decoder, BCD to seven segment decoder etc. The main applications of decoder are Jata demultiplexing, digital display, digital to analog converters ind memory addressing. aan etter atom in fig.|- Iisa 5yNCRFONOUS int inary adder is shown in fig 1. 18 if aie nats designated X, and X, Which cary! wo inp ‘and one output termingy binary numbers to be added ba ere pany the sum. The inpats ae ou spss ist ony eal ‘s The addition is po! Feng sequences oO ott mum serially, i. the least signi X, arrive at the corresponding i tine later the next significant digits arr and so on, The time interval between the arrival consecutive input digits is determined by the frequen. circuit's clock. ding. input terminals ayy) ive at the input ye * © : " or x COC I seriatadter LZ, Corr x — 3 — fp" | Fig. 1: Block diagram ofthe serial binary ade, The delay within the combinational circuit is smay, Y respect to the clock frequency and thus the sum digit a7. at the Z terminal immediately following the arrival q corresponding input digits at the input terminals, The output of the serial adder z, at time t, is a func, of the inputs x, (1,) and x, (t,) at that time t, and of ac. which had been generated at t,_ ,. The carry which repre the past history of the serial adder may be a 0 or 1. So ~ FF is required to store it and one state indicates that the c- from the previous addition is a 0, the other state indicafes the carry from the previous addition is a 1. | Let A designate the state of the serial adder ft t carry 0 was generated at t,_ , and let B designate the st the serial adder at {, if'a carry 1 was generated att _ 1 state of the adder at the time when the present inpu's applied is referred to as the present state (PS), and the sw to which the adder goes as a result of the new carry valve referred to as the next state (NS). y FF oon on am tm BOGS “ape State Diagram A } oe a ni« diagram and state ble of the sertal adder the behavior of a serial adder may be conveniently diagram and the state table as shown in Wdcarry 0. Sos Aand outputea inputees = Oca 80, the machine remains a p07 200 he mach in state A and outputs a 1, . 15 JA 1 give sum O and canny faethe ne Boes to state B and outputs a0 “ Ifthe machine isin stare Be I give jot outputs 20. Inputs x, 1, x2='1 give sum landemy chine remains in state B and outputs @ I. Input = Ogive sum I and carry 0, so, the machine pore to Aand outputs a 0. The state table also gives deen. jomation. The states, A= O and B= | have aieesdy bons signed. 50, the transition and output table is as shown iy 1. 90, the Transition and ouput table Fig. 4: Logle dlagram of the sertal binary alder To write the excitation table, and to select the memory clement we use D flip-flop. The excitation table is shown in ‘Table 2. Obtain the minimal expressions for D and zn terms of y, x1, and xz by using K-mapsas sh6wn in Fig. 3. Implement the circuit using those expressions as shown in fig.4. | rare ee Q.16 Draw the logic diagram of and show all implementation steps @ BCD 0 excess - 3 encoder (i) 4 bit binary serial adders Gil) 2 bit multiplier (iv) Parity Generator 2 checkers (4 bit) IRTU. Jan. 2016} ; NE or Ans.G) BCD to Excess - 3 Code Converter : The bit x ae combination for BCD and excess-3 codes are listed in table ooor 10 Foo Let the input variables are designated as A, B,C, D and four pepo oo 1 to 7 > ‘output are designated by w, x, ¥ ifort _s_ti oo 4 input BCD, a ; : ao ep 7 = PS [ip NS "| Up rk | OF ao 9-8 to ya DB 2 a oo] oe |—o ° o a 1 7 o}o}il}o ° 1 o o—}—o I-41 o}ifo]o ° 1 ° 1+ a ofirfa]a 1 o ° or or T}o}o]o 3 i 2 = i tfofr]a 1 ° lr =a ifrfo]a 1 o t - — tlitito 1 1 ‘ap representation of w, x, 2. No or toy Noo or nto “eT o fi “Tea | 7 * oe] Te 1 ofa n We y Tit ote ufelle| «|[e| 2-3 {peep ros Des ZR REeNeney | ifr els tale Fig. 5: K-maps for the serial adderTeen Ti The delay within the eombinat respect to the clock frequency and th i a the Z terminal immediately following the rngg tn comesponding pur digitsat the mpat terminals. The ompat ofthe serial adder % at Me isa of the inputs © C4) and xy (1) at that time tang gf, Sshich had been generated a f-y- TH© C30 which 8 the past history of the serial adder may be 80 oF | FF fe required to store t and one state indicates that trom he pein sion 0, the othe en the carry trom the previous addition isa 1. Tet A designate the state of the setial adder, carry 0 was generated att, , and let B designate het Si the serial adder att a carry 1 was generated a ¢ % state of the adder at the time when the present jn! applied is referred to as the present state (PS), ange « to which the adder goes asa result of the new cam" referred to as the next state (NS). wes ze mG) Os: My Bem) C8 Roepe TCiFCUTt isa is the sum digit! eh 5 State Diagram Leelc Diagram of BCD 10 Excess—3 Cole Converter Ci See Bletram of BCD 10 Excess-3 Code Ci . Binary Adder: lock diagram of a seria binary adder is shown infig-.tisasynchronsen ceca fwo input terminals designated X, and Xz which carry the two binary numbers to be added and one output terminal 2 which represents the sum, The inputs and outputs consist of fixed- length sequences of 0s and Is. The addition is performed serially, i. the least significant digits of the numbers X and Xz arrive at the corresponding input terminals at t,; a unit time later the next significant digits arrive at the input terminals, and so on. The time interval between the arrival of two consecutive input digits is determined by the frequency of the circuit's clock, COT an nse Zz Siatetable Fig. 2: State diogram and state table of the serlal adtg The behavior of 8 adder may be conven, described by its state diagram and the state table as sy fig. 2. The state diagram shows that if the machine is. A, Le. carry from the previous addition is a 0, the 2" X1=0,x 0 give sum Oand carry 0. So, the machine in state A and outputs a 1. Inputs x, = 0, x3 I give sun} carry 0, so, the machine remains in state A and outpa but the inputs x, = 1, x; = 1 give sum O and carry Ins, machine goes to state B and outputs a 0, Ifthe machine is in state B, i.e, earry from the pre addition is a 1, inputs x,=0, x~ 1 give sum 0 and cary Sse Jz. the machine remains in state B and outputs a0. Inputs - X27 0 give sum 0 and carry 1, so the machine remainsin ss x Band outputs a 0. Inputs x,= 1, x= 1 give sum 1 andcx = 1, so, the machine remains in state B and outputs a |. bo . X= 0, x= 0 give sum I and carry 0, so, the machine gx state A and outputs a 0. The staie table also gives the information. The states, A= 0 and B= I have alread assigned, so, the transition and output table is as show Table 1. Tre Fig. 1: Block diagram of the serial binary adder.EE Table } : Transition ang, OMtpUt table rates partial ‘Then B, is multiplied with. Ayan Ags ne Lae a a ertent roduct which are shi A Som of these partial products produce the result of multiplication using AND gates and adders as epee Figure 1. Each partial product is either 0 or | depen on 1g upon the multiplicand and multiplier. The AND gates Pr Partial products. By a DE ZexesTy. SHES Foxy Fig. 3: Kemaps for the serial adder Pe Fig. 2 2-bit by 2-bit multiplication Ina2-bit by 2-bit multiplier, two half adders are used to sum the partial products, but generally full adders are used in multiplication. Here P, - Po, are the product output. Table shows the product output of 2 bit binary numbers. The product ‘has more digits than the multiplicand and multiplier. Table : Truth ta ble of 2% 2 multiplier plates Truth tabte of it ae Input Fig. 4: Logle diagram of the sertal Binary adder Towrite the excitation table, and to selec tthe memory Multiplicand | Multiplier | P; | P; | Py | Po we use D flip-flop. The excitation table is showe Ay_| Ao [By | By jinimal expressions for D at dz in terms oO 0 oO 0 oO 0 o x,and x, by using K-maps as shown in Fig. 3, Implement oO a cuit using those expressions as shown in fig.4 oetete te Multiplier : The process of two bit multiplication o|ofolo sure 1. The multiplicand A (A, Ag) is multip! 0 [oo nm by each digit of the multiplier B (B, B,). Initially, B, is foyer ied with A, and A, and generates partial product A, By, i 0 1 “9 Fig. 1 : Process of 2-bit multiplicationg & Tt tee --cccc ccc ge = & 00 or " 10 P= B,@B,@B,OB, Parity Checker: By o 0 0 o 0 0 0 0 S|e]oJo}olalaa| -|-|=|-|o}elolole Fig. 1 acre =|=|9]2|-|-lolole =|e}=]o]-lo|-lo-5 =oo}-|e]~|-lela) 1 c= B,@B,OB,OB,®P =p PR P Y Fig. 2 Q.17 (a) Design a 4 bit binary to BCD code conven. (8) With the help of gate level logic diagram truth table, explain an octal to binary encoder RI ‘a) Design of a 4-bit Binary to-BCD code com There are 16 possible combinations of 4-bit binary (representing 0-15) and all are valid. Hence there are noé: cares, Since the input is of 4 bits (i.¢. a maximum of 2¢: digits), the output has to be an 8-bit one; but since ts three bits will be a 0 for all combinations of inputs, the «= can be treated as a 5-bit one. The conversion is shown= conversion table. From the conversion table, we obser: the expressions for BCD outputs are as follows:‘m(10,11,12,13,14,15) B=Zm(8,9) C= Em(4,5,6,7,14,15) D=Em2,3,6,7,12,13) Ee Em(,3,5,7,9,11,13,15) -prawing the K-maps for the o gs shown in fig. 2. The mi Sutputs A, B, C, D and E int By By» Bz and B, areas follows: MBs + ByBy B= BBB; CH TBs + BB, D=ByBsB; + BB, Table: Converison table utputs and m terms of the 4-bit binary reo, te oo 7 TT ais esa ae SomR SE awe mae abit binary BCD output BATS [cl DLE 0 folotototo ifofofofett ofopo top te ipofotetrt oo fot pote ifopotrfott apo fot rho ipofotrtr yt ool totote po} po fot ofr fotototo} Thre poor oprhepoyi te 7 ofr toteti ts K-map tor € OO TEETOTA OTT] | Ans.(b) Octal-to-Binary Encoder It is well-known that a binary-to-octal decoder (3-to-8 decoder) accepts a 3-bit input code and activates one of eight ‘output lines corresponding to that code. An octal-to-binary encoder performs the opposite fun accepts eight inputs and produces a 3-bit output code corresponding to the activated input. The truth table for the octal-to-binary encoder is shown intable.Ans.(a) Diode Switching Matric inputs and REDEIALES n by, eiienetnerted Karan own in fist A encoder has depending upon which of th diagram of an encoder is sl joc ooo os =f oo coon aly loc ecco aly oo-ccccalt ae ‘Sad truth ace shows that (LSB of output code) must The henever the input D, OR DyOR D, OR D, is HIGH. Fig, 1: Block dlagram of diode peliching matte %o=D+Dy+D.+, i ‘Similarty N= Dr+Dy+D.+d, % = Dy+ Dy +d, «dD, ix of wires to design an eve, It has array matrix of wires to desigs io which row lines and column lines will make Ws squares, Some of the squares are occupied by the ¢, depending on the circuit design. Let us take an exazayy 7 to 3 encoder whose truth table is shown in table. Wing the above expressions, the octal-to-binary Table Teuth able of etal bins sncoder can be implemented using thece Inputs aoanen plemented usin input OR gates as fete Te Y, ae HCE, he Citeuitis designed in suchaway that, when | ai 1h [i | fe te TY, Do is HIGH, the binary code 000 is generated: when mist so Toper ele lols jo one HIGH, the binary code 001 is generated, and soon. pal eod RsAltoalegdl is | olojoli|i Pe Ley ofololi|sjolojs|o Via bd ae ee Solojolrfoyolol riot, Db Seen pea eh nen ara OH Eons ToRei 2 [: foams: O}ololojojo}rfoj} aia) D, olojololololojiiiafil Ds The OR gates required in the expression of Y. Da Y, can be implemented with diodes. The diode switt. D, matrix for the above encoder is shown in fig. 2. In Fig. 2S, to S, are switches corresponding tc: input line. So, each line is activated only when the repose switch of this line is switched on. In the diode matrix Ré R-7 are row lines and C-1 to C-3 are column lines. diode is connected within the square which is conneciea’ ¥. y, Yo one of the row and column line. These diodes are conn: between R-I and C-3, R-2 and C-2, R-3 and C-2, RJ m C-3 and so on in the similar manner between some ct rows and columns. Any line activated through the respectn switch of the diode, if any, connected in this line will coe into forward direction and +ve point of supply is connect the column through which this diode is connected and so current is flowing through this diode and resistance to wb this column is connected. Fig. : Octab-to-binary encoder The design is made simple by the fact that only eight Dut of the total of 2* possible input conditions are used. eee a Seen 2.18 (a) Write short note on Diode switching matrix @®) Design and explain the working of BCD to 7-segment decoder. (RTL. 2014] SuSnERSUEEEEEneeeeemeeeeeeog A 988886 386 (>) Deaplay of Dorimal Degas = 2 aeven engment nee? Piet . Design of BCD to - Seven Segment Decoder BCD- to seven segment decoder can be Geugned eng loos gates. A block disgram cf BCD to- seven segment decor with four BCD inputs (4.5. (ahede, Sand g) correspoeding to seven segmen display, is shown ia Fig ¢ The trath table of the BCD © shee cece oc otar atic ever is 1. Similarly Y, will be high " Phoehot iocamrreycae ph oneten tee Ourput shows the ORing of inputs by use of diode y connecting the diodes in appropriate place fs ace ing matrix, one can obtain any pe of encoding, aa Jer array shown in fig. 2 is called & receanguias dove Silly, dsoder can also bemade as arecanglar | 2 sats cent eet ae ee oes (b) BCD to- Seven-Segment Decoder/Driver Shbeeasions commesponding to seven segment can be Wrmes ) BCD to. Seven Songnt Decoderpriver ,, | fom ine wehbe hows matiews Slows sying any one of the decimal digits, 0 through 9. ABCD. 2=2.2,3,5,6,7.8.9)- Fae ven segment decoder accepts a decimal digit in BCD = ‘generates the corresponding seven-segment code. b= F.1,2,3,4.7,8.9)-F aoriae Figure 3(a) shows a seven-segment display composed - a . even slements or segments, Each segmentis madeupot | ©" LaOLR45.67.89)-F aotui2131 fal that emits light when current is passed through it st commonly used displays are LEDs and incandescent ts. Note that letters a.b.c.d.eJf, and g run clockwise 2=D0.2.6.8)+F 0011123.1415) the top of each segment. For instance, to display a 1, the 7 a gments b and c have to be illuminated; to display a 0, the £ =F .4,5,6,8,9)+ F Or LIT31445) B= (23.45,6,8,9)+ F AOD ISIS)From the K-map_ c=B+T4D as a) R-map for segment OUP From the above K-map é=A+BD+CD+BC+ BCD =A+CD+B(C+B)+BCD =A+CD+B@(C+D) method ote es ane can be simplified using K-map coco} orto wo} 4 ol fa | 7 sal o 7 7} af »} oe oan z Hl {kts Fromthesbove map et a=A+C+ BD+BD=a4c4 56D a a] it 10 | ft y or} 4 1 al fi oi @ o wlall ef. |b segment output ‘b* cep n 0 oof fr 1 @ +] of {fr @ 7 aftr 1 e a} wf o ‘ e @ (©): Komap for T-segment output ‘ coy orto 3 ol sj} ie} « {bh Cc ce nn] ie ° ‘ a | G Talaremtate @: From the above Lap for T-segmient output ‘e" 1 ” ¢ ’ 10 ° 7 a @ Ds K-map for T-segment output F From the above K-map_ f=A+CD+BC+DD=A+D+ C+D): ~_ (2) Kemp for F-segment output 'g? ‘Fig. 3: K-map simplification. for BCD 0 a us E From the above Kemap ince | = A*CB+ BC+ BE AasCD+ (BOC) Sormtiargrea Now, using the abose simplified expressions or sev it output, the BCD- to sever 1 ae fen segment decoder cam ented using logic gates as shower nrg oe oan OS Fig. §: BCD-to-7-segment decoder driving a common anode 7-segment LED Display ———— ee Q.19 (a) Explain full subtractor in detail, Realize it with two half-subtractors. (RTU. 2013] oR Implement a full subtractor using half subtractors. {RT.U, 2012; Raj. Univ. 2005] (6) Explain 1:4 demultiplexer. Design 1:8 DEMUX using vo 1:4 DEMUX. (RTU. 2013) Ans. (a) Half Subtractor: A half subtractor is a combinational circuit which is used to perform subtraction of two bits. It has ‘wo inputs, A (minuend)and B (subtrahend) and two output Difference) and Bo., (borrow out), The logic symbol for a half subtractor is shown in fig. (a). ‘The truth table for half-subtractor is shown in table 1. A —-> Tp > ns = B. t—s., |_ bef ee, (2) Logic symbot (b) Logie diagram Fig. 1: Half subtractor Truth Table for Half Subtractor > 4: Logic diagram of BCD-t0-7-sexment decoder Pe aitaa? and I 7448/7449 BCD-10 ~ Seven ~ Decoders, ICs : 7446 and 7447 are BCD to seven decoders with active LOW open collector outputs \g. common anode seven segment displays. i$ and 7449 are with active HIGH outputs for dri splays. Fig. § shows a BCD to seven segment decoder/driver TL 7446 or 7447) used to drive a common anode 7-segment BD display. Each segment consists of one LED and the es of all LEDs are connected to + V_(SV). The eathodes [LEDs are connected through current-limiting resistors appropriate outputs of the decoder/driver, By forward different LEDs, the digits 0 through 9 can be displayed. ‘Output Bout 0 1 0 0 From the truth table, it is clear that the difference output is 0 if A= B and 1 if A # B; the borrow output Bou is 1 whenever A ye Hs a |__ 5 | bey), (2) Logie symbot (0) Lege diagram Fig. 1: Half subtractor Fig. 4: Logie diagram of BCD-to-7-segment decoder Table 1: Truth Table for Half Subtractor 416/744? and IC 7448/7449 BCD-t0 - Seven -| [ Tapas Sap Decoders, ICs : 7446 and 7447 are BCD to seven y airs decoders with active LOW open collector outputs ~ ou 4 for driving common anode seven segment displays 2 g 8 and 7449 are with active HIGH outputs for driving 1 : on cathode seven segment displays. x o ig. 5 shows a BCD to seven segment decoder/driver 7446 or 7447) used to drive a common anode 7-segment ‘of one LED and the es ofall LEDs are connected to + V_ (SV). The cathodes LEDs are connected through current-limiting resistors appropriate outputs of the decoder/driver, By forward different LEDs, the digits 0 through 9 can be displayed. is clear that the difference output is 0 if A=B and 1 if A » B; the borrow output Baw is 1 whenever A D B Fig.2 Table 2 : The Truth Table of Full subtractors Minued [Subtrabend | Borrow [Difference] Borrow bit bit in D out Bi A B Bo 0 0 0 0 0 0 0 1 1 1 o 1 0 1 1 0 1 1 0 1 1 0 o 1 o 1 o 1 0 0 1 1 0 0 1 1 1 rot From table, the sum of product expression for the difference (D) output can written as: ABB,, + ABB,, + ABB,, + ABB, ‘Simplification of the above expression. D =(AB+Ab)B,, +(AB+AB)B,, =(A@B)B, +(A@B)B, [D=A@BOB,, Similarly the sum of product expression for Bay, can written from the truth table Bow =A BB,, + ABB,, + ABB,, + ABB, Buy = (ABB, +ABB,,)+(ABB,, + ABB,,) +(ABB, +ABB,,) ) + AB(Bo +B )+ BBA Sp fication to find out € expressions for difg, K-map for D = A@B@ By AB 01 14 410 8) 00 + fay lento | ° a we + be 7a, G Je. wo K-map for By, ~ AB+ ABj,+ BB, Fig.3 Logie Cireuit a Fig. 4: Logic Circuit for full subtractor Implementation of Full Subtractor A full subtractor can also be made by mo subtractor and one OR gate. From the Karnaug Expression B,,, can be written as follows: Bow = AB +A BB,, + ABB,, AB+B,,(AOB)=AB+B,,(A08)DEMUX 1:8 DEMUX using two % 14 Fy, pemux|_y, ss t-% + Full subtractor using -¥. 10 half subtracts x 4 Demultiple: ‘or 1x4 ‘YY, pt wa de a DEMUX| _y. sic circuit of I <4 demultiplexer is shown i . be ine S, and S, 5 own in fig. There SS. }-% ‘o select line S; and Sp one data line —'4 ose and # ato 4 output SSI Sy Se Fig. Table2 Ys S 0 0 0. 0 T T T T lola] -|-| cole INote : By using two 1 4 DEMUX, 2-AND gate, I-NOT gate, we can realize 1* 8 DEMUX.] ——— Q.20(a) Design a 4-bit parallel adder using full adders. () Implement the following boolean function using % Enablerstrobe Fig. : 1% 4 Demultiplexer with enable 5 Fi A 8:1 MUX. b table of demultiplexer is shown in table 3. . Table 1: Truth table of demultiplexer 1x4 i es acca ee = Sa e| s | Ss | ¥s | ¥: [| v1 [| Yo ‘Ans.(a) Binary Parallel Adder : A full adder can add two oT x |x 0 0 ° ai ary bits with carry. By using this Full-Adder we can add two binary numbers of n bit each, let the Binary Number are 1[ 0 | 0 ° 0 0 D AyA2A,Ao and ByByB Bo. So first add Ag and Bg then add 1fo |. 0 0 D ° Ay and B, with previous carry generated (Ao and B,), Similarly, add all other bits, as shown inthe Fig.1 i[1 [0 ° D 0 0 fee 1 fefee D 0 0 0 If enable (active high) is low, it will disable the liplexer and output of all AND gate will be zero. nultiplexer work normally only when E= 1. If, Sy=00, data D is transmitted to Yo. If S, S)=01, 2D is available on Y and so on.Thus two bits of A and B are added in parallel, with the carry from previous adder. The input of full adder 1 is given logic *0". You see that carry out of one adder is connected to the C,, of next adder. Such kind of carry propagations called ‘ripple carry’. As explained earlier that first Ay and By are as sum so Coat is generated. Then A, and B, are added with C,.., and gives S, and C,.,3, and so on, But the main drawback is that bits Ay A; A, Ap and B, B B, By are applied to the adder simultaneously and since an electronic circuit take some time to give result (called propagation delay) you will get correct Coaa after time try (propagation delay). Then only Fz works correctly. Thus to add 4 bit binary number you have to 4 ty, time for getting correct sum although propagation delay is in the order of micro seconds (1s). Such propagation delay must be reduced when high-speed circuits are required. The resulting output sum bits are S,S,S,So. For example if A; A; Ay Ap = 1101 and B; B, B, By = 0110, us to have ee Ca Leas significant stage foes oe ° 4 C. acter eee od bas aie ake =a gel fe gts oa iE Ss Coljntos significant sage nal Fig? 1010. Since the carry out Ye have an overflow, We see that Sy S; 8, Sp = from the most significant stage is a 1. We have Le. the sum (10010) must be expressed in 5 bits. 4 Yo Yr Wy Yo Mt % 7483 Co Cue SS 5 Se Fig. 3: Logie symbol of IC 7483-4 bit parallel binary adder. Ans.(b) Given that 3, 5,6) F(A, B,C) = in so is can t Is the tree variable function ea bey using 8:1 molipleser The given muntenn) "sone TEV ,.). The remaining en ie given functing ground or 0 potential. The truth Truth Table tps — Inputs ¥ ~ i ——7 0 0 T T 0 0 -|-|-|-|e}e]o] els. The complete expressi ‘on for output is ¢ ABC+ABC+ABC c+ < “The 8:1 multiplex circuit implementation is giveny Logic 0" (+Vec) PP. tp. ¥=E,(1, 3, 5,6) > to, / Ground T AB Selection Lines Fig. gu.