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Dynamic Offset Compensated Operational Amplifiers

Preprint · October 2021

DOI: 10.36227/techrxiv.16810225.v1

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Dynamic Offset Compensated Operational Amplifiers

Ara Abdulsatar Assim 1,2

Evgenii Balashov 1
1
Peter the Great St. Petersburg Polytechnic University, St. Petersburg 195251, Russia
2
University of Salahaddin, Erbil 44001, Iraq

Index-terms: Dynamic Offset Cancellation, Operational Amplifier, Auto-Zeroing, Chopping,

CMOS.

Abstract
The given work is devoted to designing and implementing different dynamic offset cancellation
techniques for 50 nm technology CMOS operational amplifiers. The goal is to minimize or get rid
of the effects of the offset voltage. Offset voltage exists in all differential amplifiers due to the fact
that no pair of transistors can be fabricated with the same size, there is always a slight difference in
their dimensions (length or width), this gives rise to an undesirable effect called offset, the value of
offset voltage for cheap commercial amplifiers are in the range of 1 to 10 mV, despite the fact that
this isn’t a significant value, due to the high gain of such amplifiers, this voltage is amplified by
tens or hundreds of times, this results in clipping of the output signal and this further limits the am-
plifier’s maximum allowable input voltage within the given dynamic range, hence its of great im-
portance to take this small voltage into consideration, low-offset amplifiers find applications in
mixers, analog to digital converters, instrumentation devices, etc. In this work, by using two differ-
ent techniques for removing offset voltage (chopping and auto-zeroing), five low offset operational
amplifiers were designed. The implemented methods reduced the flicker noise by more than 457
times (from 9.4 nV/√Hz to 20 pV/√Hz) at 1 Hz. All the simulations were done using Cadence Vir-
tuoso.

1. Offset cancellation techniques

Reducing offset voltage is the goal of this research, in this work different possible solutions are be-
ing considered to reduce its value to as minimum as possible. Low-offset operational amplifiers are
widely used for different applications such as medical tests, industrial sensors, and measurement
systems, in medicine they are used for amplifying signals coming from medical electrodes (weara-
ble sensors) for performing EEG and ECG tests (fig. 1.1), in chemical industries they can be along
with chemical sensors, hall-effect sensors, pressure sensors, and for sensing small currents in meas-
urement systems [4, 5]. To minimize offset voltage, three methods are used, these are: trimming,
 2
auto-zeroing, and chopping [5, 19-24]. at zero and low frequencies, offset, flicker noise and drift are
the supreme fallacy sources in operational amplifiers. This is mainly applicable for op-amps de-
signed with CMOS transistors.

Fig. 1.1. Using low offset op-amp with medical electrodes

The succeeding topics are concerned with reducing flicker noise and lower offset, before explaining
these techniques in detail, it is necessary to have a fundamental understanding of these issues [18-
24]. Offset voltage occurs due to random unpredictabilities during manufacturing the transistors.
MOS transistors suffer from threshold voltage inconsistency since the threshold voltage is depend-
ent on transistor’s doping level and it is different for each transistor. Another common issue is mis-
match between the transistors’ lengths and widths. While flicker noise exists in lower frequencies, it
is also known as (flicker or pink noise), this type of noise has a power spectral density of 1/f, the
point at which this noise reduces to thermal noise is referred to as corner frequency. It is generally
caused by the imperfections in the joint between the gate’s silicon dioxide and the semiconductor
substrate [5, 18]. Flicker noise can be expressed as:

𝐾
𝑉𝑛 = √ (1.1)
𝑊𝐿𝐶𝑜𝑥 𝑓

where – 𝐾 is a technology dependent constant; 𝑊 – is the transistor’s width; 𝐿 is the transistor’s

length; 𝑓 − is the frequency; 𝐶𝑜𝑥 is the gate-oxide capacitance.

Trimming method is implemented during fabrication of the transistors to reduce transistor mis-
match, it may also be reduced if larger size transistors are used (as in fig. 1.2) but this is not an ef-
fective solution because larger transistors need more area [4], which will lead to a higher cost, thus
Polysilicon-resistor films are commonly used in typical CMOS processes because they are widely
available and possess a high sheet resistance [17, 18]. The laser-trimming apparatus is built from
neodymium-doped yttrium-aluminum-garnet laser. The energy of the laser is soaked up by the pol-
 3
ysilicon film, this leads to localized crystallization of the material, hence that allows a very accurate
reduction of the resistivity of the interest zone [17]. It is possible to obtain very low offset voltages
using trimming, but this method does not reduce the flicker noise, hence other techniques (chopping
and auto-zeroing) are needed to prevent this problem, they also compensate offset changes gradual-
ly as the amplifier parameters change due to again and temperature changes.

Fig. 1.2. Offset voltage vs. channel length

Chopping is one of the major techniques used for offset elimination [2, 6-9, 18-24], it is favorable in
applications where a continuous-time signal is needed, in contrast to auto-zeroing technique, chop-
per amplifier (fig. 1.3) does not cause noise-folding. This method is based on modulation in fre-
quency domain. The principle of operation is that the voltage Vin goes through the chopper that is
driven by a clock at frequency fch, hence it will be transformed to a pulse voltage [9, 18-20]. Later,
the modulated signal will be amplified along with the input offset. The second chopper acts as a
demodulator, it demodulates the input signal to a DC voltage, and at the concurrently modulates the
offset to the odd harmonics of clock frequency that will be removed by a low-pass filter [11, 18-23].
This results in a signal with no offset and flicker noise, these two components now exist at higher
frequency (which is equal to chopping frequency), fig. 1.4 and fig. 1.5 show these steps graphically
in time and frequency domain, respectively.

Fig. 1.3. Chopper amplifier architecture

 4

Fig. 1.4. Demonstrating chopping concept in time domain

Fig. 1.5. Demonstrating chopping concept in frequency domain

A chopper consists of four transistors, it is driven by two non-overlapping clock signals as shown in
fig. 1.6:

Fig. 1.6. Chopper circuit

In the power spectrum density (PSD), both the offset voltage and the flicker noise are moved away
to the chopper pulse frequency, as illustrated in fig. 1.7:

Fig. 1.7. PSD of an op-amp with and without chopping

Despite chopper amplifier’s well performance in removing offset and flicker noise, charge injection
gives rise to chopper ripple [5], various methods exist to eliminate it (refer to fig. 1.8). One way is
 5
to use dummy switches that feed charge to the transistor switch, this in return gets rid of the existing
charge. nonetheless, charge cannot be distributed equally between source and drain terminals, for
that reason, this method is not very helpful. Another solution is using two transistors connected in
parallel, this solution is handy with smaller input signals only, the last and most effective method is
to use a fully differential circuit, this reduces the offset voltage by a factor of ten [5, 18].

Fig. 1.8. (a) using parallel transistors, (b) using a fully-differential circuit

Apart from chopping, another major technique exists, it is called auto-zeroing, it is widely used to
reduce offset voltage, this method is based on a sampling (discrete-time). It samples the voltage off-
set of the amplifier in the first clock pulse, and then subtracts it from the input signal in the second
clock pulse [8, 12-14, 18]. Three main topologies exist for auto-zeroing, which are: output offset
storage, input offset storage and closed-loop offset cancellation with the help of a supplementary
operational amplifier [18]. All the mentioned circuits use two non-overlapping clock signals (CK
and CK) that are out of phase by 180 degrees, in other words when CK is logic one, CK should be
logic zero and vise-versa, if both are on at the same time even for a very short moment, both of the
inputs of amplifier inputs will be shorted, that will lead to undesired effects. The easiest method to
realize an auto-zeroing amplifier is to put a capacitor at the amplifier’s output, as illustrated in fig.
1.9, C1 capacitor stores the offset in one clock phase and compensates it in the next phase. At the
first phase the amplifier works in its normal amplification mode, in other words F1, S1 and S4
switches are on while S2 and S3 are off. In the next phase, the amplifier is working in compensation
mode, switches S1, F2 and S4 are off while S2 and S3 are on. This method is sometimes referred to
as open loop offset cancellation.

Fig. 1.9. Auto-zeroing scheme with output offset storage

 6
There is a different auto-zeroing scheme that can be realized with input offset storage. Sometimes it
is called closed loop offset cancellation. As in fig. 1.10, in the first half of each clock cycle S4, F2,
and S1 are open, but S2 and S3 are closed. in the second half, S4, F2, and S1 are closed while S2
and S3 are open.

Fig. 1.10. Auto-zeroing scheme with input offset storage

As in chopper amplifiers, auto-zeroing compensated amplifiers suffer from charge injection, there-
fore an architecture with a supplementary amplifier has been designed to be used to reduce sensitiv-
ity to charge injection as shown in fig. 1.11. The amplifier operates in the following manner: during
the first phase when F1 is closed, the amplifier G1 amplifies the input signal, in the succeeding
phase, F1 is open and F2 causes the inputs of G1 to be connected to each other, this results in an
output current (I1 due to input offset), the resulting current on I1 creates a voltage on C1 capacitor,
the given capacitor supplies the supplementary amplifier G2, through that, offset compensation
takes place.

Fig. 1.11. Auto-zeroing scheme with supplementary amplifier

As mentioned earlier, auto-zeroing compensated amplifiers are inappropriate to be used in continu-

ous-time applications, because of that reason, a different architecture has been designed for that
purpose, it is called ping-pong. Ping-pong amplifiers use two identical auto-zero amplifiers that are
fed with two clock signals (180 degrees apart). The two amplifiers work parallelly (as depicted in
fig. 1.12).
 7

Fig. 1.12. Ping-pong auto-zeroing scheme

When the clock signal F1 is high and F2 is low, the amplifier G1 works in amplification mode
while G3 is in compensating mode, during the next clock cycle (F1 is low and F2 is high), G3 am-
plifies the input signal while G1 compensates for offset, this will lead to a continuous signal exist-
ence at the output, thus convenient for continuous-signal applications, additionally, this drastically
reduces the flicker noise [12]. The only disadvantage of that method is occurrence of voltage spikes
due to switching at the output (Vb1 and Vb2), it can be reduced by using active integrators instead
of the capacitors [18]. An additional design exists (as shown in fig. 1.13) that solidly lessens chop-
per ripples, a combination of both auto-zeroing and chopping is used. That technique works because
auto-zeroing reduces the ripples and the noise folding issue caused by auto-zeroing is solved by
modulating to a larger frequency. A downside of that technique is reduction of signal to noise pow-
er because auto-zeroing’s output is discrete.

Fig. 1.13. Implementation of both chopping and auto-zeroing

2. Design of The Operational Amplifiers

The very first thing before attempting to reduce the offset is indeed implementing the operational
amplifier, two operational amplifiers have to be designed (a typical single-output operational ampli-
fier and a fully-differential operational amplifier), the single-output operational amplifier is used in
auto-zeroing configurations, while the fully-differential operational amplifier is needed for the
schemes that involve chopping, certain configurations may use two or more operational amplifiers,
 8
in such case, the other operational amplifiers are referred to as, auxiliary or supplementary op-amps,
they serve the main operational amplifier. In this part, the schematic diagram of both of the opera-
tional amplifiers, their transient analysis results, magnitude and phase responses are provided.

2.1. Schematic of a single-output operational amplifier

A standard three-stage operational amplifier topology is chosen here, the first stage is differential
amplifier, the next stage is gain-stage (common-source) followed by the last stage which is a buffer,
buffer is used when the amplifier is used to drive large resistive or capacitive loads which is re-
quired in practice (as depicted in fig. 2.1). Table 2.1 shows the transistor widths/lengths used in the
op-amp and the biasing circuits. The design uses 50 nm CMOS technology, and the width of both
transistors are quite large as in all analog circuits, while for the biasing circuit in fig. 2.1, two tech-
nologies are used which are 100 nm and 5u, different widths are used for 100 nm transistors.

Table 2.1 Sizes of the used transistors

Transistor-type W/L
P-MOS 1u / 50n
N-MOS 0.5u / 50n

Fig. 2.1. A single-ended op-amp circuit

Like all op-amps, the given single-ended op-amp has two differential inputs, they are labeled as Vn
and Vp, there is only one output which is Vout, the biasing circuit is shown as a symbol in fig. 2.1
and its circuit is provided in fig. 2.2. The biasing circuit produces a stable DC voltage of 353 mV
that is fed to the amplifier through Vbias wire.
 9

Fig. 2.2. The biasing circuit

For the sake of convenience and simplicity, the previous op-amp is now turned into a symbol, called
(OP AMP) as depicted in fig. 2.3, at this point, the op-amp must be tested to ensure it operates
properly, AC (magnitude and phase responses) and transient analyses are performed, the offset here
is not considered (VOS = 0). The amplifier is driven by two differential input sources with an am-
plitude of 250 mV, having a DC component of 500 mV and the frequency is 1 kHz, the differential
inputs are generated by using two voltage-dependent voltage sources, one with a gain of 1 and the
other with a gain of -1.

Fig. 2.3. Test bench scheme of the single-ended op-amp

The transient analysis result is presented in fig. 2.4 below, the purple signal is the differential input,
and the red signal is the resulting output, the amplification is visible, if desired, gain can be in-
creased by modifying the feedback and the input resistors.
 10

Fig. 2.4. The differential input signal (purple) and the obtained output (red) for the single-
ended op-amp circuit in figure 2.3.

It is also useful to know how the proposed operational amplifier behaves in frequency domain, the
magnitude and phase responses have been measured (fig. 2.5 and fig. 2.6), bandwidth can be ob-
tained from the magnitude response, typically the frequency at which the gain is 0 dB is the highest
operating frequency, the given amplifier has a bandwidth of 47 MHz and a DC gain of 69.78 dB.

Fig. 2.5. Magnitude response of the single-ended op-amp

Additionally, the phase response of the given op-amp is provided in fig. 2.6:

Fig. 2.6. Phase response of the single-ended op-amp

 11
2.2. Schematic of a fully-differential operational amplifier
As mentioned earlier, for certain offset cancellation techniques (such as chopping), a fully differen-
tial amplifier is used because more than one feedback path is needed, the schematic of this type of
op-amp is provided in the following figures below (fig. 2.7, fig. 2.8 and fig. 2.9), due to its large
size, the amplifier is broken into three parts (input stage, output stage and the feedback loop).

Fig. 2.7. Differential-input stage of the fully differential op-amp

The differential inputs are VinP and VinN, VCM is common-mode voltage, which is 500 mV in this
case, the outputs of the first stage are given to the inputs of the later stages, they are labeled as
(vodn and vodp).

Fig. 2.8. Output stage of the fully differential op-amp

 12
The output stage is given in fig. 2.8., the differential outputs are VoutP and VoutN, in addition to
that, negative feedback loop (fig. 2.9) is needed to ensure stability of the system and the bias circuit
is the same as for the single-ended op-amp, thus it is not shown here.

Fig. 2.9. Feedback loop of the fully differential op-amp

Now the fully differential op-amp circuit may be tested (fig. 2.10) to make sure it works correctly
before proceeding to using it in offset cancellation configurations, for convenience, as for the previ-
ous op-amp, the large schematic is represented as a symbol, called (Fully_Differential), the feed-
back resistors are chosen to have a gain value of 5 (can be easily calculated: 100 kΩ / 20 kΩ = 5),
the loads are two capacitors having a value of 250 fF.

Fig. 2.10. Test bench of the fully differential op-amp

The transient analysis result is provided in fig. 2.11, the red signal is the input (has a peak-to-peak
value of 196 mV), while the blue signal is the output signal (with a peak-to-peak value of 966 mV).
It may be concluded that the amplifier amplifies the signal correctly because 966/196 = 4.9, which
is very close to 5 (the ideally calculated gain value).
 13

Fig. 2.11. Differential input (red) and output (blue) signals for the fully-differential op-amp

Likewise, magnitude and phase responses of the fully-differential amplifier has been measured and
provided in fig. 2.12 and fig. 2.13, respectively.

Fig. 2.12. Magnitude response of the fully-differential op-amp

It can be seen that the fully-differential amplifier has a wider bandwidth, the bandwidth is 493
MHz, that is much larger in comparison with the previous op-amp but at the cost of its gain (47 dB)
and its design complexity.
 14

Fig. 2.13. Phase response of the fully-differential op-amp

At this stage, the two required operational amplifier schemes are realized, they are ready to be used
in offset cancellation schemes, offset is added deliberately (modeled as a voltage source) and then
offset reduction techniques are provided, the effect of adding offset voltage is demonstrated by us-
ing the test bench circuit illustrated in fig. 2.14.

Fig. 2.14. Modeling offset voltage

Fig. 2.14 above consists of two differential inputs (Vplus and Vminus), The capacitor with value of
250 fF acts as a load, offset is added to the positive input (as a DC voltage source of ±50 mV), the
effect of this small voltage is depicted in the following two figures (fig. 2.15 and fig. 2.16). Adding
a positive offset voltage with a value of +50 mV causes clipping at the upper-peak (top) of the sig-
nal (blue signal in fig. 2.15).
 15

Fig. 2.15. The effect of adding positive voltage offset

While adding a negative offset voltage with a value of -50 mV clips the lower-peak (bottom) of the
signal (blue signal in fig. 2.16).

Fig. 2.16. The effect of adding negative voltage offset

3. Design of Op-Amps with Dynamic Offset Cancellation

Offset voltage is a dominant error source for operational amplifiers especially at low frequencies, as
mentioned earlier, it occurs due to mismatch in transistor sizes, offset is a very vital parameter for
operational amplifiers that is used in various applications for instance, calibrating signals, sensitive
sensor interfaces, high accuracy instrumentation devices and many more. There are three major
techniques that are commonly used to remove/reduce offset voltage, these are trimming, auto-
zeroing, and chopping. Trimming is usually done during fabrication to eliminate offset by making
sure the sizes of transistors match, it does not belong to the category of dynamic offset cancellation
techniques, for that reason, this technique is mentioned only theoretically, and it is not realized in
this work. Auto-zeroing’s principle of operation is based on sampling, the offset voltage is captured
in a phase (the value is kept on a capacitor with an opposite polarity) and then subtracted in next
clock phases, while chopping operates based on continuous-time modulation, both the input signal
 16
and offset voltage are modulated to a carrier signal with a much higher frequency than the input
signal. Because the offset undergoes modulation, a ripple is observed at the amplifier’s output. Both
mentioned techniques are dynamic techniques that continuously reduce offset, they also reduce low
frequency noise and offset drift as a function of temperature or time, in this part, the auto-zeroing
and chopping methods are implemented practically with different architectures, these include ping-
pong amplifier, auto-zeroing with supplementary amplifier and a combination of both chopping and
auto-zeroing. their results are compared, and their PSS (periodic steady state) noise differences are
summarized in a table, due to the existence of clock signals, normal input and output referred noises
cannot be used for this category of circuits, hence, PSS noise is used for that purpose.

3.1. Auto-zeroing
A fundamental auto-zeroing amplifier is provided in fig. 3.1, the proposed amplifier operates in the
following manner, when the input clock C1 is on (C2 is off), both of the Vn and Vp are shorted, the
feedback loop is closed and the offset that appears at the output is fed back into the input, thus the
capacitor (C0 - 5 nF) is charged to the offset voltage value, on the other cycle when C2 is on (C1 is
off), the amplifier works as usual, meaning that the inputs are fed, at the same time the capacitor
charge compensates the offset voltage because they are opposite in sign, this will result in zero off-
set voltage at the input.

Fig. 3.1. Auto-zeroing scheme

The clock signals mentioned earlier are shown in fig. 3.2, both signals have a duty-cycle of 50%
and a frequency of 20 kHz, it is assumed they are ideal clock signals, non-idealities in the clock
pulses such as clock-skew cause residual offsets.
 17

Fig. 3.2. C1 and C2 clock signals used in the auto-zeroing circuits

Transient analysis may be run to observe the input and output signals, fig. 3.3 depicts the differen-
tial input signals (amplitude is 50 mV and DC component is 500 mV), possessing a frequency of 1
kHz.

Fig. 3.3. Differential input signals used in auto-zeroing amplifier

The output signal of the auto-zeroing amplifier (black signal) along with the differential inputs are
provided in fig. 3.4, it can be observed that the signal is a sampled version of the amplified inputs,
therefore it is not continuous but that is not an issue for this architecture, since it is not used for con-
tinuous-time applications. The visible spikes in the output signal can be eliminated using a low-pass
filter (LPF).
 18

Fig. 3.4. Output and input signals of the auto-zeroing amplifier in time-domain

A discontinuity exists at the beginning of the output signal, that is due to the capacitor C0, it takes
some time to charge and start compensating (this duration is less than 350 us) as shown in fig. 3.5,
then the capacitor carries a value of -10 mV, because the fed offset is 10 mV.

Fig. 3.5. Capacitor C0 charging to the desired voltage

Later on, the PSS analysis is executed to check that the auto-zeroing amplifier works properly, the
PSS analysis can be done in both time domain and in frequency domain for noise calculation, time-
domain PSS is provided in fig. 3.6, it is a replica of the output signal in transient analysis and that is
a good indicator, from that we may conclude that the amplifier works correctly, in addition to that,
it gives a clearer view of the output signal (because only two periods are shown here).
 19

Fig. 3.6. PSS time-domain output signal

Moreover, a comparison of the output signal (blue signal) and the signal appearing on the capacitor
C0 (red signal) is done to clearly see how offset voltage of 10 mV is removed (fig. 3.7).

Fig. 3.7. Comparison of output signal with the signal appearing on the capacitor C0

As mentioned previously, PSS analysis can be used to observe noise versus frequency, the result of
such analysis is provided in fig. 3.8:

Fig. 3.8. PSS noise comparison for the AZ amplifier with (red signal) and without compen-
sation (blue signal)
 20
From the PSS noise analysis in fig. 3.8, it is possible to see how the noise is reduced from 28.696
uV/√(Hz) to 7.821 uV/√(Hz) and the thermal noise is 179.712 nV/√(Hz), the noise reduction is not
that powerful in the given architecture, therefore other schemes for auto-zeroing are realized.

3.2. Auto-zeroing with an auxiliary amplifier

Another topology exists for auto-zeroing that includes a supplementary (auxiliary) amplifier in its
feedback path, this not only significantly reduces the flicker noise, but it also reduces the amplifi-
er’s sensitivity to charge injection. Its diagram is shown in fig. 3.9, when the C1 clock pulse is high,
the differential input signals are fed to the upper op-amp, it amplifies the input signal while all the
transistors with C2 clock are off, in the next phase, the upper op-amp does not get any signal from
the differential input sources but from the lower op-amp’s output and the common mode voltage
(VCM) which enforces the amplifiers to keep the signals at 500 mV DC voltage. The capacitor in
this case is placed between two transistors, in other words, it is fed by the Vp input signal when C1
is high and by VCM when C2 is high, thus, it captures the offset voltage much faster and considera-
bly reduces flicker noise.

Fig. 3.9. Auto-zeroing amplifier with a supplementary amplifier

Running transient analysis simulation provides such signals (fig. 3.10), the output signal (black)
looks quite similar to the output signal of the first auto-zeroing scheme but the difference in that
case is, the compensation takes place almost immediately, that is because the capacitor here (fig.
3.11) charges much quicker than the previous case, despite increasing the circuit’s complexity, us-
ing a supplementary amplifier is superior to using only one amplifier due to its better performance.
 21

Fig. 3.10. Auto-zeroing with a supplementary amplifier’s transient input and output signals

The voltage appearing on the capacitor in the given case comes with ripples (fig. 3.11), it is a DC
voltage in the range of -10.0195 mV to -10.0145 mV, the variation is in range of 5 uV, despite the
fact, this is not a considerable amount, its noticeable and caused by charge injection.

Fig. 3.11. Voltage appearing on C0 capacitor in fig. 2.25

Habitually, the PSS noise analysis is done to see the noise level before and after compensation, the
result is presented in fig. 3.12, the noise is reduced from 37.506 uV/√(Hz) to 4.940 uV/√(Hz), that
is 158% better than the first AZ amplifier.
 22

Fig. 3.12. PSS noise comparison for the AZ amplifier with a supplementary amplifier before
compensation (blue signal) and after compensation (red signal)

3.3. Continuous-time auto-zeroing

The previous two auto-zeroing amplifiers were meant to be used in non-continuous applications,
they are good in certain applications but should not be used when continuous-time signals are need-
ed, as in voice amplifiers or analog-to-digital converters. A configuration exists that is commonly
known as continuous-time auto-zeroing amplifier (CTAZ or ping-pong amplifier), it is a broad term
that can be used for any amplifier that implements two identical sub-amplifiers with opposite clock
pulses to achieve a continuous signal at the output. A realization of such amplifier is given in fig.
3.13. It’s working principle can be summarized in two stages, the first stage when C2 is high (C1 is
low), the upper amplifier receives the signal from the differential inputs, amplifies it and feeds it to
the output (Vout), at this stage, the lower amplifier’s inputs are shorted and it’s in compensation
mode, in the next stage, when C2 turns into low (C1 is high), the lower amplifier amplifies the sig-
nal while the upper amplifier compensates for offset and the output voltage is taken from the lower
amplifier, this results in a continuous signal at all times at the output.
 23

Fig. 3.13. Continuous-time auto-zeroing amplifier

The differential inputs and the output signal of the CTAZ amplifier in fig. 3.13 are presented in fig.
3.14, the black signal refers to the output, it is a continuous signal with a DC component of 500
mV, this shows that the offset of 10 mV at the input is removed, a proof that the amplifier is work-
ing flawlessly. The visible voltage spikes that can be easily resolved with a low-pass filter. The be-
ginning of the output signal is distorted since the amplifier takes some time to start compensating.

Fig. 3.14. CTAZ’s input and output signals

The PSS noise (refer to fig. 3.15) shows an incredible noise performance, the noise is lessened from
28.6967 uV/√(Hz) to 62.8146 nV/√(Hz).
 24

Fig. 3.15. PSS noise comparison for the CTAZ amplifier before compensation (blue signal)
and after compensation (red signal)

To remove the voltage spikes and other random high frequency components that are caused by
switching operations, a Butterworth LPF is connected to the output of the CTAZ amplifier as illus-
trated in fig. 3.16, the filter’s order is 7 with an input and output impedances equal to the CTAZ’s
feedback resistor value (100 kΩ). The corner frequency is equal to 8 kHz because the clock fre-
quency is 20 kHz and the input signal is 1 kHz, the corner frequency should be higher than the input
signal and less than the clock signal, so 8 kHz is a suitable value, picking a different value in the
range of 2 kHz to 10 kHz does not result in a major difference.

Fig. 3.16. Adding a LPF to the CTAZ amplifier’s output

The filter’s output is shown in fig. 3.17 (black signal), the beginning of the signal is expectedly de-
formed because offset cancellation has not taken place yet, and the signal is not in phase with the
inputs because a filter causes a time delay, in practice that does not cause any trouble, it can be
fixed if desired with a phase-locked loop (PLL).
 25

Fig. 3.17. CTAZ amplifier’s filtered output

The discrete Fourier transform (DFT) of the output signal is taken in fig. 3.18 to observe the differ-
ences in frequency components of the output signal before and after offset compensation. The com-
pensated signal which is colored in red has much less power along the entire frequency spectrum,
that is particularly crucial in lower frequencies, the non-compensated signal has a power of -6.04
dB at 0 Hz, while the compensated signal lowered this value to -21.16 dB.

Fig. 3.18. DFT of the output signal with (red) and without compensation (blue)

3.4. Chopping
In contrast to auto-zeroing, chopping amplifier does not need any capacitor, it compensates offset
voltage using modulation rather than charge compensation, a basic chopper amplifier is presented in
fig. 3.19. It consists of two choppers, a fully differential operational amplifier, and a Butterworth
low-pass filter. An offset of 10 mV is added as a DC voltage source.
 26

Fig. 3.19. Chopper amplifier circuit

The block (Fully_Differential) amplifier is the same fully differential operational amplifier provided
in section 2 (fig. 2.7. to fig. 2.9.), the chopper consists of four NMOS transistors, its configuration is
as depicted in fig. 3.20:

Fig. 3.20. Chopper schematic

The chopper is driven by two clock frequencies of 20 kHz (C1 and C2 are out of phase by 180 de-
grees) they alternate between 1 V and -1 V as in fig. 3.21, as a rule, the clock frequency should be
much higher than the frequency of the input signal. During one cycle “in1” is connected to “out1”
and “in2” is connected to “out2”, during the other cycle, “in1” will be connected to “out2” and
“in2” will be connected to “out1”.
 27

Fig. 3.21. Clock signals used in chopper amplifier

The chopper amplifier is fed with two differential sinusoidal signals, with an amplitude of 100 mV,
frequency of 1 kHz and a DC component of 500 mV as illustrated in fig. 3.22:

Fig. 3.22. Differential input signals fed to the chopper amplifier

The time-domain (transient analysis) results for the chopper amplifier circuit in fig. 3.19 without
compensation is given in fig. 3.23, to turn off compensation, the C1 and C2 clocks may simply be
replaced with a DC voltage source of 1 V and 0 V respectively, the effect of offset voltage (10 mV)
is visible, the differential outputs’ DC component is not 500 mV as supposed to be, the signals are
displaced, the peak difference is now 10.6 mV (that is nearly equal to the imposed input offset volt-
age).
 28

Fig. 3.23. Chopper amplifier’s outputs without compensation

After observing the chopper amplifier’s output before compensation, the offset compensation may
be started by replacing C1 & C2 DC sources with clock signals, the first chopper acts as a modula-
tor, it modulates the inputs to a larger frequency (in this case, its 20 kHz), the fully differential op-
amp as usual amplifies the modulated signal and feeds it to the second chopper that acts as a de-
modulator, the output signals at this point (as shown in fig. 3.24) appear as a sampled signal due to
switching, but in fact, it’s a continuous signal.

Fig. 3.24. Chopper amplifier’s output after offset compensation (before filtering)

By simply passing the outputs to a LPF, a continuous offset free signal can be obtained as in fig.
3.25:
 29

Fig. 3.25. Chopper amplifier’s output after offset compensation and filtering

The PSS noise analysis is not limited to be used in auto-zeroing amplifiers only, it can be used in
chopper amplifiers as well, fig. 3.26 shows to what extent a chopper amplifier reduces noise, before
compensation the noise was 84.764 uV/√(Hz), while after compensation, this value went down to
1.127 uV/√(Hz), in other words, after compensating for offset, the amplifier is 75 times less noisy.

Fig. 3.26. PSS noise comparison for the chopper amplifier before compensation (blue signal)
and after compensation (red signal)

The DFT samples taken illustrated in fig. 3.27 further validates the point, output signal’s power at 0
Hz is reduced from -37.29 dB to -45.23 dB.
 30

Fig. 3.27. DFT samples of the chopper amplifier’s output with compensation (red) and with-
out compensation (blue)

3.5. A combination of chopping and auto-zeroing

A combination of both chopping and auto-zeroing can be used to achieve better noise performance,
that is a more sophisticated configuration despite its complexity because auto-zeroing part gets rid
of the voltage ripples caused by chopping, while chopping gets rid of the noise folding problem that
is caused by auto-zeroing. An example of such system is provided in fig. 3.28.

Fig. 3.28. Schematic of an amplifier using both chopping and auto-zeroing

The circuit consists of two choppers, placed in the input and the output, and two auto-zeroing am-
plifiers (upper and lower) are used to achieve a continuous-time signal at the second chopper’s in-
put, its operation can be explained simply by the two-phase nonoverlapping clock signals (C1 and
 31
C2). When C1 is one and C2 is zero, the upper auto-zeroing amplifier works in amplification mode
while the lower auto-zeroing amplifier compensates the input offset of 10 mV, the feedback loop
op-amp senses the voltage difference at the output of the main amplifier then the capacitors are
charged to this value, later they are amplified and subtracted from main amplifier’s output. In the
next clock period (when C1 is zero and C2 is one), the system works in a similar manner, but this
time the lower amplifier operates in amplification mode and the upper amplifier compensates the
offset. This results in a continuous signal as provided in fig. 3.29, though visually it looks like a dis-
crete signal due to sampling and modulation.

Fig. 3.29. Output voltage of an amplifier with chopping and auto-zeroing compensation

The voltage spikes and intermodulation products that are visible in fig. 3.29 can be taken out easily
with a low-pass filter. The LPF’s output is provided in fig. 3.30, it is a signal with removed offset
voltage (the signal’s DC component is 500 mV, that is the desired value, equal to the common-
mode voltage). The circuit takes around of 765.1 us to initiate compensation of offset voltage.

Fig. 3.30. Filtered output voltage of an amplifier with chopping and auto-zeroing
 32
Additionally, the used low-pass filter adds to that existing delay, as depicted in fig. 3.31, there is a
time delay of 285.7 us, that is equivalent to a phase difference of 102.87 degrees between the fil-
tered signal (black) and the unfiltered signal (red).

Fig. 3.31. Comparison of output signals of an amplifier using both chopping and auto-
zeroing with (black) and without (red) low-pass filtering

The flicker noise reduction can be observed from the PSS noise analysis as portrayed in fig. 3.32,
flicker noise is 405.811 uV/√(Hz) without using any type of compensation, this value is reduced to
381.234 uV/√(Hz) by using auto-zeroing only (choppers are turned off), however by enabling both
choppers and auto-zeroing, the flicker noise is greatly reduced to 29.810 uV/√(Hz) from 405.811
uV/√(Hz), in other words, flicker noise is reduced approximately by 1361%.

Fig. 3.32. PSS noise comparison for the amplifier with auto-zeroing & chopping

Interestingly, the flicker noise reduction rate for an amplifier using both auto-zeroing & chopping is
less than the CTAZ amplifier, that is because implementing an amplifier with a combination of both
 33
auto-zeroing and chopping needs at least four times more transistors, and that naturally leads to an
increase in the flicker noise.

3.6. Offset voltage reduction performance

In this section, the previously proposed operational amplifiers with dynamic offset voltage cancella-
tion techniques are compared in terms of their offset voltage reduction performance (i.e., to what
extent the offset voltage is reduced). The analysis can be done by measuring the output signal’s
maximum and minimum values, then their average value is taken which corresponds to the offset
voltage level after compensation. Fig. 3.33 illustrates the auto-zeroing amplifier’s output signal, the
average of the peaks is equal to 500.041 mV, since the input signal’s offset value (DC component)
was 500 mV and the added offset was 10 mV, a difference of 0.041 mV exists, because the amplifi-
er is unable to reduce it beyond that value (ideally to zero). In short, an offset voltage of 10 mV at
the input was reduced to 0.041 mV at the output.

Fig. 3.33. Auto-zeroing amplifier’s offset and peak voltages

Likewise, the measurements are done for an auto-zeroing amplifier with a supplementary amplifier,
its offset reduction performance is better, because the new offset voltage value after compensation
is 499.989 mV as depicted in fig. 3.34, this is 0.011 mV less than 500 mV (the desired offset value),
comparing it with the previous auto-zeroing amplifier (fig.3.33), this amplifier reduces offset by 3.7
times more than the previous auto-zeroing amplifier.
 34

Fig. 3.34. Auto-zeroing with a supplementary amplifier’s offset and peak voltages

Furthermore, the output signal of a continuous-time auto-zeroing amplifier with its peaks and aver-
age is provided in fig. 3.35, this type of amplifier produces and offset of 499.954 mV, almost close
to the ideal value of 500 mV, CTAZ amplifier performs better than the previously mentioned auto-
zeroing amplifiers (fig. 3.33 & fig. 3.34).

Fig. 3.35. Continuous-time auto-zeroing amplifier’s offset and peak voltages

Moreover, the same routine can be executed for the chopper amplifiers, the output signal of the
chopper amplifier is given in fig. 3.36, the compensated output’s offset value is 10.41 uV, as ex-
pected, this value is much less than the offset voltages in all the auto-zeroing amplifiers, it can be
noted that the offset does not contain the 500 mV component, because the output signal is taken
from the chopper’s differential outputs, in other words, the chopper’s output signals are subtracted
from each other (Vch1-Vch2), each of them possesses an offset voltage of 500 mV, thus it is re-
moved.
 35

Fig. 3.36. Chopper amplifier’s offset and peak voltages

Lastly, fig. 3.37 presents the output signal of an operational amplifier that implements both tech-
niques (chopping and auto-zeroing), the compensated signal’s offset voltage is 0.01535 mV larger
than the required offset voltage of 500 mV.

Fig. 3.37. Offset and peak voltages of an op-amp with both chopping and auto-zeroing

Its performance may be assessed as worse than continuous-time auto-zeroing amplifier but better
than chopping and the other mentioned auto-zeroing amplifiers (in sections 3.1 and 3.2).

3.7. Input-referred voltage noise power spectral density comparison

All the PSS noise analyses done previously in sections (3.1 to 3.5) were done to measure output-
referred noise power spectral density, but in order to have a more thorough understanding of the
amplifiers’ actual noise performance, input-referred noise PSD must be considered, as in data
sheets. Input-referred noise PSD values are achieved by simply dividing the output-referred noise
 36
PSD results by the gain (obtained from the amplifier’s magnitude response). In this work, the sin-
gle-ended amplifier has a gain of 69.78 dB, and the fully-differential amplifier has a gain of 47 dB,
this converts to voltage gains equal to 3054.9 and 223.8, respectively. Fig. 3.38 provides the input-
referred noise PSD measurement for the auto-zeroing amplifier in section 3.1, the flicker noise is
reduced from 9.29 nV/√(Hz) to 2.53 nV/√(Hz), the flicker noise value is quite low, and it is compa-
rable to commercial state of the art operational amplifiers.

Fig. 3.38. PSS input-referred noise PSD comparison for the basic auto-zeroing amplifier
with (red signal) and without compensation (blue signal)

It is worth to mention that the ratio between the flicker noises before and after compensation is
equal for input-referred noise PSD and output-referred PSD. The input-referred noise PSD for the
op-amp (auto-zeroing with supplementary amplifier) in section 3.2 is given in fig. 3.39, the flicker
noise is brought down from 12.153 nV/√(Hz) to 1.616 nV/√(Hz).

Fig. 3.39. PSS input-referred noise PSD comparison for the AZ amplifier with an auxiliary
amplifier with (red signal) and without compensation (blue signal)
 37
The continuous-time auto-zeroing amplifier has the lowest flicker noise among all the proposed
amplifiers, the flicker noise is lessened from 9.396 nV/√(Hz) to 20.56 pV/√(Hz), in other words by
45684.5%, that is depicted in fig. 3.40.

Fig. 3.40. PSS input-referred noise PSD comparison for the CTAZ amplifier with (red sig-
nal) and without compensation (blue signal)

Moreover, input-referred noise PSD for the chopper amplifier is given in fig. 3.41, flicker noise is
brought down from 337.176 nV/√(Hz) to 4.49 nV/√(Hz), this value is quite low, considering the
fact that the amplifier has a very high bandwidth (493 MHz), and the compensation part of the
schematic has a pretty simple and low cost configuration, it consists of only two choppers (8 tran-
sistors).

Fig. 3.41. PSS input-referred noise PSD comparison for the chopper amplifier with (red sig-
nal) and without compensation (blue signal)

Lastly, the same analysis is done for the most complicated scheme in section 3.5 (op-amp imple-
menting both chopping and auto-zeroing techniques), fig. 3.42 shows that the flicker noise is 747
 38
pV/√(Hz) with no compensation, this is lowered to 54.87 pV/√(Hz). In comparison with the previ-
ously mentioned four configurations, this comes in second place, because the flicker noise after
compensation is still more than the flicker noise of the continuous-time auto-zeroing amplifier, nev-
ertheless, that still makes this circuit useful due to its high bandwidth, low voltage ripples at the
output and immunity to noise-folding problem.

Fig. 3.42. PSS input-referred noise PSD comparison for the amplifier with auto-zeroing &
chopping

3.8. Thermal performance

Like all electronic circuits, the biasing circuit used in this work is affected by changes in tempera-
ture, fig. 3.43 depicts biasing current as a function of temperature. The biasing circuit can operate
normally in the temperature range of -40 °C to 85 °C. The biasing current increases with an increase
in temperature, higher temperatures lead to a decrease in the transistor threshold voltage and reduc-
tion in carrier mobility, this effect increases the drain current.

Fig. 3.43. Bias current versus temperature

 39
Similarly, the bias voltage is also not immune to variations in temperature, fig. 3.44 shows bias
voltage versus temperature, the voltage reduces at a rate of 0.597 mV/C, nevertheless, these changes
do not cause op-amps to malfunction, heat sinks are used, and negative feedback keeps the amplifi-
ers stable.

Fig. 3.44. Bias voltage versus temperature

Summary
All the proposed dynamic offset op-amps were simulated using PSS and transient analyses, the ob-
tained results which include output-referred noise power spectrum density and offset voltage reduc-
tion performance of all the proposed dynamically compensated operational amplifiers are summa-
rized in table 3.1, table 3.2, respectively.
Table 3.1 Output-referred noise PSD
Configuration Output-referred Output-referred Reduction
noise PSD before noise PSD noise percentage
compensation after compensation (%)
(uV/√Hz) (uV/√Hz)
Auto-zeroing (AZ) 28.696 7.821 366.89
AZ with supplementary amplifier 37.506 4.94 759.08
Continuous-time auto-zeroing 28.696 0.0628146 45684.76
Chopping 84.764 1.127 7514.98
Chopping & auto-zeroing 405.811 29.810 1361.29

Table 3.2 Input-referred offset voltage reduction rates

Configuration Input offset Input-referred offset voltage Reduction
voltage (uV) after compensation (uV) rate
Auto-zeroing (AZ) 10000 20.575 486.026
AZ with supplementary amplifier 10000 5.5 1818.181
Continuous-time auto-zeroing 10000 23 434.782
Chopping 10000 5.21 1919.385
Chopping & auto-zeroing 10000 7.675 1302.931
 40
The input-referred noise PSD cannot be measured directly, it can be determined from the output-
referred noise PSD, using the following formula:
𝑆𝑜𝑢𝑡
𝑆𝑖𝑛 = (3.1)
𝑀𝑜𝑑𝑢𝑙𝑒 𝑔𝑎𝑖𝑛2

where – 𝑆𝑖𝑛 𝑎𝑛𝑑 𝑆𝑜𝑢𝑡 are the average power spectral density of noise voltage of the input and out-
put respectively, V2/(Hz); 𝑀𝑜𝑑𝑢𝑙𝑒 𝑔𝑎𝑖𝑛 is the voltage gain of the op-amp, it is provided in table
3.3:
Table 3.3 Input-referred noise PSD
Configuration Input-referred noise Input-referred noise
PSD before compensa- PSD before compensa-
tion (nV/√Hz) tion (nV/√Hz)
Auto-zeroing (AZ) 9.299 2.534
AZ with supplementary amplifier 12.153 1.616
Continuous-time auto-zeroing 9.396 0.020568
Chopping 337.176 4.493
Chopping & auto-zeroing 0.747 0.054874

The thermal performance was considered in section 3.8, the op-amps function properly in the tem-
perature range of -40 °C to 85 °C.
The power supply rejection ratio and the common-mode rejection ratio are provided in table 3.4,
PSRR and CMRR can be obtained from these formulas:

∆𝑉𝐷𝐷
𝑃𝑆𝑅𝑅 = (3.2)
∆𝑉𝑂𝑆

∆𝑉𝐶𝑀
𝐶𝑀𝑅𝑅 = (3.3)
∆𝑉𝑂𝑆

where – 𝑉𝐶𝑀 is the common-mode voltage; 𝑉𝑂𝑆 – is the offset voltage and 𝑉𝐷𝐷 – is the drain supply
voltage.

Table 3.4 PSRR and CMRR for the proposed op-amps

Configuration PSRR (dB) CMRR (dB)
Auto-zeroing (AZ) 104.103 98.08
AZ with supplementary amplifier 115.563 109.54
Continuous-time auto-zeroing 103.135 97.115
Chopping 116.033 110.012
Chopping & auto-zeroing 112.668 106.648
 41
Conclusion
In this work, a comparative analysis of CMOS operational amplifiers with dynamic offset cancella-
tion was done. The results of this analysis showed that the dynamic offset cancellation techniques
are an effective way to reduce the input offset voltage and its consequences such as flicker noise in
operational amplifiers.
Two operational amplifiers were designed (single-output and fully-differential) in 50 nm CMOS
technology, with a gain-bandwidth product (GBWP) of 47 MHz and 493 MHz, and an open-loop
gain of 69.78 dB and 47 dB respectively, both of them have an operating voltage range of 1 V. The
first configuration (basic auto-zeroing) reduced the offset voltage by only 486 times, while the best
configuration which is chopping, reduced the offset voltage by approximately 1919 times.
The results of the input-referred noise power spectral density analysis of the proposed operational
amplifiers show a flicker noise ranging from 20.57 pV/√Hz in the continuous-time auto-zeroing cir-
cuit to 4.5 nV/√Hz in basic auto-zeroing circuit at 1 Hz, that is a great reduction of flicker noise in
comparison with the previously implemented designs. Chopping technique is better than autozero-
ing due to the fact, that it is a continuous-time modulation technique that does not produce noise
folding and it is more power efficient. The chopper amplifier in this work reduced flicker noise by
75 times (from 337.1 nV/√Hz to 4.5 nV/√Hz), using only 8 transistors for modulation and demodu-
lation. But chopping has its cons, chopping induces ripples at the output. An advantage of auto-
zeroing is that it does not induce ripple and its discrete property is well cooperative with switched-
capacitor circuits. In brief, chopper amplifier and continuous-time auto-zeroing amplifier are reduc-
ing the flicker noise and input offset voltage more strongly, nonetheless, picking an operational am-
plifier for a specific application does not depend only on its flicker noise and offset voltage reduc-
tion capability. For instance, in continuous-time applications such as in analog-to-digital converters,
continuous-time auto-zeroing must be used, while for amplifying a trigger signal from a sensor, a
basic auto-zeroing amplifier can be used despite its humble qualities when compared to other more
sophisticated amplifiers.

Acknowledgements
I would like to express my deep gratitude to my supervisor, Associate Professor (Balashov E. V.)
in Peter the Great Saint Petersburg Polytechnic University for his guidance and help during the
writing of this work. Additionally, my deepest appreciation goes to my parents for their endless
love, encouragement, and support. I also thank my dearest friend (Nikolai Kirichenko) for helping
me during my stay in Russia.
 42
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