2 Microprocessor and tieracontroler i Ft diagram of 8086 microprocessor: gr 1} The following fg, shows the block diagram of 8086 yp. 2) The 8086 mp is divided into two independent functional pans, ave Uni (BAU) (b) Execution Unit (EU) Bus la EIR \< ntarace —) _ / Sains Interface Unit (B1U) “ S _ The BIU sends address, fetches instruction from memory, read data from ports/memory and write data to ports/memory. in other words BIU handles transfer of data and address on uses for execution Unit. It consists of following parts Instruction Queue: To speed up execution of program, BIU fetches 6 instruction bytes ahead of time from ind store them for EU in the FIFO register, called queue. 2) Segment Registers: '6-bit segment registers are used to store 16-bit starting address of nieniury segments. BIU containsExecution Unit(ED: Ger te Execution Unit of ro ielis BIU where to fetch instructions or ab deed jnstrvction aud executes them. Following sections describe functional part of RU Flag is a flip-flop, which indicate some condition (status). The 8086 ha 6-bit flag register with 9-active flags 2 eee ee Registers: 8086 has 8 general purpose registers, labeled as AH, AL, BH. BL, CH, CL, DH and DL. These registers can be used individually ro ose of8 bit data. The AL register is also called as accumulator. These registers in certain pa can be used as 16-bit registers. These pairs are AH and AL (AX), BH and BL (BX), C and CL (CX), DH and DL (DX). 3) Stack Pointer (SP): The 8086 allows to sei 64 KB of memory as siack. The 16-biff starting address of stack is stored in stack pointer. ALU (Arithmetic Logic Unit): All arithmetic and logical operations are performed in| ALU. The result of arithmetic operation is transferred to the corresponding register via data bus. many operating modes do 6086 ‘plain them in brief. OR Explain operating modes of 8086 microprocessor. OR Explain minimum mode of operation of 8086 microprocessor. OR__Explain: (i) Minimum mode operation (ii) Maximum mode operation. ol F Operating Modes of 8086:44. 1) There are two modes of operation for Intel 8086, nameiy the minimum mode « maximum mode. 2) The level of the pin MV/AX decides the operating mode of R024 3) When MN/MY is high the CPU operates in the minimum mode When it is tow the CPU operates in the maximum mode. 4) From pin 24 to 31 issue two different set of signals the CPU operates in minimum mode The other set of signals is issued when the CPU operates in maximum mode. Thus the pins from 24 to 31 have i Miniinum Mode operation: # ee ion 1) When onl is to be used i ) n only one 8086 CPU is to be used in 2 Microcomputer system the SU86 is used i mode the CPU issues the contro! signals 4 re One set of signals is issued when minimum mode of operation. In this required by memory and V/O d 2) All the syste single processor ugh (on SV) the CPU Operates in the minimum 3 and 32 to a¢ i mode are commoa to doth a1 und me A cuntmuin eal cunion modes ny HOLD —¥ ‘oR [sr J Minimum Mode Operation Maximum Mode Operation Q4 Differentiate minimum and maximum mode operation. UNIT: 8086 Architecture Toa mul tiprocessor syst item it operates in the maximum mode. Each processor can execute its own program. Some system Tesources (global r System resources (private) are ay Tn case of maximum mode of Controller which is used with 8086 for this very purpose. When tv/H4¥ is low (on 0 V) the CPU operates in the maximum mode, Pins trom 1 to 23 and 32 €sources) are common to all the Processors and some ssigned {0 the specific processors Speration control signals are issued by Intel 8288 bus i ‘0 40 are common to both modes, while pins 24 to 31 serve different purpose in minimum and maximum modes. ‘The minimum mode configuration of the Pins from 24 to 31 is as QSi, QS. 5, .5,,55, LOCK. RO’ GT, and RO/Gi, . Oifferentiate between minimum and maximum mode operation with any 2 points, and “Maximum Mode Operation is as follows. | Ina single-processor system, 8086 | In a multiprocessor system, 8086 minimum mode. operates in the maximum mode. | In case of maximum mode of operation control signals are issued by Intel 8288 | bus controller which is used with 8086 | for this very purpose. { In caie of minimum mode of operation | the CPU issues control signals required ! by memory aad /O devices. When (:v/30¥is high (on 5 V) the | When AwW/TEVis low (on 0 W) the | CPU operates in the maximum mode | CPU operates in the maximum mode | | Some system resources (global | | resources) are common to all the | | processors and some system resources | (private resources) are assigned to the | | specific processors. _ ‘mum mode configuration of | The minimum mode configuration of as NFA, ALE | the puns trom 24 10 31 is as Q: 5,.5,,5;. TOCK. ROG he system resources are dedicated le processor | | RN PublicationoR Sol ) 2) 3) 4) 5) 6) ly 2) 3) 4) 5) 6; 4 cameo ealster organization of 8086 jy le SRUCLOPTOCESSOF and Microcontroller xplain general UNIT I: 8086 Architecture Purpose registers of 8086 np, MEOVATAET JW15(5) 5 Expl aR — sania eee eee Explain functian of each ¢ register, ON | 8086 has powerful set of reg registers. All o€ them are 16-bit regi: ‘The general purpose ceyiste S known as generat Purpose and special purpose ers. can be used as 16-bit or 8-bil register, The special purpose rogisters are uscd as segment re as offset storage registers for particular addr The Intel 80R6 mp contains the following reg a. General purpose registers, Bislers, pointers, index rogisters or sing modes, ster. are oe Accumulator AX Goneral purpose b. Pointer and Index Registers aera iagese ©. Segment Register Counter cx [CH 4. Instruction Pointer mene ‘stack pointer SP. Polntor and ©. Status Flags, Base pointer eP Indox The register organization of 8086 jp | Soweemnaex | si] Rogiter t 2 Destination index Ci is also known as programming Code Segment | cS] Segment model. Dato Segment Ds Rogister The fol fi hows the | fu eeament [a6 lowing figure shows the | fyvxseiment | $8 register organization of 8086 ip. lnstruction Pointer ° i L ‘Status Register FLAGS There are four 16-bit general purpose register namely as AX, BX, CX and DX. (in short they are known as A, B, C and D register) Each of these 16-bit register are further subdivided into two 8-bil registers such as AH, AL, BH, BL, CH, CL, DH and DL. These register can be used as 16-bit register or 8-bit registers. ietter H & L specify higher and lower byte of registers. ‘X’ in AX, BX, CX and Dx, stands for ‘eXtended’ register. Therefore there are total 8 8-bit general purpose register which can be used as four 16- bit general purpose register as well. All general pucpose register of the 8086 mp can be used for arithmetic and logical operations Accumulator AX Genera! purpose Base 8x Register Counter CX Data ox | Register AX scrvey as a 16-bit accumulator, wil the lower X-bits of AX designated as AL and Wigher fbi as AH aL can Jas wn 4-01 accumulator tor 8-bit operation, FS Fa Gam 1, eecIROWICS a) ET | ¥*Advance Microprocessor and Microcontroller _ UNIT I: 6086 Architecture 8) BX, CX and DX serve as general purpose as well as special purpose registers. 9) The register BX can be used as ‘Base’ register for the computation of memory address, In 8086, memory address is calculated using the contents of the segment register and effectively memory address. 10) The register CX is also used as a counter in case of multi-iteration instructions. When the content of CX becomes zero such instructions terminate the execution. 11) The register DX is also used for memory addressing when data are transferred between V/O port and memory using certain I/O instructions. Q7 Give the function of different registers of 8086 yp Q Explain inction of SP and BP In 8086 y (ay Explain the function of: (i) Index registers (ii) Stack pointer Bem Sol Pointer and Index ter: (1) There are following four registers in the group of pointers and Index registers. stack pointer SP Pointer and BP Index SI Register DI (2) These are of 16-bits. They can also be used in most arithmetic and logic operations. (3) These registers are usually used to hold offset addresses for addressing within a segment. Offset addressing reduces program size by eliminating the need for each instruction to specify frequently used addresses. (4) The pointer and index register group is further divided into the pointer sub-group (containing the SP and the BP registers) and the index sub-group (containing the SI and DI registers). (5) The Pointer registers are used to access the current stack segment. The index registers are used to access the current data. (Stack segment and data segment arc specific areas of memory.) (6) Unless otherwise specified in the instruction, stack pointer registers refer 10 the current stack segment while index register refers to the current data segment. jt ter {Q. Explain Stack pointer EERSERIES Stack Pointer (SP): Most microprocessors have a single sfack pom regy called the SP. But 8086 has an additional pointer into the stack called 1 pointer BP register ogister contains address of ths top mem y Tacation tie curreni stack 6p usually used 8 Sc PAPE IN (Sem 1VcNF& arenes Gre icroprocessor and Microcontroller Draw flag register of gog6 Err P and explain the function of OR Draw and explain flag register of 8086 p. a OR __Explain control flag of 8086 Microprocessor. Sol Flag Rey of 8086 mp: $086 mp has 16-bit flag register with 9 active fla Program status word (PSW. i: 7 bit positions of the status register remain unused. 3) Out of 9 flags, 6 are conditional flags and three are control flags (unconditional). 4) The following figure shows structure of flag register of 8086 mp. BaNse sk on oe UNIT 1: 8086 Architecture s igs. It is also known as status register or nw se? 4s 2 SausFog->[ X | x [x Tx Tor [or [ir [FL xX [ar[ x Torx BK haan cond OverflowFiag Es ParkyPleg a Irterupt enable Flog eer ‘Trap Fg Sonreg £onditional Flags (Status Flags) — 1) These flags are set or reset by the processor after execution of an arithmetic or logical instruction. These flags are known as conditional flags or status flags. 2) There are 6 conditional flags. These are OF (over flow flag), SF (sign flag), ZF (zero flag), AF (Auxiliary Carry flag), PF (Parity flag) and CF (Carry flag). Carry Flag (CF) 1) CF will be set if the addition of two 16-bit binary numbers produces a carry out of the MSB position or if there is a borrow to the MSB after subtraction. 2) This flag is also affected on execution of other arithmetic and logical instruction, Parity Flag (PF) This flag is set, if the result of the operation has an even number of I's (in the lower 8 bits of the result). This flag can be used to check for transmission error. 1) This flag is set, when there is a carry out of the lower nibble to the higher nibble or a borrow from the higher nibble to the lower. 2) The auxiliary carry flag is used for decimal adjust operation. 3) The AF flag is of significance only for byte operations during which the lower order byte of the 16-bit word is used. 1) This flag is set when the result of an operation ts 7ero 2) The tlag is reset when the result is not zero Sign Flag (SF) ; , 1) This flag is set, wheu MSB bit of the result is high after an arithmetic operation. B.Sc. PART It (Sem(T 1; 8086 Architecture er! UNIT A: [BB Aavance Microprocessor and Microcontro = Code Segment ‘Explain with example, how 20 bit physical address Is generated In 8086 mp. What is physical address? How is it computed? Explain with example. Tia Explain physical address in 8086 mp. . [wisi] Explain physical and offset address in 8086 mp f logical and physical address in 8086 mp. 4 Physical and Effective Address: 1, G = ‘fy 8086 mp has | MB physical memory (Internal memory of the processor). 2) This 1 MB memory is logically divided into different subdivision known as segme Each segment has capacity of 64 Kbytes. 3) Among these 16 segments, only 4 segments are active at a time. These 4 differen KB segments are for Code, stack, data & extra daia. 4) 8086 has only 16-bit Registers. But 8086 requires 20-bit address lines to address w the memory of | MB [2”’= | MB J. 5) Hence to obtain 20-bit addresses known as physical address, from the available li registers, all 8086 memory addresses are computed by summing the contents segment register and aa effective memory address. 6) 20-bit address is split into two parts. the first part is starting address of the seg) Inown as segment address and another part is offset within the segmeni know feet Address or E : ai Address: 7) The process of addi WBE ss: pantintisem vip RN Publicationcontents are shifted. eft four bits (ie., the imal or 10 Hexadecimal number) lemory address to generate the actual physicai b. And then added to the effective m: address output. | 16-hit Segment 2 ‘Address * 16; +1 dress bit Offset Address - _ ____SA* 10) + OFA = PAD Where PA: Physical Address (20 bit), SA: Segment Address (16 bi) OFA: Offset Address (16-bit) Example: Find the value ef physical Address if starting address of Segment is B3CO and olfsel address is 1234 Sol: Given Segment address SA = B3CO, and offset address OFA = 1234, PA = SA*10+OFA PA = B3CO *10 + 1234 PA = B3CO0 + 1234 PA = B4E34q There for physical address will be B4E34y, Qi3. Calculate the value of each of the physical addresses that follows. ‘Assume all values are in hexadecimal. () 2000:1234 (ii) 4000:2146 (ill) ABCO:018A (iv) 0420:ABCD Sok (@) 2000:1234=? Given Segment Address SA = 2000} 4 Offset Address OFA = 1234y The Physical Address PA=SA*10+ OFA PA= 2000* 10 + 1234 4 PA= 20000 + 1234 | 4 PA= 21234y | Hence physical Address is 21234, i) 4D00:2146 =? Given Segment Address SA = 4D00x i Offset Address OFA = 2146y a The Physical Address PA=SA*10 + OFA PA= 4p00 * 104 2146 PA = 4D000 + 2146 a PA» 4F 146, 1s FF 146n, ~ ii) ABCO; 018A: a “B.Sc. PART IIT (Sem vi) ELECTRONICS