QCC5121 WLCSP

Engineering Sample Data Sheet

80-CF193-1 Rev. AA
December 20, 2017
Qualcomm Technologies International, Ltd.

Device description Applications

■ Quad-core processor architecture ■ Wireless speakers
■ High-performance Bluetooth® Audio SoC ■ Wired/wireless stereo headsets/headphones
■ Flexible flash programmable platform ■ Qualcomm TrueWireless™ stereo earbuds
■ Low power for extended battery life ■ USB to Bluetooth dongle with Qualcomm® aptX™ HD

Features System architecture

®
■ Qualified to Bluetooth v5.0 ■ Serial interfaces: UART, Bit Ext Memory
specification Serializer (I²C/SPI), Bluetooth
Apps
Radio
■ Dual 120 MHz Qualcomm® USB 2.0 Developer
Processor I/O
UART/USB
Kalimba™ audio DSPs ■ Integrated PMU: Dual
Stereo HQ and
■ 32/80 MHz Developer SMPS for system/digital Line In / Dual
Analog Mic In
ADC USB PIO
Processor for applications circuits, Integrated Li-ion
battery charger Stereo Apps
■ Firmware Processor for Headphones Class-D or Firmware I²C/SPI

system ■ 15 PIOs, 5 LED pads with Class-AB Processor

PWM OR
■ Flexible QSPI flash Line Out
Headphones
■ 81-ball 3.9798 x 4.0184 x or LED Driver
programmable platform Line Out with PWM
LED

0.54 mm WLCSP ®
■ Advanced audio algorithms ANC Qualcomm
Kalimba™
■ High-performance 24‑bit DSP XTAL
DigMic
stereo audio interface
SMPS
■ Digital and analog Digital LDOs
microphone interfaces I²S/PCM Audio
Interface Qualcomm®
■ Active Noise Cancellation: Kalimba™
DSP Li-Ion
Feedforward, Feedback, SPDIF
Charger
Battery

Hybrid

Confidential and Proprietary – Qualcomm Technologies International, Ltd.

NO PUBLIC DISCLOSURE PERMITTED: Please report postings of this document on public servers or websites to [email protected].

Restricted Distribution: Not to be distributed to anyone who is not an employee of either Qualcomm Technologies International, Ltd. or its affiliated companies
without the express approval of Qualcomm Configuration Management.

Not to be used, copied, reproduced, or modified in whole or in part, nor its contents revealed in any manner to others without the express written permission of
Qualcomm Technologies International, Ltd.

Qualcomm Kalimba, Qualcomm Kymera, Qualcomm TrueWireless, and Qualcomm aptX are products of Qualcomm Technologies International, Ltd. Other
Qualcomm products referenced herein are products of Qualcomm Technologies International, Ltd.

Qualcomm and Qualcomm TrueWireless are trademarks of Qualcomm Incorporated, registered in the United States and other countries. Kalimba and Kymera are
trademarks of Qualcomm Technologies International, Ltd. aptX is a trademark of Qualcomm Technologies International, Ltd., registered in the United States and
other countries. Other product and brand names may be trademarks or registered trademarks of their respective owners.

This technical data may be subject to U.S. and international export, re-export, or transfer ("export") laws. Diversion contrary to U.S. and international law is strictly
prohibited.

Qualcomm Technologies International, Ltd. (formerly known as Cambridge Silicon Radio Limited) is a company registered in England and Wales with a registered
office at: Churchill House, Cambridge Business Park, Cowley Road, Cambridge, CB4 0WZ, United Kingdom.
Registered Number: 3665875 | VAT number: GB787433096

© 2017 Qualcomm Technologies International, Ltd. All rights reserved.

General description

QCC5121 WLCSP is a system on-chip (SoC) with on-chip Bluetooth, audio and programmable application
processor. It includes high-performance, analog, and digital audio codecs, Class-AB and Class-D headphone
drivers, advanced power management, Li-ion battery charger, light-emitting diode (LED) drivers, and flexible
interfaces including inter-integrated circuit sound (I²S), inter-integrated circuit interface (I²C), universal asynchronous
receiver transmitter (UART), and programmable input/output (PIO).
An application-dedicated Developer Processor and a system Firmware Processor run code from an external quad
serial peripheral interface (QSPI) flash. Both processors have tightly coupled memory (TCM) and an on-chip cache
for performance while executing from external flash memory. The system Firmware Processor provides functions
developed by Qualcomm Technologies International, Ltd. (QTIL). The Developer processor provides flexibility to the
product designer to customize their product.
The Audio subsystem contains two programmable Kalimba cores running Qualcomm® Kymera™ system DSP
architecture framework from read only memory (ROM). A range of audio processing capabilities are provided from
ROM which are configurable in fully flexible audio graphs. In built capabilities in ROM, may be complimented or
replaced by capabilities run from random access memory (RAM), including those provided by QTIL, the product
designer or third parties.
The flexibility provided by the fully programmable applications processor plus the ability to configure and program the
audio processors enables manufacturers to easily differentiate products with new features.
QCC5121 WLCSP is driven by a flexible, software platform with powerful integrated development environment (IDE)
support. This enables rapid time-to-market deployment for a broad range of consumer electronic products, including
headphones, headsets, speakers, and Qualcomm TrueWireless stereo earbuds.
For more information on development tools and audio development kit (ADK)s for the QCC5121 WLCSP, including
information on Bluetooth and other features supported, see createpoint.qti.qualcomm.com.

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Ordering information

Package
Device Order number
Type Size Shipment method

3.9798 x 4.0184 x
WLCSP 81-ball
QCC5121 WLCSP 0.54 mm 0.4 mm Tape and reel QCC5121-0-81WLNSP
(Pb free)
pitch

NOTE Until QCC5121 WLCSP reaches Production status, contact your QTIL regional representative for
information on acquiring engineering samples.
At Production status minimum order quantity is 2 kpcs. For engineering samples minimum order
quantity is 0.5 kpcs.
Your attention is drawn to QTIL’s (“Seller”’s) standard terms of supply which govern the supply of
Prototype Products or Engineering Samples and which state in clause 5:
5.1 “Prototype Products” or “Engineering Samples” means any products that have not passed all the
stages of full production acceptance as determined solely by the Seller. The Seller will usually identify
which of the Goods ordered are considered Prototype Products designating them “ES” on the Quotation
and any Order for Prototype Products shall be subject to the special terms contained in this clause 5.
5.2 The Seller has used reasonable efforts to design and build the Prototype Products in accordance
with the relevant specification, but because the testing carried out by the Seller in respect of the
Prototype Products is incomplete, the Seller does not give or enter into any warranties, conditions, or
other terms in relation to quality or fitness for purpose of the Prototype Products and/or that the
Prototype Products are free from bugs, errors, or omissions.
Supply chain: QTIL's manufacturing policy is to multisource volume products. For further details,
contact your local sales account manager or representative.

QCC5121 WLCSP Development Kit ordering information

QTIL supplies QCC5121 WLCSP development equipment.

Description Model Order number

QCC5121 WLCSP Development Kit DK-5121-WLCSP-CF338-110 65-CF338-110

TRBI200 Transaction Bridge Interface High-
DK-TRBI200-CE684-1 65-CE684-1
Speed Debug Adaptor and Programmer

The QCC5121 WLCSP Development Kit, includes a flexible development board that has a wide range of
interconnects, and QCC5121 WLCSP mounted on a plug-in module.

TRBI200 is a high-speed universal serial bus (USB) to transaction bus interface that supports high-speed debug and
flash programming.

NOTE TRBI200 use is not mandatory for flash programming or other manufacturing operations. Those actions
are performable using direct USB connection to the QCC5121 WLCSP USB device interface.

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QCC5121 WLCSP Data Sheet Ordering information

QTIL contacts
General information www.qualcomm.com
Information on this product [email protected]
Customer support for this product createpoint.qti.qualcomm.com
Details of compliance and standards [email protected]
Help with this document [email protected]

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Device details

Audio subsystem Li-ion battery charger

■ Dual 32‑bit Kalimba audio digital signal processor (DSP) ■ Integrated battery charger supporting internal mode (up to
cores with flexible clocking from 2 MHz to 120 MHz to 200 mA) and external mode (up to 1.8 A)
allow optimization and trade-off performance vs. power ■ Variable float (or termination) voltage adjustable in 50 mV
consumption steps from 3.65 V to 4.4 V
■ DSPs execute code from ROM and from program RAM, ■ Thermal monitoring and management are implementable
original equipment manufacturer (OEM) and third party in application software
developed features can run from program RAM
■ Pre-charge to fast charge transition configurable at 2.5 V,
■ 80 KB program RAM 2.9 V, 3.0 V, and 3.1 V
■ 256 KB data RAM Power management
■ 5 Mb ROM ■ Integrated power management unit (PMU) to minimize
Application subsystem external components
■ Dual-core application subsystem 32/80 MHz operation ■ QCC5121 WLCSP runs directly from a Li-ion, USB, or
external supply (2.8 V to 6.5 V)
■ 32‑bit Firmware Processor:
■ Auto-switching between battery and USB (or other)
□ Reserved for system use charging source
□ Runs Bluetooth upper stack, profiles, house-keeping ■ Power islands employed to optimize power consumption
code for variety of use-cases
■ 32‑bit Developer Processor: ■ Dual switch-mode power supply (SMPS):
□ Runs developer applications □ Automatic mode selection to minimize power
■ Both cores execute code from external flash memory using consumption
QSPI clocked at 32 MHz or 80 MHz □ 1.8 V SMPS generates power for both the device and
■ On-chip caches per core allow for optimized performance off-chip circuits
and power consumption □ Dedicated digital SMPS (output voltage changes
automatically to minimize device power consumption)
Bluetooth subsystem
■ Qualified to Bluetooth v5.0 specification including 2 Mbps
Bluetooth low energy (Production parts)
■ Single ended antenna connection with on-chip balun and
Tx/Rx switch
■ Bluetooth, Bluetooth low energy, and mixed topologies
supported
■ Class 1 support

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QCC5121 WLCSP Data Sheet Device details

Audio engine and digital audio interfaces Peripherals and physical interfaces
■ 24-Bit I²S interface with 1 input and 3 output channels ■ A UART interface
■ Programmable audio master clock (MCLK) ■ 2 x Bit Serializers (programmable serial peripheral
■ Sony/Philips digital interface (SPDIF): 2, configurable as interface (SPI) and I²C hardware accelerator)
input or output ■ 1 x USB interface:
■ Stereo analog outputs configurable as differential Class- □ A full speed USB (USB-FS) Device (12 Mbps)
AB headphone outputs or differential high efficiency Class-
D outputs: –USB interface includes ESD protection to
IEC-6000-4-2 (device level)
□ A signal-to-noise ratio (SNR) differential: 98 dBA ■ QSPI NOR flash interface
□ A total harmonic distortion plus noise (THD+N) □ QSPI encryption to protect developer code and data
differential, 32 Ω load: -85 dB
■ Dual analog inputs configurable as single ended line inputs
□ Encryption programmable with a 128‑bit security key of
or, unbalanced or balanced analog microphone inputs: OEM choice stored in on-chip one-time programmable
(OTP) memory
□ SNR single-ended: 96 dBA ■ Up to 15 PIO and 5 open drain/digital input LED pads with
□ THD+N single-ended: -85 dB pulse width modulation (PWM)
■ 1 microphone bias (single bias shared by the two Package and compliance
channels):
■ 81-ball 3.9798 x 4.0184 x 0.54 mm, 0.4 mm pitch WLCSP
□ Crosstalk attenuation between two inputs using ■ Green (restriction of hazardous substances (RoHS)
recommended application circuit: 65 dB
compliant and no antimony or halogenated flame
■ Digital microphone inputs with capability to interface up to retardants)
6 digital microphones
■ Both analog-to-digital converter (ADC)s and digital-to-
analog converter (DAC)s support sample rates of 8, 16,
32, 44.1, 48, 96 kHz. DACs also support 192 kHz.

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QCC5121 WLCSP functional block diagram

Applications Subsystem

Firmware Processor Developer Processor Cache 0

Qualcomm ®
Stacks and Libraries Developer Code DMA Controller
Cache 1 QSPI Flash Controller Serial Flash
Encryption Accelerator
TCM 0 Data RAM 0 TCM 1 Data RAM 1 Shared RAM

Host Interfaces Subsystem Bluetooth Subsystem

Processor Subsystem Digital Baseband Bluetooth Radio

UART
Transmitter Antenna
General Purpose Interfaces
Firmware Processor Packet Processing Engine Modulator
I²C / SPI
LO

Receiver
Program ROM RAM Digital Modem Radio Interface
USB FS Device FS PHY USB Device ADC Mixer

PMU Subsystem Audio Subsystem

®
Qualcomm Kalimba™ DSP Qualcomm® Kalimba™ DSP
SMPSs and LDOs ® Subsystem Clocking
Qualcomm Kymera™ system DSP Qualcomm® Kymera™ system DSP
architecture, QTIL, and Developer Algorithms architecture, QTIL, and Developer Algorithms

Li-ion Battery (3.7 V) and charge Li-ion Battery Audio Engine

Auxiliary ADC Program ROM
Charger
Line/Mic In
2 x Codec Outputs Analogue Audio
Buffer Line/Headphone Out
Debug Interface Program RAM/Cache Access ANC
PIO Controller Controller Digital Mics
Digital Audio
SPDIF Input/Output
PIOs PIO 6 x Codec Inputs Interfaces
Data RAM I²S/PCM Input/Output

bdu1512740137732.1
Developer/QTIL
Firmware System Manager Boot Manager Reference Oscillator Crystal

I/O MUX
Firmware Processor OTP Memory
LED / PWM LED I/Os

QCC5121 WLCSP functional block diagram

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Revision history

Revision Date Change reason

AA December 2017 Initial release. Alternative document number CS-00405666-DS.

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Status information

QTIL Product Data Sheets progress according to the following formats: Advance Information, Engineering Sample,
Pre-production Information, and Production Information. The status of this document is Engineering Sample.
Advance Information
Information for designers concerning QTIL product in development. All values specified are the target values of the
design. Minimum and maximum values specified are only given as guidance to the final specification limits and must
not be considered as the final values.

Engineering Sample
Information about initial devices. Devices are untested or partially tested prototypes, their status is described in an
Engineering Sample Release Note. All values specified are the target values of the design. Minimum and maximum
values specified are only given as guidance to the final specification limits and must not be considered as the final
values.

All detailed specifications including pinouts and electrical specifications may be changed by QTIL without notice.

Pre-production Information
Pinout and mechanical dimension specifications finalized. All values specified are the target values of the design.
Minimum and maximum values specified are only given as guidance to the final specification limits and must not be
considered as the final values.

All electrical specifications may be changed by QTIL without notice.

Production Information
Final Data Sheet including the guaranteed minimum and maximum limits for the electrical specifications.

Production Data Sheets supersede all previous document versions.

Device implementation
As the feature-set of the QCC5121 WLCSP is firmware build-specific, see the relevant software release note for the
exact implementation of features on the QCC5121 WLCSP.

Life support policy and use in safety-critical applications

QTIL products are not authorized for use in life-support or safety-critical applications. Use in such applications is
done at the sole discretion of the customer. QTIL will not warrant the use of its devices in such applications.

QTIL environmental and RoHS compliance

QCC5121 WLCSP devices meet the requirements of Directive 2011/65/EU of the European Parliament and of the
Council on the Restriction of Hazardous Substance (RoHS).
QCC5121 WLCSP devices are free from halogenated or antimony trioxide-based flame retardants and other
hazardous chemicals. For more information, see QTIL Environmental declaration statement for QTIL semiconductor
products.

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Contents

General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
QCC5121 WLCSP Development Kit ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
QTIL contacts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Device details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
QCC5121 WLCSP functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Status information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Device implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Life support policy and use in safety-critical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
QTIL environmental and RoHS compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.1 QCC5121 WLCSP package dimensions diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.2 QCC5121 WLCSP device terminal functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.2.1 QCC5121 WLCSP device terminal functions (Radio) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.2.2 QCC5121 WLCSP device terminal functions (Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.2.3 QCC5121 WLCSP device terminal functions (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.2.4 QCC5121 WLCSP device terminal functions (QSPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.2.5 QCC5121 WLCSP device terminal functions (PIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.2.6 QCC5121 WLCSP device terminal functions (Audio) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.2.7 QCC5121 WLCSP device terminal functions (AIO/LED drivers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.2.8 QCC5121 WLCSP device terminal functions (SMPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.2.9 QCC5121 WLCSP device terminal functions (Power supplies and control) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.2.10 QCC5121 WLCSP device terminal functions (Ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.2.11 QCC5121 WLCSP device terminal functions (Not connected) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.3 QCC5121 WLCSP PCB design and assembly considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.3.1 Typical solder reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.4 Moisture sensitivity level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2 Bluetooth subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.1 Bluetooth v5.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.2 Bluetooth radio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.2.1 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.2.2 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

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QCC5121 WLCSP Data Sheet Contents

3 Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.1 Crystal specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4 System power states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.1 No Power state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.2 Active state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.3 Shallow Sleep state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.4 Deep Sleep state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.5 Dormant state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.6 Off state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.7 Transition between static power states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.8 Power islands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5 Host Interfaces subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.1 Host Interfaces subsystem features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6 Applications subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.1 Application subsystem features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7 Audio subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.1 Audio subsystem features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.2 Dual core Kalimba . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.3 Program ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.4 Program RAM and caches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.5 Data RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.6 Buffer Access Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.7 Audio engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.7.1 Active Noise Cancellation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.8 Always On Voice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
8 Audio interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8.1 Analog audio interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8.1.1 Line/Mic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8.1.2 Line/Headphone outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8.2 Digital audio interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8.2.1 Digital microphone inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8.2.2 Standard I²S/PCM interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8.2.3 I²S/PCM master mode timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.2.4 I²S/PCM slave mode timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.2.5 SPDIF interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.2.6 Audio MCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8.3 Simultaneous audio routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8.3.1 Codec inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8.3.2 Codec outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

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8.3.3 Audio slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

9 Peripheral interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.1 PIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.2 PIO pad allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.3 Standard I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.4 Pad multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.5 RESET# reset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9.6 SYS_CTRL pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9.7 LED pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
9.8 LED controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
9.9 USB interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
9.10 USB device port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
9.11 USB charger detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
10 Transaction bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
11 Boot Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
11.1 OTP memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
12 System Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
12.1 System timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
13 PMU subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
13.1 Li-ion charger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
13.2 General charger operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
13.2.1 Battery protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
13.2.2 Temperature measurement during charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
13.3 Charging modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
13.4 External charger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
13.4.1 Selection of sense resistor value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
13.4.2 Selection of PNP transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
13.5 Power regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
13.5.1 Switch mode regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
13.5.2 Bypass LDO regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
13.5.3 KA regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
14 QCC5121 WLCSP example application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
15 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
15.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
15.2 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
15.3 Battery input pin specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
15.4 Charger input pin specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
15.5 Battery charger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

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15.6 Regulator enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

15.7 Bypass LDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
15.8 1.8 V SMPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
15.9 Digital SMPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
15.10 10‑bit auxiliary ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
15.11 Digital terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
15.12 LED driver pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
15.13 ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
16 Audio performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
16.1 Digital-to-analog converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
16.2 Analog-to-digital converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
16.3 Microphone bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
17 Bluetooth performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
18 Power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
19 Environmental declaration statement for QTIL semiconductor products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
20 Software development and tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
20.1 Qualcomm® MultiCore Development Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
20.2 Audio Development Kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Document references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

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Tables

Table 1-1: QCC5121 WLCSP device terminal functions (Radio)................................................................................................19

Table 1-2: QCC5121 WLCSP device terminal functions (Clock)................................................................................................ 19
Table 1-3: QCC5121 WLCSP device terminal functions (USB).................................................................................................. 20
Table 1-4: QCC5121 WLCSP device terminal functions (QSPI)................................................................................................. 20
Table 1-5: QCC5121 WLCSP device terminal functions (PIO)................................................................................................... 21
Table 1-6: QCC5121 WLCSP device terminal functions (Audio)............................................................................................... 22
Table 1-7: QCC5121 WLCSP device terminal functions (AIO/LED drivers)............................................................................... 23
Table 1-8: QCC5121 WLCSP device terminal functions (SMPS)................................................................................................24
Table 1-9: QCC5121 WLCSP device terminal functions (Power supplies and control)............................................................. 24
Table 1-10: QCC5121 WLCSP device terminal functions (Ground)...........................................................................................25
Table 1-11: QCC5121 WLCSP device terminal functions (Not connected)............................................................................... 26
Table 8-1: High-quality ADC analog gain vs. input impedance and input amplitude............................................................... 40
Table 8-2: Headset output driver modes................................................................................................................................. 41
Table 8-3: I²S/PCM master mode timing diagram symbols...................................................................................................... 42
Table 8-4: I²S/PCM slave mode timing diagram symbols......................................................................................................... 43
Table 8-5: Audio MCLK clock output frequencies.................................................................................................................... 44
Table 8-6: Codec input use conditions..................................................................................................................................... 45
Table 8-7: Codec output use conditions................................................................................................................................... 45
Table 8-8: QCC5121 WLCSP audio slots................................................................................................................................... 45
Table 9-1: Virtual PIO............................................................................................................................................................... 47
Table 9-2: LED controller pattern............................................................................................................................................. 48
Table 10-1: Transaction bridge PIO multiplex...........................................................................................................................50
Table 13-1: Parameters in Trickle charge..................................................................................................................................54
Table 13-2: Parameters in Pre-charge...................................................................................................................................... 55
Table 13-3: Parameters in Fast charge..................................................................................................................................... 55
Table 13-4: Parameters in Standby mode................................................................................................................................ 56
Table 16-1: Class-D headset output driver or Class-AB line out............................................................................................... 71
Table 16-2: High-quality audio input (HQADC)........................................................................................................................ 72
Table 16-3: Microphone bias....................................................................................................................................................72

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QCC5121 WLCSP Data Sheet Contents

Table 19-1: Restricted substances present in QTIL products....................................................................................................75

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Figures

QCC5121 WLCSP functional block diagram................................................................................................................................7

Figure 1-1: QCC5121 WLCSP package dimensions diagram..................................................................................................... 18
Figure 2-1: Bluetooth subsystem............................................................................................................................................. 27
Figure 3-1: Crystal oscillator..................................................................................................................................................... 29
Figure 4-1: QCC5121 WLCSP static power states diagram....................................................................................................... 31
Figure 5-1: Host Interfaces subsystem..................................................................................................................................... 33
Figure 6-1: Applications subsystem..........................................................................................................................................34
Figure 7-1: QCC5121 WLCSP Audio subsystem........................................................................................................................ 36
Figure 7-2: Always On Voice state diagram.............................................................................................................................. 38
Figure 8-1: QCC5121 WLCSP high-quality ADC input switch configuration..............................................................................39
Figure 8-2: I²S/PCM master mode timing diagram.................................................................................................................. 42
Figure 8-3: I²S/PCM slave mode timing diagram......................................................................................................................43
Figure 11-1: Boot Manager...................................................................................................................................................... 51
Figure 12-1: System Manager.................................................................................................................................................. 52
Figure 13-1: PMU subsystem................................................................................................................................................... 53
Figure 13-2: Charge cycle states............................................................................................................................................... 54
Figure 13-3: Power regulation..................................................................................................................................................58
Figure 14-1: QCC5121 WLCSP example application schematic................................................................................................ 60

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1 Package information

QCC5121 WLCSP is available in a 3.9798 x 4.0184 x 0.54 mm 81-ball WLCSP package.

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QCC5121 WLCSP Data Sheet Package information

1.1 QCC5121 WLCSP package dimensions diagram

The dimensions of the QCC5121 WLCSP package from top, bottom and side view are shown in Figure 1-1.

Figure 1-1 QCC5121 WLCSP package dimensions diagram

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1.2 QCC5121 WLCSP device terminal functions

The balls on the QCC5121 WLCSP are grouped into various terminal functions. The device terminal functions
include:
■ Radio
■ Clock
■ USB
■ QSPI
■ PIO
■ Audio
■ AIO/LED drivers
■ SMPS
■ Power supplies and control
■ Ground

1.2.1 QCC5121 WLCSP device terminal functions (Radio)

Table 1-1 QCC5121 WLCSP device terminal functions (Radio)

Radio Ball Pad type Supply domain Description

BT_RF 46 RF VDD_BT_RADIO Bluetooth transmit/receive.

1.2.2 QCC5121 WLCSP device terminal functions (Clock)

Table 1-2 QCC5121 WLCSP device terminal functions (Clock)

Clock Ball Pad type Supply domain Description

XTAL_IN 75 Analog Internal 1.2 V from XTAL clock input.

VDD_XTAL_1V8
XTAL_OUT 74 Analog Internal 1.2 V from XTAL clock output.
VDD_XTAL_1V8

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1.2.3 QCC5121 WLCSP device terminal functions (USB)

NOTE USB_DN and USB_DP are usable as PIOs with the restriction that they are both inputs or both outputs.

Table 1-3 QCC5121 WLCSP device terminal functions (USB)

USB Ball Pad type Supply domain Description

USB_DN 3 Digital VDD_BYP USB Full Speed device D- I/O.

IEC-61000-4-2 (device level) ESD
Protection
USB_DP 13 Digital VDD_BYP USB Full Speed device D+ I/O.
IEC-61000-4-2 (device level) ESD
Protection

1.2.4 QCC5121 WLCSP device terminal functions (QSPI)

Table 1-4 QCC5121 WLCSP device terminal functions (QSPI)

Reset
QSPI Ball Pad type Supply domain Description
state

QSPI1_IO[3] 19 Digital: Bidirectional VDD_PADS_2 Strong QSPI 1, input/output 3.

with programmable pull-up
strength internal pull-
up/pull-down
QSPI1_IO[2] 30 Digital: Bidirectional VDD_PADS_2 Strong QSPI 1, input/output 2.
with programmable pull-up
strength internal pull-
up/pull-down
QSPI1_IO[1] 39 Digital: Bidirectional VDD_PADS_2 Weak QSPI 1, input/output 1.
with programmable pull-down
strength internal pull-
up/pull-down
QSPI1_IO[0] 11 Digital: Bidirectional VDD_PADS_2 Weak QSPI 1, input/output 0.
with programmable pull-down
strength internal pull-
up/pull-down
QSPI1_CLK 10 Digital: Bidirectional VDD_PADS_2 Strong QSPI 1, clock output.
with programmable pull-down
strength internal pull-
up/pull-down
QSPI1_CS0# 29 Digital: Bidirectional VDD_PADS_2 Strong QSPI 1, chip select 0,
with programmable pull-up active low.
strength internal pull-
up/pull-down

1.2.5 QCC5121 WLCSP device terminal functions (PIO)

NOTE PIO alternative functions include SPI/I²C, UART, SPDIF, digital microphone. Any PIO function can be
multiplexed to any PIO. Alternative functions in Table 1-5 are available only on the specific PIO port.

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Table 1-5 QCC5121 WLCSP device terminal functions (PIO)

Reset
PIO port Ball Pad type Supply domain Description
state

PIO[21] 12 Digital: Bidirectional VDD_PADS_3 Weak Programmable I/O line

with programmable pull-down 21.
strength internal pull-
Alternative function:
up/pull-down
■ PCM_DOUT[2]
PIO[20] 31 Digital: Bidirectional VDD_PADS_3 Weak Programmable I/O line
with programmable pull-down 20.
strength internal pull-
Alternative function:
up/pull-down
■ PCM_DOUT[1]
PIO[19] 1 Digital: Bidirectional VDD_PADS_3 Weak Programmable I/O line
with programmable pull-down 19.
strength internal pull-
Alternative function:
up/pull-down
■ PCM_DIN[0]
PIO[18] 21 Digital: Bidirectional VDD_PADS_3 Weak Programmable I/O line
with programmable pull-down 18.
strength internal pull-
Alternative function:
up/pull-down
■ PCM_DOUT[0]
PIO[17] 40 Digital: Bidirectional VDD_PADS_3 Weak Programmable I/O line
with programmable pull-down 17.
strength internal pull-
Alternative function:
up/pull-down
■ PCM_SYNC
PIO[16] 49 Digital: Bidirectional VDD_PADS_3 Weak Programmable I/O line
with programmable pull-down 16.
strength internal pull-
Alternative function:
up/pull-down
■ PCM_CLK
PIO[15] 41 Digital: Bidirectional VDD_PADS_3 Weak Programmable I/O line
with programmable pull-down 15.
strength internal pull-
Alternative function:
up/pull-down
■ MCLK_OUT
PIO[8] 54 Digital: Bidirectional VDD_PADS_1 Weak Programmable I/O line
with programmable pull-down 8.
strength internal pull-
Alternative function:
up/pull-down
■ TBR_CLK
PIO[7] 52 Digital: Bidirectional VDD_PADS_1 Strong Programmable I/O line
with programmable pull-upa 7.
strength internal pull-
Alternative function:
up/pull-down
■ TBR_MISO[0]
PIO[6] 51 Digital: Bidirectional VDD_PADS_1 Strong Programmable I/O line
with programmable pull-up 6.
strength internal pull-
Alternative function:
up/pull-down
■ TBR_MOSI[0]
PIO[5] 53 Digital: Bidirectional VDD_PADS_1 Weak Programmable I/O line
with programmable pull-down 5.
strength internal pull-
Alternative function:
up/pull-down
■ TBR_MISO[1]

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Table 1-5 QCC5121 WLCSP device terminal functions (PIO) (cont.)

Reset
PIO port Ball Pad type Supply domain Description
state

PIO[4] 50 Digital: Bidirectional VDD_PADS_1 Weak Programmable I/O line

with programmable pull-down 4.
strength internal pull-
Alternative function:
up/pull-down
■ TBR_MOSI[1]
PIO[3] 44 Digital: Bidirectional VDD_PADS_1 Weak Programmable I/O line
with programmable pull-down 3.
strength internal pull-
Alternative function:
up/pull-down
■ TBR_MISO[2]
PIO[2] 48 Digital: Bidirectional VDD_PADS_1 Weak Programmable I/O line
with programmable pull-down 2.
strength internal pull-
Alternative function:
up/pull-down
■ TBR_MISO[3]
PIO[1] 56 Digital: Bidirectional VDD_PADS_1 Strong Automatically defaults
with programmable pull-upb to RESET# mode
strength internal pull- when the device is
up/pull-down unpowered, or in off
modes.
Reconfigurable as a
PIO after boot.
Alternative function:
■ Programmable I/O
line 1
a PIO[7] must not be held low at boot.
b PIO[1] can be reconfigured as a PIO after boot.

1.2.6 QCC5121 WLCSP device terminal functions (Audio)

Table 1-6 QCC5121 WLCSP device terminal functions (Audio)

Audio Ball Pad type Supply domain Description

AUDIO_HPR_N/ 72 Analog VDD_AUDIO_HP_ Headphone/speaker differential

SPKR_N SPKR right output, negative.
Alternative function:
■ Differential right line output,
negative
AUDIO_HPR_P/ 62 Analog VDD_AUDIO_HP_ Headphone/speaker differential
SPKR_P SPKR right output, positive.
Alternative function:
■ Differential right line output,
positive
AUDIO_HPL_N/ 81 Analog VDD_AUDIO_HP_ Headphone/speaker differential left
SPKL_N SPKL output, negative.
Alternative function:
■ Differential left line output,
negative

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Table 1-6 QCC5121 WLCSP device terminal functions (Audio) (cont.)

Audio Ball Pad type Supply domain Description

AUDIO_HPL_P/ 71 Analog VDD_AUDIO_HP_ Headphone/speaker differential left

SPKL_P SPKL output, positive.
Alternative function:
■ Differential left line output,
positive
AUDIO_DACREF 58 Analog VDD_AUDIO_1V8 Low noise DAC reference
decoupling I/O.
AUDIO_MIC_BIAS 70 Analog VDD_AUDIO_1V8 Mic bias output.
AUDIO_BGBYP 69 Analog VDD_AUDIO_1V8 Audio bandgap decoupling I/O.
AUDIO_MIC1_N/ 79 Analog VDD_AUDIO_1V8 Microphone differential 1 input,
LINEIN_L_N negative.
Alternative function:
■ Differential audio line input left,
negative
AUDIO_MIC1_P/ 78 Analog VDD_AUDIO_1V8 Microphone differential 1 input,
LINEIN_L_P positive.
Alternative function:
■ Differential audio line input left,
positive
AUDIO_MIC2_N/ 77 Analog VDD_AUDIO_1V8 Microphone differential 2 input,
LINEIN_R_N negative.
Alternative function:
■ Differential audio line input right,
negative
AUDIO_MIC2_P/ 76 Analog VDD_AUDIO_1V8 Microphone differential 2 input,
LINEIN_R_P positive.
Alternative function:
■ Differential audio line input right,
positive

1.2.7 QCC5121 WLCSP device terminal functions (AIO/LED drivers)

NOTE There is an internal 10 µA current source that can be connected to a thermistor typically for battery
temperature monitoring. Any LED/IO can be multiplexed to this current source.

Table 1-7 QCC5121 WLCSP device terminal functions (AIO/LED drivers)

AIO/LED drivers Ball Pad type Supply domain Description

AIO[5]/LED[5] 43 Analog or digital input/ VDD_BYP General-purpose analog/digital

open drain output. input or open drain LED output.
AIO[4]/LED[4] 34 Analog or digital input/ VDD_BYP General-purpose analog/digital
open drain output. input or open drain LED output.
AIO[2]/LED[2] 25 Analog or digital input/ VDD_BYP General-purpose analog/digital
open drain output. input or open drain LED output.

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Table 1-7 QCC5121 WLCSP device terminal functions (AIO/LED drivers) (cont.)

AIO/LED drivers Ball Pad type Supply domain Description

AIO[1]/LED[1] 42 Analog or digital input/ VDD_BYP General-purpose analog/digital

open drain output. input or open drain LED output.
AIO[0]/LED[0] 33 Analog or digital input/ VDD_BYP General-purpose analog/digital
open drain output. input or open drain LED output.

1.2.8 QCC5121 WLCSP device terminal functions (SMPS)

Table 1-8 QCC5121 WLCSP device terminal functions (SMPS)

SMPSs Ball Pad type Supply domain Description

LX_1V8 18 Analog SMPS_DCPL Inductor connection for 1.8 V

SMPS.
LX_DIG 17 Analog SMPS_DCPL Inductor connection for digital 1.1 V
SMPS.

1.2.9 QCC5121 WLCSP device terminal functions (Power supplies and control)
Table 1-9 QCC5121 WLCSP device terminal functions (Power supplies and control)

Power supplies and control Ball Pad type Supply domain Description

VDD_AUX 66 Supply - 1.8 V supply for AUX.

VDD_XTAL_1V8 57 Supply - 1.8 V supply for XTAL driver.
VDD_BT_RADIO 37 Supply - Internally regulated supply for
Bluetooth radio.
VDD_BT_1V8 38 Supply - 1.8 V supply for Bluetooth radio.
VDD_AUDIO_HP_SPKR 61 Supply - 1.8 V supply for HPR/SPKR output.
VDD_AUDIO_HP_SPKL 60 Supply - 1.8 V supply for HPL/SPKL output.
VDD_AUDIO_1V8 68 Supply - 1.8 V supply for analog audio.
VDD_DIG 4 Supply - 1.1 V supply output from digital
regulator
VDD_PMU_VINDIG 5 Supply - 1.8 V supply input into digital
regulator
VDD_VKA 22 Supply - Low voltage supply output from
keep-alive/dormant regulator.
SYS_CTRL 32 Digital VBAT Typically connected to an ON/OFF
input push button. Boots device in
response to a button press when
power is still present from battery
and/or charger but software has
placed the device in the OFF or
DORMANT state. Additionally
useable as a digital input in normal
operation. No pull.
Additional function:
■ PIO[0] input only

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Table 1-9 QCC5121 WLCSP device terminal functions (Power supplies and control) (cont.)

Power supplies and control Ball Pad type Supply domain Description

VCHG_SENSE 6 Analog VCHG Charger input sense pin after

external mode sense-resistor. High
impedance.
CHG_EXT 23 Analog VCHG External charger transistor current
control. Connect to base of external
charger transistor as per application
schematic.
VBAT_SENSE 24 Analog VBAT Battery voltage sense input.
VBAT 7 Supply VBAT Battery voltage input.
VDD_BYP_CHG 15 Supply VCHG Charger input to Bypass regulator.
VDD_BYP 16 Supply VCHG Bypass regulator decoupling.
SMPS_DCPL 8 Analog - Analog power pad. Either battery or
charger inputs are switched into this
decoupling pad.
SMPS_VBAT 9 Supply VBAT Supply to SMPS power switch from
battery.
SMPS_VCHG 27 Supply VCHG Supply to SMPS power switch from
charger input.
VDD_PADS_1 45 Supply - 1.8 V/3.3 V PIO supply.
VDD_PADS_2 20 Supply - 1.8 V/3.3 V PIO supply.
VDD_PADS_3 2 Supply - 1.8 V/3.3 V PIO supply.

1.2.10 QCC5121 WLCSP device terminal functions (Ground)

Table 1-10 QCC5121 WLCSP device terminal functions (Ground)

Ground Ball Description

VSS_AUX 73 Ground connection for AUX circuits.

VSS_BT_LO 64 Ground connection for Bluetooth local oscillator.
VSS_BT_RADIO 55 Ground connection for Bluetooth RF circuits.
VSS_BT_RF_GND 47 Ground connection for Bluetooth RF circuits and Bluetooth
PA.
VSS_DIG_PADS 28, 36 Ground for digital I/Os.
VSS_PMU 14 Clean ground connection for PMU circuits.
VSS_SMPS_DIG 35 Ground pad for Digital SMPS.
VSS_SMPS_1V8 26 Ground pad for analog SMPS.
VSS_AUDIO_HP_SPKR 63 Ground VSS for HPR/SPKR.
VSS_AUDIO_HP_SPKL 59 Ground VSS for HPL/SPKL.
VSS_AUDIO 80 Ground for audio circuits.
VSS_AUDIO_REF 67 Ground for audio reference.

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1.2.11 QCC5121 WLCSP device terminal functions (Not connected)

Table 1-11 QCC5121 WLCSP device terminal functions (Not connected)

Not connected Ball Description

NC 65 Ground on PCB.

1.3 QCC5121 WLCSP PCB design and assembly considerations

Recommendations to achieve maximum board-level reliability of the QCC5121 WLCSP integrated circuit (IC)
package.
■ Use of nonsolder mask defined (NSMD) lands (lands smaller than the solder mask aperture) are preferred
because of the greater accuracy of the metal definition process compared to the solder mask process. With
solder mask defined pads, the overlap of the solder mask on the land creates a step in the solder at the land
interface, which can cause stress concentration and act as a point for crack initiation.
■ Ideally, use via-in-pad technology to achieve truly NSMD lands. Where this is not possible, a maximum of one
trace connected to each land is preferred and this trace should be as thin as possible. Take into consideration its
current carrying and the radio frequency (RF) requirements.
■ 35 µm thick (1 oz) copper lands are recommended rather than 17 µm thick (0.5 oz). This results in a greater
standoff which has been proven to provide greater reliability during thermal cycling.
■ Land diameter should be the same as that on the package (0.25 mm) to achieve optimum reliability.
■ Solder paste is preferred to flux during the assembly process because this adds to the final volume of solder in
the joint, increasing its reliability.
■ When using a nickel gold plating finish, keep the gold thickness below 0.5 µm to prevent brittle gold/tin
intermetallics forming in the solder.
■ For increased board-level reliability, you could consider the use of underfill.

1.3.1 Typical solder reflow profile

For further information describing the reflow profile of an IC when attaching its physical connection solder points to a
printed circuit board (PCB) see Typical Solder Reflow Profile for Lead-free Devices Information Note.

1.4 Moisture sensitivity level

QCC5121 WLCSP is qualified to moisture sensitivity in accordance with JEDEC J-STD-020.

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2 Bluetooth subsystem

Bluetooth Subsystem

Processor Subsystem Digital Baseband Bluetooth Radio

Transmitter Antenna

Firmware Processor Packet Processing Engine Modulator

elm1478616986807.6
LO

Receiver
Program ROM RAM Digital Modem Radio Interface
ADC Mixer

Figure 2-1 Bluetooth subsystem

The Bluetooth subsystem, see Figure 2-1, is a dual-mode radio supporting concurrent classic and Bluetooth low
energy operation. It is fully qualified to the Bluetooth v5.0 specification. It has:
■ 32 MHz processor running Bluetooth firmware
■ Bluetooth packet processing engine and modem
■ A single power domain under control of the System Manager subsystem
■ Power and clocks automatically removed to reduce power when the Bluetooth radio is not operating

NOTE For Bluetooth feature details, refer to ADK documentation.

2.1 Bluetooth v5.0

QCC5121 WLCSP supports Bluetooth v5.0 including Bluetooth low energy 2 Mbps.

2.2 Bluetooth radio

The Bluetooth radio consists of a single RF I/O port shared for receive and transmit. The RF port impedance is 50 Ω
when operating.

2.2.1 Receiver
The receiver consists of an LNA that boosts the incoming RF signal. The passive mixer down-converts the wanted
signal and splits the wanted output between I and Q quadrature-related channels. Passive low pass filtering at the
output of the mixer attenuates out of band signals while allowing the wanted signal to pass through. This helps to
avoid saturating the ADC input.

LNA, Mixer, and ADC gains are automatically controlled by the AGC and are based on saturation detection and
wideband RSSI detection indications from the RF front end.

The receive ADC is a continuous time second order sigma-delta architecture.

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QCC5121 WLCSP Data Sheet Bluetooth subsystem

2.2.2 Transmitter
The transmitter is implemented using a polar transmit architecture. There are separate paths for phase and
amplitude modulated data. The phase modulation (PM) path is used for basic rate modulation. The phase
modulation and amplitude modulation is used for enhanced data rate modulation (EDR2 and EDR3).

The advantage of using a polar transmit architecture is that a nonlinear PA is usable. The PA is a Class-D design and
therefore provides high-power efficiency compared to previous generation devices.

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3 Crystal oscillator

Reference Oscillator Crystal

uun1478616994779.4
Figure 3-1 Crystal oscillator
The Bluetooth specification requires frequency accuracy of ±20 ppm. The output RF frequency is directly linked to
the frequency accuracy of the crystal oscillator, so this must be ±20 ppm. This specification must be fulfilled over the
operating temperature range of the device.
The crystal is specified by the following terms:
■ Initial Frequency Error: The difference between the required frequency and the actual oscillating frequency
caused by the crystal itself and its PCB connections. It is also called Calibration Tolerance or Frequency
Tolerance
■ Frequency Stability Error: The total of how far the crystal can move off frequency with temperature, aging, or
other effects. It is also called Temperature Stability, Frequency Stability, or Aging.
■ Pullability: The change in frequency for a change in load capacitance.
QCC5121 WLCSP contains an array of capacitors attachable to the XTAL_IN node, and switched to pull the crystal
onto frequency and, therefore compensate for Initial Frequency errors by a simple per-device trim on the production
line with the trim stored in the Application subsystem QSPI flash. However, it is not possible to compensate for
frequency stability errors, therefore a crystal must be chosen with a Frequency Stability error that is better than the
Bluetooth specification ±20 ppm clock accuracy.
Some crystal datasheets combine both these terms into one tolerance value. This causes a problem because only
the initial frequency error can be compensated for and the trim cannot compensate for temperature or aging
performance. If frequency stability is not explicitly stated, QTIL cannot guarantee remaining within the Bluetooth's
±20 ppm frequency accuracy specification.
The fine load capacitance trim steps are small (0.025 pF), so with typical values of crystal pullability the Initial
Frequency tolerance can be effectively eliminated down to the accuracy of the measurement equipment used.
The sum of Initial Frequency Error and Frequency Stability Error must be kept below the Bluetooth specification of
±20 ppm. Typically a crystal with ±15 ppm Frequency Stability over temperature/aging can be used.
To improve startup time and achieve minimum current consumption, crystals with low capacitive loading requirement
are preferred, but this may come at the expense of greater susceptibility to frequency variation caused by the
environment.

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QCC5121 WLCSP Data Sheet Crystal oscillator

3.1 Crystal specification

Parameter Min Typ Max Units

Frequency - 32 - MHz
Frequency stability (after trimming) - ±15 ±20 ppm
Crystal Load Capacitance (lower preferred) - 6 10 pF
Crystal Shunt Capacitance (lower preferred) - 1 2 pF
Crystal ESR, 32 MHz (lower preferred) - 25 50 Ω
Device coarse load capacitance range 1 - 13.8 pF
Device coarse load capacitance step - 0.4 - pF
Device fine load capacitance range -0.5 - 0.5 pF
Device fine load capacitance step - 0.025 - pF
Input signal (direct connection) 0.4 - 1.2 V pk-pk

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4 System power states

Figure 4-1 shows the static IC power states for QCC5121 WLCSP and the functions that are available in each state.
In a system-wide low-power state, software moves between these static power states to reduce total system power.

If no subsystem Software controls

requires a clock the the state change
System Manager configures from Active to
the hardware wakeup Dormant and
sources and configures hardware
Subsystems transitions the wakeup sources
Power autonomously state to Deep Sleep
attach
No power
change state Shallow Deep
changes Active between Dormant Off
state Active and Sleep Sleep
to Active Shallow
Sleep Software controls
the state change

hed1480340640888.2
from Active to Off .
Rising edge on
SYS_CNTRL or
VCHG changes state
from Off to Active

Figure 4-1 QCC5121 WLCSP static power states diagram

4.1 No Power state

When the IC has no power at all, it is in the No Power state. When power is present, for example on battery attach,
the IC automatically boots and moves to Active state.

4.2 Active state

In Active state, the on-chip clocks and power supplies are running, and all functions of the IC are available.

4.3 Shallow Sleep state

Shallow Sleep state is functionally the same as the Active state. However, individual subsystems can autonomously
enter Shallow Sleep state to conserve power. In Shallow Sleep state, a subsystem can turn off or reduce the
frequency of clocks and/or power down memories.

4.4 Deep Sleep state

In Deep Sleep state, the main digital power rail (VDD_DIG_CORE) is in state retention. To reduce leakage the digital
voltage is typically reduced to 0.85 V. The main digital clocks are stopped and a limited number of device features
remain active, including:
■ Boot Manager
■ LED PWM drivers
■ PIO controller
QCC5121 WLCSP extensively uses digital power islands. Deep Sleep state current varies significantly depending on
which functions are active or in state retention.

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QCC5121 WLCSP Data Sheet System power states

The following events can move QCC5121 WLCSP to Active state (selectable via software) from Deep Sleep state:
■ A rising edge on SYS_CTRL
■ A rising edge on VCHG
■ Activity on any PIO
■ Activity on any digital interface
■ A timer
■ Digital activity on any LED pads (when configured as a digital input)
■ Activity on the debug interfaces
■ USB device resume

4.5 Dormant state

In Dormant state, the PMU is enabled in an ultralow power mode. The main digital supply (VDD_DIG_CORE) is off.
This configuration reduces power consumption but limits available device features.

In Dormant state, the following inputs can transition the IC to the Active state (selectable via software):
■ A rising edge on SYS_CTRL
■ A rising edge on VCHG
■ Activity on any PIO[8:1]
■ A timer

NOTE Time accuracy in Dormant state is limited to ±20 %

■ Digital activity on any LED pad (when configured as digital inputs)

4.6 Off state

The Off state is different to No Power state because the IC has power attached from VBAT. In this state the following
events boot the chip and transition it to Active state:
■ A rising edge on SYS_CTRL held high for 20 ms
■ A rising edge on VCHG held high for 20 ms

NOTE The device cannot power off with VCHG attached. Dormant state is the lowest possible power state
when voltage is present on the VCHG input.

4.7 Transition between static power states

Transition into Shallow Sleep and Deep Sleep states is automatic, with the system constantly entering the lowest
power mode. Transition into the Dormant and Off states is under the control of the application software.

4.8 Power islands

To reduce digital leakage the Bluetooth, Audio, and Applications subsystems are contained within separate power
islands. When these subsystems are enabled, the power is applied automatically.

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5 Host Interfaces subsystem

In QCC5121 WLCSP all host interfaces are located together in their own subsystem called the Host Interfaces
subsystem, see Figure 5-1.

Host Interfaces Subsystem

UART

General Purpose Interfaces

I²C / SPI

bug1480340639469.6
USB FS Device FS PHY USB Device

Figure 5-1 Host Interfaces subsystem

Host interfaces within the Host Interfaces subsystem are shared by other QCC5121 WLCSP subsystems, for
example Applications subsystem, Bluetooth subsystem, and Audio subsystem. Host interface sharing ensures that
subsystems have access to the required interfaces as if they had their own dedicated host interface, and makes
efficient use of a single host interface. These host interfaces can operate concurrently. The System Manager
allocates host interface resources to individual subsystems as required.
Each subsystem serviced by the Host Interface Subsystem has its own memory management unit (MMU), which is
accessed directly by the Host Interface Subsystem via the transaction bus. Interrupts are routed to the correct
subsystem.

5.1 Host Interfaces subsystem features

QCC5121 WLCSP supports the following Host Interfaces:
■ USB Device
□ Full Speed (12 Mbps)
□ Multiple IN and OUT endpoints, allocable individually
□ Charging support

■ UART
□ Supports H4 and BCSP HCI interfaces or raw UART to application

■ 2 x Bit Serializers that are configurable independently as

□ I²C Master
□ SPI Master

These host interfaces can operate concurrently, subject to pin multiplexing constraints, between the UART, SPI, and
I²C.
Host Interface signals for UART, SPI and I²C go via a PIO mux with a further multiplexing implemented at the top
level to the PIOs. The Host Interface subsystem must be selected as the controlling subsystem for the relevant PIOs.

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6 Applications subsystem

The Applications subsystem, see Figure 6-1, is a processor-based subsystem that provides on-chip Bluetooth high-
level protocol stack functionality and customer programmability.
It has two 32‑bit processors, one for Qualcomm Technologies International, Ltd. (QTIL) firmware, and another for
customer execution that features memory protection logic.
The primary nonvolatile program storage is off-chip flash memory interfaced using high-speed QSPI interface. This is
cached to provide program code and data for both processors, and file system data and any other data required for
chip configuration.
Support is software-dependent, refer to ADK release notes.

Serial Flash

Applications Subsystem

Firmware Processor Developer Processor Cache 0

®
Developer Code DMA Controller
Qualcomm Stacks and Libraries

nlo1480340640108.1
Cache 1 QSPI Flash Controller
Encryption Accelerator
TCM 0 Data RAM 0 TCM 1 Data RAM 1 Shared RAM

Figure 6-1 Applications subsystem

The Applications subsystem controls several peripheral interfaces:
■ Some other chip resources are programmable. For example, PIO controllers.
■ Interfaces such as USB Device, UART, I²C, SPI.

6.1 Application subsystem features

Application subsystem features include:
■ 2 x 32/80 MHz central processing unit (CPU) cores using Kalimba DSP architecture
□ 32‑bit reduced instruction set computer (RISC) core with DSP features, integrated for optimal control code
execution
□ Sleep mode, interrupt controller, timers, zero overhead looping
□ Private data RAM, 32 KB on Developer processor
□ 2-way cache 16 KB on Developer processor
□ 8 KB of tightly coupled memory on Developer processor
□ Debug features such as hardware breakpoints, single step, PC trace, code instrumentation message
support
■ 32 KB shared buffer RAM
■ A direct memory access (DMA) controller core with acceleration for data encryption and comparison, access to
QSPI flash and remote subsystems

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QCC5121 WLCSP Data Sheet Applications subsystem

■ Demand-paged buffer management hardware providing efficient use of shared memory by local and remote
masters
■ QSPI data path unit with support for flash at 32 MHz single data rate (SDR), inline decryption, smart multimaster
arbitration
■ Multiple remote subsystem interfaces for messaging, control, and data transfer between the various radio and
audio subsystems
The Applications subsystem is powered and brought out of reset by the System Manager and starts up automatically
when clocked.
The subsystem has a single power-island. Each RAM instance is controlled independently to optimize power.

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7 Audio subsystem

Figure 7-1 shows the QCC5121 WLCSP Audio subsystem.

Audio Subsystem
®
Qualcomm Kalimba™ DSP Qualcomm® Kalimba™ DSP
Subsystem Clocking
Qualcomm® Kymera™ system DSP Qualcomm® Kymera™ system DSP
architecture, QTIL, and Developer Algorithms architecture, QTIL, and Developer Algorithms

Program ROM Audio Engine

hzi1512740173939.1
Line/Mic In
2 x Codec Outputs Analogue Audio
Buffer Line/Headphone Out
Program RAM/Cache Access ANC
Controller Digital Mics
Digital Audio
SPDIF Input/Output
6 x Codec Inputs Interfaces
Data RAM I²S/PCM Input/Output

Figure 7-1 QCC5121 WLCSP Audio subsystem

7.1 Audio subsystem features

Audio subsystem features include:
■ CPU clock options:
□ 120/80/32 MHz for audio processing
□ 32/16/8/4/2 MHz for Always On Voice processing
■ Program ROM: 5 Mb
■ Program RAM/cache: 80 KB
■ Data RAM size: 256 KB
■ Analog DAC: Stereo analog outputs configurable as differential Class-AB headphone outputs or differential high
efficiency Class-D
■ Analog ADC: Stereo analog inputs configurable as single ended line inputs, or unbalanced, or balanced analog
microphone inputs
■ I²S/PCM interface
□ One interface, 24‑bit
□ Supports 8, 16, 32, 44.1, 48, 96, 192 kHz sample rates

■ SPDIF interfaces
□ 2, configurable as input or output
□ Supports 8, 16, 32, 44.1, 48, 96, 192 kHz sample rates
■ Audio MCLK: Programmable, available on PIO[15]
■ Audio engine
□ 2 Codec output channels, supporting 8, 16, 32, 44.1, 48, 96, 192 kHz sample rates
□ 6 Codec input channels supporting 8, 16, 32, 44.1, 48, 96 kHz sample rates

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QCC5121 WLCSP Data Sheet Audio subsystem

■ Digital mics
□ 6 mono/3 stereo
□ Supports 500 kHz, 1, 2, 4 MHz clock frequencies
■ Active Noise Cancellation: Hybrid, Feedforward, and Feedback modes
■ Always On Voice mode: Supports voice trigger phrase and voice command interpretation

7.2 Dual core Kalimba

The audio subsystem has identical 2 x 32‑bit, clocked up to 120 MHz dual Kalimba cores. Each core has its own set
of timers, interrupt controllers, and caches. Caches are implemented in program RAM. Both Kalimba cores have
identical memory maps that enable them to see all RAMs, NVM interfaces, and buffers in remote subsystems and
shared peripherals, such as codec and buffer access controller.
Kymera framework runs on the audio core to communicate with the rest of the device.

7.3 Program ROM

The Audio subsystem has a 5 Mb ROM.

7.4 Program RAM and caches

The Audio subsystem has 80 KB of program RAM implemented as 10 banks of 8 KB each. Caches are implemented
in Program RAM.
Access for each bank is arbitrated individually. By default, each CPU has full access to entire RAM, but access
permissions can be set up at a bank level.
Each CPU supports:
■ Direct mapped mode
■ 2-way set-associative mode (full and half capacity)

7.5 Data RAM

The Audio subsystem has 256 KB of DM RAM divided into eight banks of 32 KB each. All RAM banks are equally
accessible by the CPUs.
Data RAM is directly accessible to the audio engine for audio streaming and for remote access.

7.6 Buffer Access Controller

The BAC enables remote subsystems to access audio buffers and data RAM. The BAC implements operations to
manipulate audio buffer data to save DSP MIPs. Audio engine streams data in and out of buffer RAM through the
BAC.

7.7 Audio engine

The Audio subsystem implements 6 inputs and 2 outputs codec channels to service the digital and analog audio
interfaces. The subsystem also implements Active Noise Cancellation hardware.

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QCC5121 WLCSP Data Sheet Audio subsystem

7.7.1 Active Noise Cancellation

The following Active Noise Cancellation (ANC) modes are supported using Digital Mics or Analog Mics:
■ Hybrid ANC
■ Feedforward ANC
■ Feedback ANC

7.8 Always On Voice

Always On Voice (AOV) allows the device to respond to a spoken trigger word. The trigger word can be detected
during low power or active modes such as music streaming or ANC. The device contains two capabilities within the
Audio subsystem ROM, and an Always On Voice framework manages the state machine, see Figure 7-2.
■ Voice Activity Detector (VAD): Is a low resource capability that consumes less than 2 MHz of DSP resource, and
detects acoustic energy. This can run continuously or in a duty cycle mode, where the VAD runs for a period
(typically 25 ms). The device then drops into Deep Sleep mode for the remainder of a 100 ms period. The device
supports a DSP clock frequency of 2 MHz to minimize power consumption when only the VAD is running.
■ Trigger Word Detector (TWD): Is a capability that consumes less than 32 MHz, and detects whether the specified
keyword has been spoken. TWD does not operate until VAD has a positive result. When TWD gets a positive
result, a voice command transaction can start with an audio gateway.
An OEM has the option of using an alternative TWD and/or VAD as a downloaded capability.
Figure 7-2 shows the state changes involved in detecting voice in a low power mode.

No voice No trigger
detected detected

Trigger
Duty cycle Voice phrase
Low power - Wake up - Active for
wake detected detected
Device idle Listening voice Listening trigger any other
(default: 2 MHz) (default: 32MHz) operation
No voice No trigger
detected in found
duty time Timeout
Voice
Wake up - command

huc1507560333898.2
No voice Listening Voice detected
command command
Timeout No
command
detected

Figure 7-2 Always On Voice state diagram

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8 Audio interfaces

8.1 Analog audio interfaces

QCC5121 WLCSP analog interfaces include:
■ Line/Mic inputs
■ Line/Headphone outputs

8.1.1 Line/Mic inputs

QCC5121 WLCSP has two high-quality audio input ADCs (HQADC), primarily intended for line input use, but also
suitable for other applications that support mixed differential and single ended use cases. The ADC is 24‑bit, and
capable of sample rates from 8 kHz to 96 kHz. The HQADC is configurable, with an internal switch arrangement, see
Figure 8-1. VAG is a virtual ground reference. The software API allows for direct control of the nine switches, or a
simpler control, supporting three standard modes:
■ Stereo differential input (switch value 0xC6)
■ Stereo single ended input, using the P inputs (switch value 0xA5)
■ Stereo single ended input, using the N inputs (switch value 0x14A)
Inputs should be AC coupled, typically with a 2u2 capacitor. This capacitor value can be reduced at the expense of
low frequency response attenuation.

VAG

S8

IN1P
S7
PreAmp ADC
S6
IN1N

S5

VAG

S4
VAG

S3

IN2P
S2
PreAmp ADC
oyi1492787650311.2

S1
IN2N

S0

VAG

Figure 8-1 QCC5121 WLCSP high-quality ADC input switch configuration

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QCC5121 WLCSP Data Sheet Audio interfaces

Each ADC channel receives a differential/single-ended input and generates a 3‑bit Delta-Sigma modulated output
that goes to the decimation filter block in the digits. The ADC serves both line and mic modes. Both channels have
independent references, and most control signals are also independent.
The input is fed into a programmable gain amplifier. The audio output from the pre-amplifier stage is always
differential and has a maximum amplitude of 2.4 Vpp. The pre-amplifier can support single ended and differential
inputs at the same input amplitude. At 0 dB gain the maximum input is 2.4 Vpp, see Table 8-1.
Table 8-1 High-quality ADC analog gain vs. input impedance and input amplitude

Input amplitude (mVpp, differential,

Analog system gain (dB) Input impedance (kΩ) and single ended)

0 20 2400
3 20 1699
6 20 1203
9 20 852
12 20 603
15 20 427
18 20 302
21 20 214
24 20 151
27 10 107
30 10 76
33 10 54
36 10 38
39 10 27

If the audio signal is single ended, the input goes ~300 mV below ground and ~300 mV above the 1.8 V audio power
supply rail. The input impedance is 20 kΩ with gains 0 dB to 24 dB, and 10 kΩ at higher gains. A gain of 0 dB is
typically used for line-input while higher gain settings are used when a low-level MIC signal is sampled. Both
channel's ADCs are driven with 8 MHz clock and produces the digital output with the same rate.
Inputs should be AC coupled, typically with a 2.2 μF capacitor. This capacitor value can be reduced at the expense of
low frequency response attenuation.
The ADC clocks are derived from a 32 MHz low jitter reference clock.
QCC5121 WLCSP has a microphone bias source, capable of biasing two external analog microphones at a load
current of up to 3 mA.

8.1.2 Line/Headphone outputs

Two high-quality audio output DACs (HQDAC) drive stereo low impedance differential loads (BTL headphones) or
Line out.
DAC clocks are derived from a 32 MHz low jitter reference clock.
The HQ-DACs support two modes of operation. Class-D is a high efficiency, switching mode amplifier. The
secondary Class-AB is a linear amplifier, and consumes more power.

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QCC5121 WLCSP Data Sheet Audio interfaces

QCC5121 WLCSP also has a low-power mode, where the entire analog loop can be disabled and a digital PWM bit-
stream can drive the Class-D amplifier directly. This low-power mode can be used to trade off performance vs. power
consumption.
Table 8-2 Headset output driver modes

Mode Description

Class-D Enables a lower power consumption for the headset.

3-state BD modulation enables a filter-free configuration.
Directly driven from the digital circuitry.
Most of the analog portion is powered-down.
Drives differential headphone loads of 16/32 Ω.
Class-AB Enables either headphone or speaker applications.
Can drive the same headphone outputs instead of switching to Class-D.
Typically, useful for driving high impedance loads such as differential line out, or analog input
power amp.

8.2 Digital audio interfaces

Audio digital interfaces include:
■ Digital microphone inputs
■ Standard I²S/PCM interface
■ SPDIF interface
■ Audio MCLK

8.2.1 Digital microphone inputs

Up to six channels of digital microphone inputs are supported. These are grouped as three pairs.
Most digital mics can be configured to enable two microphones to share a single data line. QCC5121 WLCSP
supports this mode. It is achieved by one microphone outputting data on the rising clock edge and the other
outputting data on the falling edge of the clock, while otherwise tri-stating their output.
Four digital mic clock frequencies can be generated, configurable at 500 kHz, 1 MHz, 2 MHz and 4 MHz. Multiple
microphones can share the same clock.
The digital mic function can be assigned to PIOs, see Related Information.
Related Information
“QCC5121 WLCSP device terminal functions (PIO)” on page 20

8.2.2 Standard I²S/PCM interface

QCC5121 WLCSP provides a standard I²S/PCM interface capable of operating at up to a 192 kHz sample rate.
The I²S/PCM port is highly configurable, and has the following options:
■ Master (generate CLK and WS) or Slave (receive CLK and WS)
■ Word Select polarity
■ Left or right justification
■ Sign extension / zero pad

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QCC5121 WLCSP Data Sheet Audio interfaces

■ Optional 1‑bit period delay on WS to start of channel data

■ 13/16/24-bit per sample
■ Up to four slots per frame

NOTE In multislot operation with 3 or 4 slots per frame, data padding to 32 bits within slots is not possible.

8.2.3 I²S/PCM master mode timing diagram

t dmclksynch t dmclkhsyncl

WS

f mlk

t mclkh t mclkl

CLK

t dmclklpoutz

t dmclkpout tr ,t f t dmclkhpoutz

I2S_DOUT MSB (LSB) LSB (MSB)

ory1492787796422.2
t supinclkl t hpinclkl

I2S_DIN MSB (LSB) LSB (MSB)

Figure 8-2 I²S/PCM master mode timing diagram

Table 8-3 I²S/PCM master mode timing diagram symbols

Symbol Parameter Min Typ Max Unit

tdmclksynch Delay time from I2S_CLK high to I2S_SYNC - - 20 ns

high
tdmclkpout Delay time from I2S_CLK high to valid - - 20 ns
I2S_OUT
tdmclkhsyncl Delay time from I2S_CLK high to I2S_SYNC - - 20 ns
low
tdmclklpoutz Delay time from I2S_CLK low to I2S_OUT - - 20 ns
high impedance
tdmclkhpoutz Delay time from I2S_CLK high to I2S_OUT - - 20 ns
high impedance
tsupinclkl Set-up time for I2S_IN valid to I2S_CLK low - - 20 ns
thpinclkl Hold time for I2S_CLK low to I2S_IN invalid 0 - - ns

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QCC5121 WLCSP Data Sheet Audio interfaces

8.2.4 I²S/PCM slave mode timing diagram

f sclk

t sclkh t tsclkl

WS

t susclksynch t hsclksynch

CLK

t dpoutz
t dpoutz
t dsclkhpout tr ,t f

I2S_DOUT MSB (LSB) LSB (MSB)

ach1492787836140.2
t supinsclkl t hpinsclkl

I2S_DIN MSB (LSB) LSB (MSB)

Figure 8-3 I²S/PCM slave mode timing diagram

Table 8-4 I²S/PCM slave mode timing diagram symbols

Symbol Parameter Min Typ Max Unit

thsclksynch Hold time from I2S_CLK low to I2S_SYNC 5 - - ns

high
tsusclksynch Set-up time for I2S_SYNC high to I2S_CLK 15 - - ns
low
tdsclkhpout Delay time from CLK high to I2S_OUT valid - - 20 ns
data
tdpoutz Delay time from I2S_SYNC or I2S_CLK low, - - 20 ns
whichever is later, to I2S_OUT data line high
impedance
tsupinsclkl Set-up time for I2S_IN valid to CLK low 15 - - ns
thpinsclkl Hold time for I2S_CLK low to I2S_IN invalid 5 - - ns

8.2.5 SPDIF interface

SPDIF (IEC 60958) is a digital audio interface. It uses biphase coding to minimize the DC content of the transmitted
signal, and enables the receiver to decode clock information from the transmitted signal. QCC5121 WLCSP has up
to two SPDIF interfaces configurable as input or output. These interfaces are compatible with IEC 60958-1, IEC
60958-3, IEC 60958-4, and AES/EBU standards.
Signals are input/output via PIO and typically require external line drivers (for 75 Ω cabling) or optical transceivers
(‘Toslink’). Any PIO is assignable for SPDIF use.

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QCC5121 WLCSP Data Sheet Audio interfaces

8.2.6 Audio MCLK

QCC5121 WLCSP has two internal clock sources for audio interfaces. A standard 120 MHz clock (divided down), or
an independent PLL (MPLL) that is useable as an alternate MCLK frequency clock source for the I²S/PCM and
SPDIF ports. When it cannot be generated directly from the 120 MHz clock, the MPLL can be output on a PIO for use
by an external codec where low jitter I²S/PCM and SPDIF performance is required.
Table 8-5 lists the output frequencies that the MPLL can generate.
The MPLL increases system power consumption and therefore only used when necessary.
Table 8-5 Audio MCLK clock output frequencies

Sample rate (kHz)

MCLK frequency (Hz)
MCLK divided by 128 MCLK divided by 256 MCLK divided by 384

1,024,000 8 - -
2,048,000 16 8 -
3,074,000 24 - 8
4,096,000 32 16 -
5,644,800 44.1 - -
6,144,000 48 24 16
8,192,000 - 32 -
9,216,000 - - 24
11,289,600 88.2 44.1 -
12,288,000 96 48 32
16,934,400 - - 44.1
18,432,000 - - 48
22,579,200 176.4 88.2 -
24,576,000 192 96 -
33,868,800 - - 88.2
36,864,000 - - 96
45,158,400 - 176.4 -
49,152,000 - 192 -
67,737,600 - - 176.4
73,728,000 - - 192

8.3 Simultaneous audio routing

There are some limitations on how QCC5121 WLCSP can simultaneously use its audio inputs and outputs.

8.3.1 Codec inputs

Table 8-6 lists conditions in which six codec inputs can be active simultaneously.

NOTE Each codec input channel can only be used for an analog input or a digital mic, but not both
simultaneously.

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QCC5121 WLCSP Data Sheet Audio interfaces

Table 8-6 Codec input use conditions

Channel Analog Digital

Codec Input A ADC Left Digital Microphone

Codec Input B ADC Right Digital Microphone
Codec Input C N/A Digital Microphone
Codec Input D N/A Digital Microphone
Codec Input E N/A Digital Microphone
Codec Input F N/A Digital Microphone

8.3.2 Codec outputs

Table 8-7 lists conditions in which two codec outputs can be active simultaneously.
Table 8-7 Codec output use conditions

Channel Analog

Codec Output A DAC Left

Codec Output B DAC Right

8.3.3 Audio slots

QCC5121 WLCSP has audio slots, where one slot is a single audio data stream.

NOTE QCC5121 WLCSP can support a maximum of 8 active audio input slots and 8 active audio output slots
simultaneously.

Table 8-8 lists typical QCC5121 WLCSP audio slot usage.

Table 8-8 QCC5121 WLCSP audio slots

Interface Number of slots Notes

Stereo I²S 2 -
SPDIF 3 M, W, and user data channels per SPDIF interface
PCM 2 to 4 One slot per channel. For example, 4 channel PCM requires
4 slots
Analog ADC 2 Per stereo ADC
Analog DAC 2 Per stereo DAC
Digital microphone 1 One slot per channel. For example, 4 digital mics require 4
slots

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9 Peripheral interfaces

9.1 PIO
QCC5121 WLCSP has the following digital I/O pads:
■ 15 PIO pads
■ 6 x pads for the Applications subsystem QSPI interface
■ 5 x pads intended for LED operation: LED[5:4, 2:0]
■ 1 x Reset (active low) pad: PIO[1]
■ 1 x Output on standard pad: XTAL_CLKOUT
■ 1 x Power-on signaling: SYS_CTRL, usable as an input after boot.
■ USB device I/O: If not used for USB purposes, this port is usable as digital I/O.

9.2 PIO pad allocation

The following QCC5121 WLCSP functions have specific pad allocations:
■ QSPI (for the Applications subsystem)
■ LED pads
■ Transaction bridge
■ Audio I²S/PCM

NOTE Digital microphones, SPDIF, UART, Bit Serializer (I²C/SPI), and LED PWM controllers can use any PIO.

9.3 Standard I/O

The standard digital I/O pins (PIO) on QCC5121 WLCSP are split into separate pad domains. Each VDD_PADS
domain can be separately powered, from 1.7 V to 3.6 V. The VDD_PADS of a particular pin should be powered
before voltages are supplied to PIO powered by that domain otherwise back powering can occur through the ESD
protection in the pad.

PIO can be programmed to have a pull-up or pull down with two strengths (weak and strong). PIO can also be
programmed with a sticky function where they are strongly pulled to their current input state. PIO have a reset pull
state, after reset the pulls can be re-configured by software.

PIO also have a programmable drive strength capability of 2, 4, 8, or 12 mA.

All PIO are readable by all subsystems, but for write access are assigned by software to particular subsystem
control. PIO inputs are via Schmitt triggers.

9.4 Pad multiplexing

A QCC5121 WLCSP pad’s function is chosen at runtime from multiple potential functions, using multiplexing.

In the input direction, signals driven into the chip, all PIOs are distributed to each subsystem and visible on the PIO
status bus. It is the subsystem's responsibility to select I/Os of interest for a particular application.

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QCC5121 WLCSP Data Sheet Peripheral interfaces

In the output direction, the System Manager has overall control of PIO allocation and control. When a PIO is
allocated to a particular subsystem, the output is propagated combinationally from the subsystem to the pad. That is,
there are no registers between the subsystem and the pad.

The LED pins and some other peripheral I/O states can be read as virtual PIO, see Table 9-1.

Table 9-1 Virtual PIO

Function PIO

SYS_CTRL PIO[0]
LED[5:4, 2:0] PIO[71:70, 68:66]
USB_DN PIO[63]
USB_DP PIO[62]

9.5 RESET# reset pin

The QCC5121 WLCSP digital reset pin (RESET#) is an active low reset signal. PIO[1] defaults to RESET# upon
boot.
The pin is active low and on-chip glitch filtering avoids the need to filter out any spurious noise that may cause
unintended resets. The RESET# pin has a fixed strong pull-up to VDD_BYP, and therefore can be left unconnected.
The input is asynchronous, and is pulse extended within QCC5121 WLCSP to ensure a full reset.
QCC5121 WLCSP contains internal Reset Protection functionality to automatically keep the power rails enabled and
enable the system to restart after unintended reset (such as a severe ESD event). Therefore for short assertions of
RESET# the device does not turn off due to Reset Protection functionality.
Assertion of RESET# beyond the Reset Protection timeout (typically greater than ~1.8 s) causes the device to power
down. QCC5121 WLCSP then requires a SYS_CTRL assertion or VCHG attach to restart.

NOTE QCC5121 WLCSP is always powered if VCHG is present. It does not power down if RESET# is
asserted while VCHG remains present.
QTIL recommends that QCC5121 WLCSP is powered down via software-controlled methods rather
than external assertion of RESET#.
Holding RESET# low continuously is not the lowest QCC5121 WLCSP power state, because pull
downs are enabled on VCHG and VDD_BYP in this state.

After boot, PIO[1] is configurable as a digital PIO.

9.6 SYS_CTRL pin

SYS_CTRL is an input pin that acts as a power on signal for the internal regulators. It can also be used as an input
(appears to software as virtual PIO[0]) or as a multifunction button.
From the OFF state, SYS_CTRL must be asserted for >20 ms to start power up.
SYS_CTRL is VBAT tolerant (4.8 V max), and typically connected via a button to VBAT. SYS_CTRL has no internal
pull resistor, and requires an external pull-down if left undriven.
SYS_CTRL can be logically disconnected from the power on signal for internal regulators by software. Therefore, for
example, once booted, software takes control of the internal regulators and the state of SYS_CTRL is ignored by the
regulators.

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QCC5121 WLCSP Data Sheet Peripheral interfaces

9.7 LED pads

QCC5121 WLCSP contains six LED pads that are configurable in four different operating modes:

1. LED Driver: This mode is designed for driving LEDs. The pad operates as an open-drain pad, tolerable of
voltages up to 7.0 V. Therefore the cathode of the LED should be connected to the QCC5121 WLCSP LED pad.
Each pad is rated to sink up to 50 mA of current.
2. Digital / Button input: This mode is designed for slow input signals, typically buttons. It is not designed for fast
switching digital inputs like SPI. For these types of inputs, use the standard PIOs.
In this mode, an internal weak pull-down can be enabled. Typically this is used for active high button signals to
ensure that the input returns to 0 when the button is released. The pads are 7.0 V tolerant and the logic 1
threshold is typically 1 V.
In digital input mode, the logic inputs can be read by the software as virtual PIO[71:70, 68:66].
3. Analog input: In this mode, the LED pad is used as an analog input port. The pad voltage is routable to a 10‑bit
auxiliary ADC.
In analog input mode, the input range is 0 to VDD_1V8_LDO.
4. Disabled: This is the default state for LED pads, where the pad is 7.0 V tolerant and a high impedance with no
pull-down.

9.8 LED controllers

QCC5121 WLCSP has six PWM-based LED controllers, controlled by the Applications subsystem. They are usable
for driving the LED pads or other PIOs.
It is possible for an application to configure the LED flash rate and ramp time.
Once configured, the LED flash and ramp rate are fully hardware controlled within the LED/PWM module. It is
possible to synchronize any number of the six LED drivers together. Together with the hardware flash/ramp, this is
usable for generating color change sequences on RGB LEDs.
LED outputs are able to operate in Deep Sleep state, but not in Dormant state.
The six PWM blocks repeat up the 72 virtual PIOs (which are labeled from 0 to 71). The configuration is the same
whether the PWM controller is driving a PIO or an LED pad.
Table 9-2 shows the repeating LED controller pattern.
Table 9-2 LED controller pattern

LED_PWM PIO
Number

LED_PWM[0] PIO[0], PIO[6], PIO[12], PIO[18], PIO[24], PIO[30], PIO[36], PIO[42], PIO[48], PIO[54], PIO[60], PIO[66]
LED_PWM[1] PIO[1], PIO[7], PIO[13], PIO[19], PIO[25], PIO[31], PIO[37], PIO[43], PIO[49], PIO[55], PIO[61], PIO[67]
LED_PWM[2] PIO[2], PIO[8], PIO[14], PIO[20], PIO[26], PIO[32], PIO[38], PIO[44], PIO[50], PIO[56], PIO[62], PIO[68]
LED_PWM[3] PIO[3], PIO[9], PIO[15], PIO[21], PIO[27], PIO[33], PIO[39], PIO[45], PIO[51], PIO[57], PIO[63], PIO[69]
LED_PWM[4] PIO[4], PIO[10], PIO[16], PIO[22], PIO[28], PIO[34], PIO[40], PIO[46], PIO[52], PIO[58], PIO[64], PIO[70]
LED_PWM[5] PIO[5], PIO[11], PIO[17], PIO[23], PIO[29], PIO[35], PIO[41], PIO[47], PIO[53], PIO[59], PIO[65], PIO[71]

NOTE Not all PIOs may be usable with the PWM generator due to other functions being assigned by an OEM.

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QCC5121 WLCSP Data Sheet Peripheral interfaces

In the PIO allocation LED_PAD[0] = PIO[66], LED_PAD[1] = PIO[67], LED_PAD[2] = PIO[68], LED_PAD[4] =
PIO[70], and LED_PAD[5] = PIO[71]. The mapping from the LED pad number to the LED_PWM driver is:
■ LED_PAD[0] = PIO[66] = LED_PWM[0]
■ LED_PAD[1] = PIO[67] = LED_PWM[1]
■ LED_PAD[2] = PIO[68] = LED_PWM[2]
■ LED_PAD[4] = PIO[70] = LED_PWM[4]
■ LED_PAD[5] = PIO[71] = LED_PWM[5]

9.9 USB interface

QCC5121 WLCSP has a USB device interface: An upstream port, for connection to a host Phone/PC or battery
charging adaptor.
For details software support for USB features, refer to ADK documentation.

9.10 USB device port

The device port is a USB2.0 Full Speed (12 Mb/s) port. Typically QCC5121 WLCSP enumerates as a compound
device with a hub with the enabled audio source / sink / HID / mass storage device appearing behind this hub.
The DP 1.5 k pull-up is integrated in QCC5121 WLCSP. No series resistors are required on the USB data lines.
QCC5121 WLCSP contains integrated ESD protection on the data lines to IEC 61000-4-2 (device level). In normal
applications, no external ESD protection is required.
Extra ESD protection is not required on VCHG (VBUS) because QCC5121 WLCSP meets the USB certification
requirements of a minimum of 1uF, and a maximum of 10 µF being present on VCHG (VBUS).
The VCHG input of QCC5121 WLCSP is tolerant of a constant 6.5 V and transients up to 7.0 V. If extra overvoltage
protection is required, external clamping protection devices can be used.

9.11 USB charger detection

QCC5121 WLCSP supports charger detection to the USB BCv1.2 standard.
It provides Data Contact Detection (DCD) using an internal current source, and provides:
■ Detection of standard downstream ports (SDP)
■ Charging downstream ports (CDP)
■ Dedicated downstream ports (DCP)
The voltage on the USB data lines can be read by the 10‑bit auxiliary ADC. This allows detection of proprietary
chargers that voltage bias USB the data lines.
For USB C type connectors, the LED pins can be used to detect the voltage on the CC line pins to detect the charge
current capabilities of the upstream device.

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10 Transaction bridge

The transaction bridge is an external bridge into the internal transaction bus between QCC5121 WLCSP
subsystems. It is the primary debug interface and can also be used for production programming.
A USB to transaction bridge interface (TRBI200) is available. For details, contact a QTIL sales representative.
The transaction bridge is multiplexed on PIO[8:2], see Table 10-1.
TRBI200 can use USB3.0 for maximum data rate.

NOTE USB3.0 signals can generate noise in the Bluetooth ISM band. For applications where sensitive RF
measurements take place, QTIL recommends connecting TRBI200 using USB2.0.

The transaction bridge is a multilane interface, and only requires three wires for its minimum configuration (suitable
for production programming).

NOTE Minimum configuration is sufficient for production programming and code download, but not for
extensive debug and code tracing. The configuration in use is automatically detected.

Table 10-1 Transaction bridge PIO multiplex

Required for minimum

TRB PIO Intermediate configuration Full bus width
configuration

RXCLK PIO[8] Yes Yes Yes

TX_D0 PIO[7] Yes Yes Yes
RX_D0 PIO[6] Yes Yes Yes
TX_D1 PIO[5] No Yes Yes
RX_D1 PIO[4] No Yes Yes
TX_D2 PIO[3] No No Yes
TX_D3 PIO[2] No No Yes

NOTE PIO[7] should not be held low during boot.

Transaction bridge debug access is lockable. When locked, this interface only becomes active after the correct
unlock key sequence is provided.

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11 Boot Manager

Boot Manager

wcn1480340633806.4
OTP Memory

Figure 11-1 Boot Manager

The Boot Manager, see Figure 11-1, performs all low-level housekeeping functions. It manages chip boot and the
lowest level stages of Deep Sleep and Dormant state entry/exit.

11.1 OTP memory

QCC5121 WLCSP contains one-time programmable memory areas, used to hold a 128‑bit customer programmable
security key.

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12 System Manager

System Manager

mth1478625942759.4
Firmware Processor

Figure 12-1 System Manager

The System Manager, see Figure 12-1, runs from ROM and controls the allocation of the resources in the system
and coordinates firmware operation using message-passing and interaction with the other subsystems.
Chip-level sleep modes are coordinated by the System Manager. Each subsystem indicates to the System Manager
that they are asleep. System Manager can individually disable clocks and/or power to subsystems in turn to minimize
device power.

12.1 System timer

The System Manager maintains a 1 MHz system timer, which is distributed to the subsystems in the hardware using
the transaction bus. The system time has 20 ppm, 250 ppm, and 20% modes to optimize current in low-power states.

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13 PMU subsystem

PMU Subsystem

SMPSs and LDOs

naf1478625986091.5
Li-ion Battery (3.7 V) and charge Li-ion Battery
Auxiliary ADC
Charger

Figure 13-1 PMU subsystem

The power management unit (PMU) subsystem, see Figure 13-1, is designed to support Li-ion batteries, integrating
a charger with Instant-On support. Instant-On enables QCC5121 WLCSP to operate regardless of the state of the
battery, or even when the battery is removed.

QCC5121 WLCSP VFBGA has 2 SMPSs. The 1.8 V SMPS provides power for the chip circuitry and external
customer circuits. The digital SMPS is used to power the internal digital circuits.

13.1 Li-ion charger

The QCC5121 WLCSP Li-ion charger is designed to support small to large batteries (several Amp hours). It is
connectable in one of two modes:
■ Internal configuration: Supporting charge rates of 2 mA to 200 mA with no external components required.
■ External configuration: Supporting charge rates of 200 mA to 1800 mA with the addition of one PNP pass device
and external resistor.

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QCC5121 WLCSP Data Sheet PMU subsystem

13.2 General charger operation

The charger system has five main operating states. The current charger status can be read by application software.
Figure 13-2 shows the five states in the charge cycle.

oiy1491460154670.2
Figure 13-2 Charge cycle states

Trickle charge
This mode is entered when VBAT is sensed in the range 0 to Vpre. This is encountered only with a deeply
discharged battery (below Vpre threshold, point (A)), or when the cell's battery protection circuit has opened,
temporarily disconnecting the cell. It is used to pass a small charging current to safely charge a cell, and also cause
a cell battery protection circuit to reset.

The hysteresis on Trickle charge into Pre-Charge is typically 100 mV.

During Trickle charge, QCC5121 WLCSP controls charge current internally. The external pass transistor is not used.
Table 13-1 Parameters in Trickle charge

Parameter Description Min Typ Max

Vpre threshold (A) Voltage at which the charger transitions out of Trickle 2.0 V 2.1 V 2.2 V
charge into Pre-charge.
Itrick Trickle charge current. 1 mA - 50 mA

Pre-charge
This mode is entered when VBAT is sensed in the range Vpre to Vfast. In this range, it is not recommended to charge
the cell at maximum rate, but a faster charge rate than that of Trickle charge is allowable. Typically this is ~10 % to
20 % of the Fast charge rate. The Vfast threshold, point (B) is programmable.

The hysteresis on the Vfast transition from Pre-Charge to Fast charge is typically 200 mV.

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QCC5121 WLCSP Data Sheet PMU subsystem

During Pre-Charge, QCC5121 WLCSP controls the charge current internally and the external pass transistor is not
used.

Table 13-2 Parameters in Pre-charge

Parameter Description Min Typ Max

Vfast threshold (B) Voltage at which the charger transitions out of Pre- 0 = 2.8 V 0 = 2.9 V 0 = 3.0 V
charge into Fast charge.
1 = 2.9 V 1 = 3.0 V 1 = 3.1 V
2 = 3.0 V 2 = 3.1 V 2 = 3.2 V
3 = 2.4 V 3 = 2.5 V 3 = 2.6 V
Ipre Pre-charge current. 2 mA - 200 mA

Fast charge
Fast charge has two parts:
■ Constant current: Entered when VBAT is sensed in the range Vfast to Vfloat point (C). This is the maximum
charge rate, and should be set according to the battery manufacturers Data Sheet.
■ Constant voltage: When Vfloat is reached the cell voltage is maintained at Vfloat, and the current slowly
reduces until the termination point (E) is reached where charging ceases, and the charger transitions to Standby
mode.
Vfloat can be configured from 3.65 V to 4.40 V in 5 mV increments. This allows use of cells with different Vfloat
values, or cell life extension by reducing Vfloat. Vfloat can also be altered depending on temperature change, for cell
life protection.

The current termination point (E) can be adversely influenced by dynamic changes in VBAT load current, or to a
lesser extent changes in VCHG voltage.

Table 13-3 Parameters in Fast charge

Parameter Description Min Typ Max

Ifast Ifast 2 mA - 200 mA

Fast charge current (Internal mode).
Ifast Ifast - - 1.8 A
Fast charge current (External mode).
Termination point (E) Transition from fast charge (constant voltage) to - 0 = 10 -
Standby. Expressed as % of Ifast.
1 = 20
2 = 30
3 = 40

Standby mode
Once the charge current has fallen and the charger is terminated, the system enters Standby mode. In Standby
mode, the charger does not charge. It continues to monitor the battery voltage. If the voltage falls back below Vfloat
by more than a configurable threshold Vhyst, point (D), then the charger re-enters Fast charge mode. Vhyst is
expressed as a percentage of Vfloat.

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QCC5121 WLCSP Data Sheet PMU subsystem

In this way, the charger system maintains the cell near full charge while prolonging cell life.

Table 13-4 Parameters in Standby mode

Parameter Description Min Typ Max

Vhyst threshold (D) Percentage of Vfloat at which the charger moves from 0 = 0.006 0 = 0.012 0 = 0.018
Standby back to Fast charge.
1 = 0.018 1 = 0.024 1 = 0.030
2 = 0.030 2 = 0.036 2 = 0.042
3 = 0.042 3 = 0.048 3 = 0.054

13.2.1 Battery protection

Deeply discharging a Li-ion battery for a long time can cause irreversible damage, leading to excessive heating on a
subsequent charger cycle.
To prevent this, customer application software should turn off the device at ~3.0 V. Typically cells have ~5 % usable
capacity left at this point.
QTIL strongly recommends that all applications include a battery protection IC, normally built into the battery pack
itself, as a secondary level of protection. This protection typically disconnects the battery cell if the voltage drops too
low, or goes too high, and protects against overcurrent in the connections between QCC5121 WLCSP and the cell
itself.

13.2.2 Temperature measurement during charging

Application layer software can be used to monitor the battery temperature using an NTC thermistor, typically
mounted in contact with the cell. This information can then be used to disable charging or alter the charge current at
extremes of temperature.
For temperature measurement, software can be configured to drive an enable signal to a potential divider, which
consists of an external 10K resistor and 10K NTC in series. A PIO is used to provide a switched 1.8 V nominal supply
to the external 10K resistor; this minimizes the external consumption. An LED pad would be required as a sense line
from the 10K NTC thermistor.
Related Information
“QCC5121 WLCSP device terminal functions (AIO/LED drivers)” on page 23

13.3 Charging modes

The QCC5121 WLCSP charger is designed to work in one of two modes:
■ Headset mode: Delivers a known current into the battery with the system (IC + all external components) running
directly from VCHG.
■ Speaker mode: Limits the current taken from the VCHG port to a known value. In this mode, the system can take
peak currents from the battery during charging, and as long as the average current into the battery is higher than
the average current taken from the battery the system charges.

13.4 External charger

In external charging mode, a single external PNP pass transistor is used for fast charge. QCC5121 WLCSP senses
the charging current by measuring the voltage drop across an external sense resistor (between the VCHG and
VCHG_SENSE pins) and controls the base current of the PNP transistor.
At the higher currents available in external mode, the routing of VBAT_SENSE becomes more critical. The
VBAT_SENSE pin should be routed separately back to the battery itself to ensure that the cell voltage is sensed
correctly and not influenced by volt drops in PCB tracks.

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QCC5121 WLCSP Data Sheet PMU subsystem

The charge current can be configured using the ADK configuration tool. The ADK configuration tool allows
configuration of different charge rates dependent on temperature and type of USB charger detected. The ADK
configuration tool uses the supplied Rsense tolerance and assumes the worst case actual Rsense to configure the
charger, this ensures that the charge current never exceeds the appropriate value.
For more information, refer to ADK documentation.

13.4.1 Selection of sense resistor value

At maximum charge current setting, the sense resistor Rsense should be chosen to give 100 mV voltage between the
VCHG and VCHG_SENSE pins. For example, a 100 mΩ Rsense resistor gives a max charge current of 1 A, while a
68 mΩ Rsense resistor gives a max charge current of 1.5 A.
The fast charge current is configurable for charge currents equivalent to 5 mV steps over the range of 25 mV to
100 mV across Rsense.
Ensure that the sense resistor is suitably rated to dissipate heat generated within it. QTIL recommends 1% or lower
tolerance Rsense resistors to ensure accurate charge current measurement.
For more information, refer to ADK documentation.

13.4.2 Selection of PNP transistor

The PNP transistor should have an Hfe lower than 700. Do not use high gain or Darlington type transistors. Ensure
that the transistor and heatsinking are suitably rated to dissipate generated heat at maximum charge current. Select
an Hfe to keep the base current in normal operating modes in the range 0 mA to 40 mA. In low VCHG conditions, the
base current may exceed this and QCC5121 WLCSP controls the base current to a safe limit.

NOTE The base current of the PNP transistor is drawn from VCHG. Account for this if VCHG current has to be
limited to a set maximum.

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QCC5121 WLCSP Data Sheet PMU subsystem

13.5 Power regulation

QCC5121 WLCSP integrates all regulators required for typical applications. Figure 13-3 shows the internal regulator
power flow.

NOTE For clarity, Figure 13-3 does not show all I/O connectors and external passive components. For all
power connections and decoupling capacitor values, see Related Information.

USB_VBUS (VCHG) ANA LDO KA LDO Digits Keep Alive Supply

Bypass LDO
VBAT

2.9 / 3.3 V

USB Pads Supply

Microphone Bias Output

Audio Analog
Mic Bias

VDD_DIG Digits Supply

USB_VBUS (VCHG)
Digital SMPS
VBAT

SMPS
System SMPS
DCPL

System 1.8 V Rail

tog1495720508843.6
RF_LO LDO Bluetooth LO Supply

RF_PA LDO Bluetooth PA Supply

Figure 13-3 Power regulation

Related Information
“QCC5121 WLCSP example application schematic” on page 60

13.5.1 Switch mode regulators

For optimum power efficiency QCC5121 WLCSP contains two switch mode regulators. These can be powered from
VBAT or VCHG under application software control.
The System SMPS generates the main 1.8 V supply rail, which supplies most of the analog circuits on QCC5121
WLCSP. It can also be used to supply QSPI flash memory and external components.
The digital SMPS generates the power for the digital circuits. It is variable voltage and automatically switches
between 1.1 V (nominal) and 0.85 V (nominal) in low-power modes.

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QCC5121 WLCSP Data Sheet PMU subsystem

The SMPS both have three operating modes, Normal (PWM), and two lower power modes with reduced current
capability, PFM, and ULP. Normally the system auto switches, but this can be optionally disabled.
The SMPS is designed to use a 4.7 µH inductor and a 2.2 µF output capacitor.
For guidance on choice of inductor, capacitor and layout, refer to QCC5121 WLCSP Hardware Layout Guide
Application Note.
A single node SMPS_DCPL is a low impedance decoupling point for the inputs to both SMPS. This point must have
a 2.2 µF. It is recommended to have a 100 nF capacitor on the SMPS_DCPL point.
The SMPS Regulators are enabled by a rising edge on SYS_CTRL, or a rising edge on VBAT or presence of VCHG.

13.5.2 Bypass LDO regulator

For circuits that require 3.3 V such as USB, the QCC5121 WLCSP contains a Bypass LDO regulator. This can be
powered from VBAT or VCHG under application software control. It has a variable output voltage, and automatically
switches between 3.3 V (nominal) when powered from USB (VCHG) and 2.9 V (nominal) when supplied from VBAT.
Bypass LDO regulator output is available for use by external peripherals.

NOTE In Deep Sleep and Dormant modes the bypass LDO regulator switches to a lower power mode, with
reduced regulation and lower current capability. This reduces overall system power consumption. This
low-power mode can be disabled if not required.

Enable the Bypass LDO regulator using a rising edge on SYS_CTRL, or a rising edge on VBAT, or by the presence
of VCHG.

13.5.3 KA regulator
The Keep Alive (KA) regulator generates a supply for the internal blocks that remain powered in the lowest power
states.

NOTE The KA regulator should not be used for external circuits.

NOTE Connect a 470n capacitor on the output.

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14 QCC5121 WLCSP example application schematic

Battery
Stereo Headset
with USB-C, 2x DigMics stereo, 2x AnaMics
GND

External charger up to 1.8A (optional)

or up to 200mA if internal charger is used
Total 15 PIOs (including debug) for PCM/UART/Buttons etc
(remove R1 and Q1 if internal charger is used, 1V8_SMPS
tie VCHG_SENSE to USB_VBUS, CHG_EXT float)
USB_VBUS Q1 VBAT
R1 VDD_DIG VDD_RADIO
0R1
L1 L2 C81
C1 2DB1713 C2 C3 C4 C5 C6 C7 C8 C9 C11 C10
4u7 4u7
2u2 2u2 2u2 2u2 2u2 C51 470n 2u2 C71 1u0 1u0 470n 10p 470n
470n 470n

27

15

23

24

16

18

22

17

66
57

68

60
61

38

37
6

4
GND GND

VCHG_SENSE

SMPS_DCPL
SMPS_VCHG

VDD_AUDIO_HP_SPKR
VBAT_SENSE

VDD_AUDIO_HP_SPKL
VDD_BYP_CHG

SMPS_VBAT
CHG_EXT

VDD_BT_1V8
VDD_BYP

VDD_AUDIO_1V8

VDD_BT_RADIO
LX_1V8

VDD_PMU_VINDIG

VDD_DIG
LX_DIG

VDD_XTAL_1V8
VBAT

VDD_AUX
VDD_VKA
KA_LDO
RF_PA
LDO
LDO
Charger LV_DIG 1V8_SMPS
LDO 20 U2 1V8_SMPS
VDD_PADS_2 SPI Flash
10 6 8

VDD_PADS_2
Sense Sense
QSPI1_CLK SCK VDD
Bypass LDO 1.8V Ana SMPS 1.1V Digital SMPS 29 1
QSPI1_CS0# CE
11 5
QSPI1_IO[0]
QSPI1_IO[1]
39 2
SI/SIO0
SO/SIO1
C12
100n
System QSPI Flash
30 3
QSPI1_IO[2] WP/SIO2
19 7 4
QSPI1_IO[3] HOLD/SIO3 VSS GND

USB_D_P 13
USB_DP
USB_D_N 3
USB_DN (*) Alternative functions:
UART, 2x Bitserial interface SPI/I2C
(I2C amp control, I2C/SPI for sensors interface)
50R
U3
50R or Digital Audio interfaces: SPDIF, DigMics
i i
ANT 2
OUT IN
4 BT_RF 46
BT_RF (2-channel 1-in/1-out SPDIF, up to 6 dig mics in stereo config)

QCC5121 WLCSP
Bluetooth RF C13
3 1 0p5
GNDGND
2.45GHz A cap between

81-ball 3.9798 x 4.0184 0.4mm pitch

the chip and the
GND
filter may be
required if the
filter is
reflective
1V8_SMPS
2
VDD_PADS_3
12

VDD_PADS_3
PIO[21]
PIO[20]
31
1
PIOs connected to DigMics
PIO[19]
21
PIO[18]
PIO[17]
40 1-Channel In/Out PCM/I2S Interface
49
PIO[16]
PIO[15]
41 Digital Audio In, Out to digital amp
1V8_SMPS
45
VDD_PADS_1
PIO[8]
54 Debug T-Bridge Interface single-lane
PIO[7]
52 (or additional PIOs if not used)

VDD_PADS_1
51
PIO[6]
PIO[5]
53 may also use PIO[2-5] for multi-lane T-Bridge
VBAT 50
PIO[4]
PIO[3]
44
48
PIOs connected to DigMics
S1 PIO[2]
ON/OFF
32
PIO[1]
56 Additional PIO
SYS_CTRL 33 (Note: this is Reset# during boot)
LED[0]/AIO[0]

AUDIO_MIC2_N/LINEIN_R_N
AUDIO_MIC2_P/LINEIN_R_P
AUDIO_MIC1_N/LINEIN_L_N
42

AUDIO_MIC1_P/LINEIN_L_P
R2 LED[1]/AIO[1]
10k 25
LED[2]/AIO[2]

AUDIO_HPR_N/SPKR_N

AUDIO_HPR_P/SPKR_P
AUDIO_HPL_N/SPKL_N
VSS_AUDIO_HP_SPKR

AUDIO_HPL_P/SPKL_P
VSS_AUDIO_HP_SPKL

34 USB-C_AIO
LED[4]/AIO[4]
43
VSS_BT_RF_GND

AUDIO_MIC_BIAS
VSS_AUDIO_REF

LED[5]/AIO[5]

AUDIO_DACREF
VSS_SMPS_DIG
VSS_SMPS_1V8

To PIO
VSS_DIG_PADS
VSS_DIG_PADS
VSS_BT_RADIO

AUDIO_BGBYP
R3
VSS_AUDIO
VSS_BT_LO

XTAL_OUT

10k
VSS_PMU
VSS_AUX

NC_GND

XTAL_IN

R7 R8 R9
330R 220R 220R
TH1
10k LD3

BLUE
D1 D2 GREEN

RED
73

47
55
64

26
35
14

80
67
59
63

28
36

65

75

74

79

78

70

76

77

71

81

72

62

58

69
VBAT

C21 C22 GND

XTL1 32MHz 10n 2u2
Battery temperature sense 3x RGB LEDs
1 3 C25 C26 C27 C28
2u2 2u2 2u2 2u2 GND GND
5x LED/AIOs: three for RGB LEDs, one for USB-C sensing,
Dig Mics 1V8_SMPS one for battery pack NTC sensing
2

GND GND
USB-C Stereo configuration C29 C30
USB_VBUS L6 R10 R11
(RH ANC) 100n 4u7 MIC_1
15nH 2k2 2k2
CON2
U6 GND Mic 1 C31
15p
B12
GND
USB-C
GND
A1
Vdd
7 Left Right
1 6
B11
RX1_P TX1_P
A2
GND Vdd Ana Mics (LH ANC) GND GND Speakers (16-32 Ohm)
2 5 DIGMIC_DIN1 L7
R12 LR DOUT MIC_2
B10 A3 USB_CC2
RX1_N TX1_N 15nH
100k 3 4
GND CLK
B9 A4 USB-C_AIO Mic2 C32
View into product receptacle

VBUS VBUS 15p

MP45DT02

hza1512740080916.1
B8 A5 USB_CC1 R13
SBU2 CC1
100k GND
GND GND
USB_D_N B7 A6 USB_D_P
D_N D_P U7
USB_D_P B6 A7 USB_D_N 7
D_P D_N Vdd
1 6
GND Vdd
USB_CC2 B5 A8
CC2 SBU1
2
LR DOUT
5 A5-A6 and B5-B6 can also be connected as Line Inputs (SE or Diff), AC-coupled
B4 A9
VBUS VBUS
3
GND CLK
4 DIGMIC_CLK (for SE Line input AC-GND the unused input)
B3 A10
TX2_N RX2_N
MP45DT02
R14 B2 A11 R15
5k1 TX2_P RX2_P 5k1 GND
B1 A12
GND GND
USB-C connector

Figure 14-1 QCC5121 WLCSP example application schematic

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15 Electrical characteristics

15.1 Absolute maximum ratings

Parameter Pin Min Max Unit

Storage temperature - -40 85 °C

Supply voltage
5 V (USB VBUS) CHG_EXT -0.4 7.0 V
LX_1V8
LX_DIG
SMPS_DCPL
SMPS_VCHG
VCHG_SENSE
VDD_BYP_CHG
Battery SMPS_VBAT -0.4 4.8 V
VBAT
VBAT_SENSE
3.3 V USB_DN -0.4 3.8 V
USB_DP
VDD_BYP
1.8 V AUDIO_BGBYP -0.4 2.1 V
AUDIO_DACREF
AUDIO_MIC_BIAS
AUDIO_MIC1_N/ LINEIN_L_N
AUDIO_MIC1_P/ LINEIN_L_P
AUDIO_MIC2_N/ LINEIN_R_N
AUDIO_MIC2_P/ LINEIN_R_P
VDD_AUDIO_1V8
VDD_AUDIO_HP_SPKL
VDD_AUDIO_HP_SPKR
VDD_AUX
VDD_BT_1V8
VDD_PMU_VINDIG
VDD_XTAL_1V8
1.8 V AUDIO_HPL_N/ SPKL_N -0.4 2.1 V
AUDIO_HPL_P/ SPKL_P
AUDIO_HPR_N/ SPKR_N
AUDIO_HPR_P/ SPKR_P
Digital I/O PIO[21:2] -0.4 3.8 V

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QCC5121 WLCSP Data Sheet Electrical characteristics

Parameter Pin Min Max Unit

QSPI1_CLK
QSPI1_CS0#
QSPI1_IO[3:0]
PIO[1]
VDD_PADS_3:1
AIO/LED[5:4, 2:0] -0.4 7.0 V
SYS_CTRL -0.4 4.8 V
1.2 V BT_RF -0.4 1.4 V
VDD_BT_RADIO
XTAL_IN
XTAL_OUT
1.1 V VDD_DIG -0.4 1.4 V
VDD_VKA
All ground / VSS pads - -0.4 0.4 V

NOTE Stressing the device beyond the Absolute Maximum Ratings may cause instantaneous and permanent
damage.
Device performance is not guaranteed beyond the Recommended Operating Conditions.
Prolonged exposure beyond the Recommended Operating Conditions may permanently affect device
reliability and/or performance.

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QCC5121 WLCSP Data Sheet Electrical characteristics

15.2 Recommended operating conditions

Parameter Pin Min Typ Max Unit

Operating temperature range - -40 20 85 °C

Supply voltage
5 V (USB VBUS) CHG_EXT 4.75 / 3.78a 5.0 6.5 V
SMPS_VCHG
VCHG_SENSE
VDD_BYP_CHG
SMPS_DCPL 2.8 3.7 / 5.0 6.5 V
LX_1V8 0 3.7 / 5.0 6.5 V
LX_DIG
Battery SMPS_VBAT 3.0 / 2.8b 3.7 4.6 V
VBAT
VBAT_SENSE
3.3 V VDD_BYP 2.8 2.9 / 3.3 3.5 V
USB_DN 0 - 3.6 V
USB_DP
1.8 V VDD_AUDIO_1V8 1.7 1.8 1.95 V
VDD_AUDIO_HP_SPKL
VDD_AUDIO_HP_SPKR
VDD_AUX
VDD_BT_1V8
VDD_PMU_VINDIG
VDD_XTAL_1V8
AUDIO_BGBYP 0 - 1.95 V
AUDIO_DACREF
AUDIO_MIC_BIAS
AUDIO_MIC1_N/
LINEIN_L_N
AUDIO_MIC1_P/
LINEIN_L_P
AUDIO_MIC2_N/
LINEIN_R_N
AUDIO_MIC2_P/
LINEIN_R_P
1.8 V AUDIO_HPL_N/ SPKL_N 0 - 1.95 V
AUDIO_HPL_P/ SPKL_P
AUDIO_HPR_N/ SPKR_N
AUDIO_HPR_P/ SPKR_P
Digital I/O VDD_PADS_3:1 1.7 1.8 3.6 V
PIO[21:2] 0 - VDD_PADS V

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QCC5121 WLCSP Data Sheet Electrical characteristics

Parameter Pin Min Typ Max Unit

QSPI1_CLK
QSPI1_CS0#
QSPI1_IO[3:0]
PIO[1] 0 - VDD_BYP V
AIO/LED[5:4, 2:0] 0 - 1.95 V
SYS_CTRL 0 - 4.6 V
1.2 V BT_RF 1.14 1.2 1.26 V
VDD_BT_RADIO
XTAL_IN
XTAL_OUT
1.1 V VDD_DIG 1.0 1.1 1.21 V
VDD_VKA
All ground / VSS pads - 0 - 0 V
a Minimum input voltage of 4.75 V is required for full specification. Li-ion charger operates at reduced specification from 3.78 V.
b Recommended software power-off threshold at 3.0 V. Device operates down to 2.8 V.

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QCC5121 WLCSP Data Sheet Electrical characteristics

15.3 Battery input pin specification

Battery specifications common to all regulators.

VBAT Min Typ Max Unit

Operating voltage 2.8 3.7 4.8 V

Software power-off threshold - 3 - V
Under voltage lockout rising threshold 2.47 2.6 2.73 V
Under voltage lockout hysteresis 20 - 70 mV
USB dead/weak battery rising threshold 3.14 3.3 3.46 V
USB dead/weak battery threshold 20 - 70 mV

15.4 Charger input pin specification

VCHG specifications common to all regulators.

VCHG Min Typ Max Unit

Operating voltage (full device specification) 4.75 5 6.5 V

Operating voltage (reduced charger specification) 3.78 5 6.5 V
VCHG_PRESENT rising threshold 3.42 3.6 3.78 V
VCHG_PRESENT hysteresis 20 - 70 mV
Full operating range VCHG_ - 6.5 V
PRESENT
On chip pull-down (disabled when VCHG_PRESENT = 1) 10 20 30 kΩ

15.5 Battery charger

Trickle charge mode Min Typ Max Unit

VPRE threshold (rising) 2.0 2.1 2.2 V

VPRE threshold (falling) 1.9 2.0 2.1 V
Trickle charge current: 1 - 50 mA
VCHG: 4.25 V to 6.5 V
VBAT: 0 V to 2.2 V
Full temperature range: -10°C to 125°C

Pre-charge mode Min Typ Max Unit

VFAST threshold (rising) 0 2.8 2.9 3.0 V

Configured by application software 1 2.9 3.0 3.1 V
2 3.0 3.1 3.2 V
3 2.4 2.5 2.6 V
VFAST threshold (falling) hysteresis 0.15 0.2 0.25 V

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QCC5121 WLCSP Data Sheet Electrical characteristics

Fast charge modes Min Typ Max Unit

Current step size - 100 - µA

Internal fast charge accuracy: 197 (-1.5%) 200 203 (+1.5%) mA
VCHG: 5 V
VBAT: 3.4 V
Temperature: 25°C
Internal fast charge accuracy: 194 (-3%) 200 206 (+3%) mA
VCHG: 4.75 V to 6.5 V
VBAT: 2 V to 4.2 V
VCHG-VBAT ≥ 0.55 V
Full temperature range: -10°C to 125°C
Internal fast charge accuracy (Low VCHG voltage) 100 (-50%) 200 206 (+3%) mA
VCHG: 4.4 V to 6.5 V
VBAT: 2 V to 4.2 V
VCHG-VBAT ≥ 0.15 V
Full temperature range: -10°C to 125°C

Fast charge mode Min Typ Max Unit

Battery Voltage 4.18 4.2 4.22 V

VCHG: 5 V (-0.5%) (+0.5%)
Temperature: 25°C
Battery Voltage 4.16 4.2 4.24 V
VCHG : VFLOAT+50 mV to 6.5 V (-1%) (+1%)
Full temperature range: -10°C to 125°C
Termination current 0 7 10 13 %
Termination accuracy as a percentage of fast 1 17 20 23 %
charge.
2 27 30 33 %
3 37 40 43 %

Standby mode Min Typ Max Unit

Voltage hysteresis on VBAT, VHYST, as a 0 0.006% 0.012% 0.018% %

percentage of VFLOAT
(75 mV @ (100 mV @ (125 mV @
4.2 V) 4.2 V) 4.2 V)
1 0.018% 0.24% 0.030% %
(125 mV @ (150 mV @ (175 mV @
4.2 V) 4.2 V) 4.2 V)
2 0.030% 0.036% 0.042% %
(175 mV @ (200 mV @ (225 mV @
4.2 V) 4.2 V) 4.2 V)
3 0.042% 0.048% 0.054% %
(225 mV @ (250 mV @ (275 mV @
4.2 V) 4.2 V) 4.2 V)

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QCC5121 WLCSP Data Sheet Electrical characteristics

Charger headroom error mode Min Typ Max Unit

Headroom error threshold (falling) - 100 - mV

Headroom error threshold (rising) - 170 - mV

Charger Vbat overvoltage mode Min Typ Max Unit

Overvoltage (rising) 4.65 4.7 4.75 V

Headroom error hysteresis - 100 - mV
Headroom error threshold (falling) 4.55 4.6 4.65 V

External charge mode Min Typ Max Unit

External fast charge current, IFAST 0.2 - 1.8 A

External pass device hfe 45 120 700 -
Sense voltage between VCHG and VCHG_SENSE 99 100 101 mV
RTRIM, ICTRL_AND_ TRIM applied (-1%) (+1%)
Full temperature range: -10°C to 125°C
External resistor software setting step size - 5 - mV
Typical external sense resistor values 1 A max 100.98 102 103.02 mΩ
(-1%) (+1%)
1.5 A max 67.32 68 68.68 mΩ
(-1%) (+1%)

15.6 Regulator enable

SYS_CTRL, switching threshold Min Typ Max Unit

Rising threshold - - 1.6 V

Falling threshold 0.4 - - V

15.7 Bypass LDO

Min Typ Max Unit

Input voltage VDD_BYP_BAT / VDD_BYP_CHG V

Output voltage, operating from VDD_BYP_CHG, >0.3 V 3.2 3.3 3.4 V
headroom
Output voltage, operating from VDD_BYP_BAT, >0.3 V 2.8 2.9 3 V
headroom
Pass device resistance when headroom <0.3 V - - 3 Ω
Maximum load current - - 100 mA
Current available for external use - - 50 mA
ULP modea
Output voltage, operating from VDD_BYP_CHG 3.1 3.3 3.5 V

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QCC5121 WLCSP Data Sheet Electrical characteristics

Min Typ Max Unit

Output voltage, operating from VDD_BYP_BAT 2.7 2.9 3.1 V

Maximum load current - - 1 mA
a ULP mode is automatically entered in Deep Sleep and Dormant modes, application software can disable automatic mode
switching.

15.8 1.8 V SMPS

1.8 V SMPS
Min Typ Max Unit

Input Supply SMPS_VCHG / SMPS_VBAT -

Output Voltage 1.7 1.8 1.9 V
Inductor value 3.06 4.7 5.6 µH
Inductor saturation current 0.8 - - A
Inductor ESR (10 kHz - 1 MHz) - - 290 mΩ
Bypass capacitor value 3.06 4.7 5.7 µF
Normal operation (PWM)
Load Current - - 350 mA
Current available for external use - - 100 mA
Peak conversion efficiency - 88 - %
Switching frequency 1.9 1.95 2.1 MHz
PFM mode
Load current - - 40 mA
Peak conversion efficiency - 88 - %
ULP mode
Load current - - 40 mA
Peak conversion efficiency - 88 - %

15.9 Digital SMPS

Digital SMPS
Min Typ Max Unit

Input Supply SMPS_VCHG / SMPS_VBAT -

Output Voltage (active) 1 1.1 1.2 V
Output Voltage (Deep Sleep) 0.8 0.85 0.95 V
Inductor value 3.06 4.7 5.6 µH
Inductor saturation current 0.3 - - A
Inductor ESR (10 kHz - 1 MHz) - - 290 mΩ
Bypass capacitor value 3.06 4.7 5.7 µF
Normal operation (PWM)

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QCC5121 WLCSP Data Sheet Electrical characteristics

Digital SMPS
Min Typ Max Unit

Load Current - - 150 mA

Peak conversion efficiency - 85 - %
Switching frequency 1.9 1.95 2.1 MHz
PFM mode
Load current - - 55 mA
Peak conversion efficiency - 85 - %
ULP mode
Load current - - 70 mA
Peak conversion efficiency - 85 - %

15.10 10‑bit auxiliary ADC

Min Typ Max Unit

Resolution - - 10 Bits
Input voltage rangea 0 - VDD_AUX_A V
DC
Accuracy (Guaranteed INL -2 - 2 LSB
monotonic)
DNL -1 - 1 LSB
Offset -1 - 1 LSB
Gain error -0.8 - 0.8 %
Input bandwidth - - 65 kHz
Conversion time 7.57 7.74 7.91 μs
Sample rateb - - 130K samples/sec
External source impedance - - 50 kΩ
External LED capacitance for < 0.5 LSB error 15 100 - nF
a LSB size = VDD_AUX_ADC/1023. VDD_AUX_ADC = 1.8 V typical ± 3%.
b This is the maximum sample rate allowed by the conversion time. The auxiliary ADC is shared between multiple functions.
Achievable sample rate depends on the specific application.

15.11 Digital terminals

Min Typ Max Unit

VDD_PADS supply 1.7 1.8 3.6 V

VIL input logic level low - - 0.22 x V
VDD_PADS
VIH input logic level high 0.7 x - - V
VDD_PADS
Drive current (configurable) 2, 4, 8, 12 4 - mA
VOL output logic level low, at max rated drive - - 0.22 x V
VDD_PADS

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QCC5121 WLCSP Data Sheet Electrical characteristics

Min Typ Max Unit

VOH output logic level high, at max rated drive 0.75 x - - V

VDD_PADS
Strong pull (up & down) 15 65 150 kΩ
Weak pull (up & down) 500 2200 5000 kΩ

15.12 LED driver pads

LED driver pads Min Typ Max Unit

Open drain current High impedance state - - 5 µA

Current sink state - - 50 mA
LED pad resistance V < 0.5 V - - 12 Ω
VIL input logic level low - - 0.4 V
VIH input logic level high 1.0 - - V

15.13 ESD protection

Test Pins Specification Class

Human Body Model AIO/LED[5:4, 2:0] AEC Q100-002 1B (1000 V)

All other pins AEC Q100-002 1C (2000 V)
Charge Device model All pins AEC Q100-011 C1 (300 V)
Product Level ESD USB_DN IEC 61000‑4‑2 (device level) Level 4 (8 kV
contact /
USB_DP
15 kV air)
AUDIO_MIC1_N/ LINEIN_L_N
AUDIO_MIC1_P/ LINEIN_L_P
AUDIO_MIC2_N/ LINEIN_R_N
AUDIO_MIC2_P/ LINEIN_R_P

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16 Audio performance

16.1 Digital-to-analog converters

Table 16-1 Class-D headset output driver or Class-AB line out

Parameter Conditions Min Typ Max Unit

Input Sample Width - - - 24 Bits

Input Sample Rate, Fsample - 8 - 96 kHz
Max Power 0 dBFS, 32 Ω, and 16 Ω load - - 30 mW
Load - 16 32 30k Ω
SNR fin = 1 kHz 95 98 - dBA
48 kHz
Fsample
B/W = 20 Hz → 24 kHz
A-Weighted
-1 dBFS
32 Ω / 16 Ω load
THD+N fin = 1 kHz - -85 -80 dB
48 kHz
B/W = 20 Hz → 24 kHz
0 dBFS
30 mW
THD+N fin = 6.3 kHz - - -75 dB
48 kHz
B/W = 20 Hz → 24 kHz
0 dBFS
30 mW
Digital gain Digital gain resolution = 1/32 -24 - 21.5 dB
Stereo separation (crosstalk) - 80 - - dB

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QCC5121 WLCSP Data Sheet Audio performance

16.2 Analog-to-digital converters

Table 16-2 High-quality audio input (HQADC)

Parameter Conditions Min Typ Max Unit

Output Sample Width - - - 24 Bits

Output Sample Rate, - 8 - 96 kHz
Fsample
Input level - - - 2.4 V pk-pk
Input impedance 0 dB to 24 dB analog gain - 20 - kΩ
27 dB to 39 dB analog gain - 10 - kΩ
SNR, single ended fin = 1 kHz 93 96 - dBA
48 kHz
B/W = 20 Hz → 24 kHz
A-Weighted
THD+N<0.1%
2.4 V pk-pk input (0 dB gain)
THD+N, single ended fin = 1 kHz - -85 -80 dB
48 kHz
B/W = 20 Hz → 24 kHz
2.4 V pk-pk input (0 dB gain)
Digital gain Digital gain resolution = 1/32 -24 - 21.5 dB
Analog gain 3 dB steps 0 - 39 dB
Stereo separation (crosstalk) - 80 - - dB

16.3 Microphone bias

Table 16-3 Microphone bias

Parameter Conditions Min Typ Max Unit

Output voltage (Tunable, - 1.5 - 2.1 V

step = 0.1 V)
Output current capability - 0.07 - 3.0 mA
Output noise B/W = 20 Hz → 20 kHz 4.5 5.1 7.4 uVrms
Unweighted
Crosstalk Between Using recommended - 80 - dB
Microphones application circuit

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17 Bluetooth performance

For QCC5121 WLCSP Bluetooth performance information, refer to QCC5121 WLCSP Bluetooth Performance
Specification.

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18 Power consumption

For QCC5121 WLCSP power consumption data, refer to relevant ADK release documentation.

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19 Environmental declaration statement for QTIL
semiconductor products

This declaration statement applies to QTIL products.

QTIL semiconductor products and packing materials meet the following substance restriction requirements, including
Table 19-1:
■ EU RoHS Directive 2011/65/EU1 maximum concentration values
■ EU REACH, Regulation (EC) No 1907/20061:
□ List of substances subject to authorization (Annex XIV)
□ Restrictions on the manufacture, placing on the market and use of certain dangerous substances,
preparations, and articles (Annex XVII)
■ POP regulation (EC) No 850/20041
■ EU Packaging and Packaging Waste, Directive 94/62/EC1
■ Montreal Protocol on substances that deplete the ozone layer
■ “California Prop 65”

Table 19-1 Restricted substances present in QTIL products

Amount
Found in products Substances CAS no. Applicable regulations
present, ppm

WLP packaged N-Methyl pyrrolidone 872-50-4 150-210 REACH SVHC, Prop 65

QTIL products contain less than 900 ppm of bromine or chlorine and less than 1500 ppm of bromine and chlorine
combined in each homogeneous material (“BrCl-free”).
For more information about QTIL responsible product design, including substances QTIL avoids, refer to the Product
®
Responsibility section of the Qualcomm website: http://www.qualcomm.com.

1 Applicable amendments as published in the EU Official Journal.

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20 Software development and tools

QTIL provides a Qualcomm® MultiCore Development Environment (QMDE), device firmware, and an example
application within an ADK. These support software development on QCC5121 WLCSP, enabling development of a
range of products including:
■ Stand-alone audio units such as mono and stereo headsets, mono and stereo speakers, and hearing aids.
■ Basic and gaming USB audio dongles.
■ Companion devices to application processors.

20.1 Qualcomm® MultiCore Development Environment

The QMDE provides features for building software and debugging it on the hardware. QMDE includes an editor and
tools to build, deploy, and debug applications. QMDE works with multiple ADKs as a single unified debugger.

20.2 Audio Development Kit

The ADK provides example applications including the Sink application. The Sink Application is a modifiable
reference software package implementation of an audio rendering device, supporting Bluetooth technologies. The
ADK also includes all the required software for programming and configuring the device.
For the complete ADK documentation set, visit CreatePoint at createpoint.qti.qualcomm.com.

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Document references

Document Reference, date

Core Specification of the Bluetooth System Bluetooth Specification

Version 5.0,
06 December 2016
Approved Packing Materials 80-32511-5
Environmental Declaration Statement for QTIL Semiconductor Products CS-00360035-ST
ESDA/JEDEC Joint Standard For Electrostatic Discharge Sensitivity Testing Human Body JS-001-201
Model (HBM) - Component Level ANSI/ESDA/JEDEC
Field-Induced Charged-Device Model Test Method for Electrostatic- Discharge- Withstand JESD22-C101E
Thresholds of Microelectronic Components
I²S Specification Revised: June 5, 1996.
Philips Semiconductors
IC Packing and Labelling Specification CS-00112584-SP
IEC 61000-4-2 Electromagnetic compatibility (EMC) – Part 4-2: Testing and measurement IEC 61000-4-2, Edition 2.0,
techniques – Electrostatic discharge immunity test 2008-12
IEEE 802.11 - Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) CS-00209818-ST
Specifications
QCC5121 WLCSP Bluetooth Performance Specification TBD
QCC5121 WLCSP Hardware Layout Guide Application Note TBD
Typical Solder Reflow Profile for Lead-free Devices Information Note CS-00116434-AN

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Glossary

Term Definition
ADC Analog-to-digital converter
ADK Audio development kit
AIO Analog input/output
Balun Balanced/unbalanced interface or device that changes a balanced output to an
unbalanced input or vice versa
Bluetooth Set of technologies providing audio and data transfer over short-range radio connections
CPU Central processing unit
DAC Digital-to-analog converter
DMA Direct memory access
DSP Digital signal processor
ESD Electrostatic discharge
HQ High quality
I/O Input/output
IC Integrated circuit
IDE Integrated development environment
IEC International Electrotechnical Commission
I²C Inter-integrated circuit interface
I²S Inter-integrated circuit sound
LDO Low (voltage) drop-out
LED Light-emitting diode
MCLK Audio master clock
MMU Memory management unit
NC Not connected
NSMD Nonsolder mask defined
OEM Original equipment manufacturer
OTP One-time programmable
PCB Printed circuit board
PCM Pulse code modulation
PIO Programmable input/output, also known as general-purpose I/O
PMU Power management unit
PWM Pulse width modulation
®
QMDE Qualcomm MultiCore Development Environment

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QCC5121 WLCSP Data Sheet Glossary

Term Definition
QSPI Quad serial peripheral interface (flash)
QTIL Qualcomm Technologies International, Ltd.
RAM Random access memory
RF Radio frequency
RISC Reduced instruction set computer
RoHS Restriction of Hazardous Substances in Electrical and Electronic Equipment Directive
(2002/95/ EC)
ROM Read only memory
SDR Single data rate
SMPS Switch-mode power supply
SNR Signal-to-noise ratio
SoC System on-chip
SPDIF Sony/Philips digital interface
SPI Serial peripheral interface
TCM Tightly coupled memory
THD+N Total harmonic distortion plus noise
UART Universal asynchronous receiver transmitter
USB Universal serial bus
USB-FS Full speed USB
XTAL Crystal

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MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION