SLCS132C − MARCH 1997 − REVISED MAY 1997

D Ultra-Fast Operation . . . 10 ns (typ) D AND PW PACKAGE

D Low Positive Supply Current (TOP VIEW)
12.7 mA (Typ)
D Operates From a Single 5-V Supply or From VCC+ 1 8 Q OUT
a Split ± 5-V Supply IN + 2 7 Q OUT
IN − 3 6 GND
D Complementary Outputs
VCC− LATCH ENABLE
4 5
D Input Common-Mode Voltage Includes
Negative Rail
D Low Offset Voltage
D No Minimum Slew Rate Requirement
symbol (each comparator)
D Output Latch Capability
D Functional Replacement to the LT1116 IN +
Q OUT
description IN − Q OUT

The TL3116 is an ultra-fast comparator designed

to interface directly to TTL logic while operating
from either a single 5-V power supply or dual POSITIVE SUPPLY CURRENT
± 5-V supplies. The input common-mode voltage vs
FREE-AIR TEMPERATURE

ÎÎÎÎÎ
extends to the negative rail for ground sensing
applications. It features extremely tight offset 15

ÎÎÎÎÎ
voltage and high gain for precision applications. It VCC = ± 5 V
14
has complementary outputs that can be latched
I CC − Positive Supply Current − mA

using the LATCH ENABLE terminal. Figure 1 13

shows the positive supply current of the
12
comparator. The TL3116 only requires 12.7 mA
(typical) to achieve a propagation delay of 10 ns. 11
The TL3116 is a pin-for-pin functional replace-
10
ment for the LT1116 comparator, offering
high-speed operation but consuming much less 9
power.
8

AVAILABLE OPTIONS 7
PACKAGED DEVICES
CHIP 6
SMALL
TA TSSOP FORM‡
OUTLINE† 5
(PW) (Y)
(D) −50 −25 0 25 50 75 100 125
0°C to 70°C TL3116CD TL3116CPWLE TL3116Y TA − Free-Air Temperature − °C

−40°C to 85°C TL3116ID TL3116IPWLE

— Figure 1
† The PW packages are available left-ended taped and reeled only.
‡ Chip forms are tested at TA = 25°C only.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

 
 
 ! "#$ !  %#&'" ($) Copyright  1997, Texas Instruments Incorporated
(#"! "  !%$""! %$ *$ $! 
$+! !#$!
!(( ,-) (#" %"$!!. ($!  $"$!!'- "'#($
$!.  '' %$$!)

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1



 


 
   

SLCS132C − MARCH 1997 − REVISED MAY 1997

TL3116Y chip information

This chip, when properly assembled, displays characteristics similar to the TL3116C. Thermal compression or
ultrasonic bonding may be used on the doped-aluminum bonding pads. Chips may be mounted with conductive
epoxy or a gold-silicon preform.

BONDING PAD ASSIGNMENTS

VCC+
(5) (1)
LATCH ENABLE
(1) (1) (8)
(1) (2) (8)
IN+ + Q OUT
(7) (3)
IN− − Q OUT
(7)
(2) (4)
(6)
VCC −
55 GND
(6)
CHIP THICKNESS: 10 MILS TYPICAL
(3) BONDING PADS: 4 × 4 MILS MINIMUM
(6)
TJ max = 150°C
TOLERANCES ARE ± 10%.
(4) (5) (6)
ALL DIMENSIONS ARE IN MILS.
TERMINALS 1 AND 6 CAN BE
63 CONNECTED TO MULTIPLE PADS.

COMPONENT COUNT
Bipolars 53
MOSFETs 49
Resistors 46
Capacitors 14

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265






 
   

SLCS132C − MARCH 1997 − REVISED MAY 1997

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 7 V to 7 V
Differential input voltage, VID (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage, VI (LATCH ENABLE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to network ground.
2. Differential voltages are at IN+ with respect to IN −.

DISSIPATION RATING TABLE

TA ≤ 25°C DERATING FACTOR TA = 70°C
PACKAGE
POWER RATING ABOVE TA = 25°C POWER RATING
D 725 mW 5.8 mW/°C 464 mW
PW 525 mW 4.2 mW/°C 336 mW

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3



 


 
   

SLCS132C − MARCH 1997 − REVISED MAY 1997

electrical characteristics at specified operating free-air temperature, VDD = ±5 V, VLE = 0 (unless

otherwise noted)
TL3116C TL3116I
PARAMETER TEST CONDITIONS† UNIT
MIN TYP‡ MAX MIN TYP‡ MAX
TA = 25°C 0.5 3 0.5 3
VIO Input offset voltage mV
TA = full range 3.5 3.5
Temperature coefficient
αVIO −2.5 −2.8 µV/°C
of input offset voltage
TA = 25°C 0.1 0.2 0.1 0.2
IIO Input offset current µA
A
TA = full range 0.3 0.35
TA = 25°C 0.7 1.1 0.7 1.1
IIB Input bias current µA
A
TA = full range 1.2 1.5
Common-mode input VDD = ± 5 V −5 2.5 −5 2.5
VICR V
voltage range VDD = 5 V 0 2.5 0 2.5
Common-mode rejection
CMRR − 5 ≤ VIC ≤ 2.5 V 75 100 75 100 dB
ratio
Positive supply: 4.6 V ≤ +VDD ≤ 5.4 V,
60 80 60 80
Supply-voltage rejection TA = 25°C
kSVR dB
ratio Negative supply: − 7 V ≤ −VDD ≤ − 2 V,
80 100 80 100
TA = 25°C
I(sink) = 4 mA, V+ ≤ 4.6 V,
400 600 400 600
TA = 25°C
VOL Low-level output voltage mV
I(sink) = 10 mA, V+ ≤ 4.6 V,
750 750
TA = 25°C
V+ ≤ 4.6 V, IO = 1 mA,
3.6 3.9 3.6 3.9
TA = 25°C
VOH High-level output voltage V
V+ ≤ 4.6 V, IO = 10 mA,
3.4 3.8 3.4 3.8
TA = 25°C
Positive supply current 12.7 14.7 12.7 15
ICC TA = full range mA
Negative supply current −2.6 −3
Low-level input voltage
VIL 0.8 0.8 V
(LATCH ENABLE)
High-level input voltage
VIH 2 2 V
(LATCH ENABLE)
Low-level input current VLE = 0 0 1 0 1 µA
IIL
(LATCH ENABLE) VLE = 2 V 24 39 24 45 µA
† Full range for the TL3116C is TA = 0°C to 70°C. Full range for the TL3116I is TA = − 40°C to 85°C.
‡ All typical values are measures with TA = 25°C.

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265






 
   

SLCS132C − MARCH 1997 − REVISED MAY 1997

switching characteristics, VDD = ±5 V, VLE = 0

TL3116C TL3116I
PARAMETER TEST CONDITIONS† UNIT
MIN TYP MAX MIN TYP MAX
∆VI = 100 mV, TA = 25°C 9.9 12 9.9 12
VOD = 5 mV TA = full range 9.9 14 9.9 15
tpd1 Propagation delay time‡ ns
∆VI = 100 mV, TA = 25°C 8.2 10.3 8.2 10.3
VOD = 20 mV TA = full range 8.2 12.7 8.2 13.7
∆VI = 100 mV, VOD = 5 mV,
tsk(p) Pulse skew (|tpd+ − tpd−|) 0.5 0.5 ns
TA = 25°C
tsu Setup time, LATCH ENABLE 3.4 3.4 ns
† Full range for the TL3116C is 0°C to 70°C. Full range for the TL3116I is − 40°C to 85°C.
‡ tpd1 cannot be measured in automatic handling equipment with low values of overdrive. The TL3116 is 100% tested with a 1-V step and 500-mV
overdrive at TA = 25°C only. Correlation tests have shown that tpd1 limits given can be ensured with this test, if additional dc tests are performed
to ensure that all internal bias conditions are correct. For low overdrive conditions, VOS is added to the overdrive.

TYPICAL CHARACTERISTICS

Table of Graphs
FIGURE
vs Input voltage 2
ICC Positive supply current vs Frequency 3
vs Free-air temperature 4
ICC Negative supply current vs Free-air temperature 5
vs Overdrive voltage 6
vs Supply voltage 7
tpd Propagation delay time vs Input impedance 8
vs Load capacitance 9
vs Free-air temperature 10
VIC Common-mode input voltage vs Free-air temperature 11
VIT Input threshold voltage (LATCH ENABLE) vs Free-air temperature 12
vs Output source current 13
VO Output voltage
vs Output sink current 14
II Input current (LATCH ENABLE) vs Input voltage 15

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5



 


 
   

SLCS132C − MARCH 1997 − REVISED MAY 1997

TYPICAL CHARACTERISTICS

POSITIVE SUPPLY CURRENT POSITIVE SUPPLY CURRENT

vs vs

ÎÎÎÎ ÎÎÎÎÎ
INPUT VOLTAGE FREQUENCY

ÎÎÎÎ ÎÎÎÎÎ
20 24
VCC = ± 5 V VCC = ± 5 V

ÎÎÎÎ ÎÎÎÎÎ
18 TA = 25°C TA = 25°C
22
I CC − Positive Supply Current − mA

I CC − Positive Supply Current − mA

16
20
14
TA = 85°C TA = 85°C
12 18
TA = 25°C
10 TA = 25°C
TA = − 40°C 16
8

6 14
TA = − 40°C
4
12
2

0 10
1 2 3 4 5 6 7 8 0 101 102
VI − Input Voltage − V f − Frequency − MHz
Figure 2 Figure 3

POSITIVE SUPPLY CURRENT NEGATIVE SUPPLY CURRENT

vs vs
FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE
15
ÎÎÎÎÎ 0
ÎÎÎÎ
ÎÎÎÎ
VCC = ± 5 V VCC = ± 5 V
14
I CC − Negative Supply Current − mA
I CC − Positive Supply Current − mA

− 0.5
13

12
−1
11

10 − 1.5

9
−2
8

7
− 2.5
6

5 −3
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TA − Free-Air Temperature − °C TA − Free-Air Temperature − °C
Figure 4 Figure 5

6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265






 
   

SLCS132C − MARCH 1997 − REVISED MAY 1997

TYPICAL CHARACTERISTICS

PROPAGATION DELAY TIME PROPAGATION DELAY TIME

vs vs

ÎÎÎÎÎ ÎÎÎÎÎ
OVERDRIVE VOLTAGE SUPPLY VOLTAGE

ÎÎÎÎÎ ÎÎÎÎÎ
12 12
VCC = ± 5 V VCC = ± 5 V

10
ÎÎÎÎÎ TA = 25°C
10 ÎÎÎÎÎ
TA = 25°C

t pd − Propagation Delay Time − ns

t pd − Propagation Delay Time − ns

8 8

6 6

4 4

2 2

0 0
0 10 20 30 40 50 4.4 4.6 4.8 5 5.2 5.4 5.6
Overdrive Voltage − mV VCC − Supply Voltage − V
Figure 6 Figure 7

PROPAGATION DELAY TIME PROPAGATION DELAY TIME

vs vs
INPUT IMPEDANCE LOAD CAPACITANCE
20 14

ÎÎÎÎÎ
Stepsize = 100 mV
18 VCC = ± 5 V

ÎÎÎÎÎ
12
t pd − Propagation Delay Time − ns

TA = 25°C tPDHL
t pd − Propagation Delay Time − ns

16
tPDLH
14 10

12 5 mV 8
10
20 mV 6
8

6 4
4
ÎÎÎÎÎ
ÎÎÎÎÎ
2 VCC = ± 5 V
2 TA = 25°C
0 0
0 50 100 150 200 250 300 0 10 20 30 40 50
ZI − Input Impedance − Ω CL − Load Capacitance − pF
Figure 8 Figure 9

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7



 


 
   

SLCS132C − MARCH 1997 − REVISED MAY 1997

TYPICAL CHARACTERISTICS

PROPAGATION DELAY TIME COMMON-MODE INPUT VOLTAGE

vs vs

ÎÎÎÎÎÎÎÎ
FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE

ÎÎÎÎÎ ÎÎÎÎÎÎÎÎ
25 6
VCC = ± 5 V VCC = 5 V (Upper Limit)

ÎÎÎÎÎÎÎÎ
VCC = ± 5 V (Upper Limit)

VIC − Common-Mode Input Voltage − V

t pd − Propagation Delay Time − ns

4
20

ÎÎÎÎÎÎÎ
15

ÎÎÎÎÎÎÎ
Rising Edge 0 VCC = 5 V (Lower Limit)

10
Falling Edge
−2

ÎÎÎÎÎÎÎÎ
5
−4

0
− 50 − 25 0 25 50 75 100 125
−6
− 50 − 25 0
ÎÎÎÎÎÎÎÎ
25
VCC = ± 5 V (Lower Limit)

50 75 100 125
TA − Free-Air Temperature − °C TA − Free-Air Temperature − °C
Figure 10 Figure 11

INPUT THRESHOLD VOLTAGE (LATCH ENABLE) OUTPUT VOLTAGE

vs vs
FREE-AIR TEMPERATURE OUTPUT SOURCE CURRENT

ÎÎÎÎ 5
ÎÎÎÎÎ
VIT − Input Threshold Voltage (LATCH ENABLE) − V

ÎÎÎÎ ÎÎÎÎÎ
VCC = ± 5 V VCC = ± 5 V
1.8 4.8
TA = 25°C
1.6 4.6
VO − Output Voltage − V

1.4 4.4
TA = 85°C TA = 25°C
1.2 4.2

1 4
TA = − 40°C
0.8 3.8

0.6 3.6

0.4 3.4

0.2 3.2

0 3
−50 −25 0 25 50 75 100 125 150 0 5 10 15 20
TA − Free-Air Temperature − °C IO(source) − Output Source Current − mA
Figure 12 Figure 13

8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265






 
   

SLCS132C − MARCH 1997 − REVISED MAY 1997

TYPICAL CHARACTERISTICS

OUTPUT VOLTAGE INPUT CURRENT (LATCH ENABLE)

vs vs

ÎÎÎÎÎ ÎÎÎÎÎ
OUTPUT SINK CURRENT INPUT VOLTAGE

ÎÎÎÎÎ ÎÎÎÎÎ
2 30
VCC = ± 5 V VCC = ± 5 V

ÎÎÎÎÎ ÎÎÎÎÎ
1.8 25
TA = 25°C TA = 25°C

I I − Input Current (LATCH ENABLE) − µ A

1.6 20
VO − Output Voltage − V

1.4 15

1.2 10

1 TA = 25°C 5
TA = − 40°C
0.8 0

0.6 TA = 85°C −5

0.4 − 10

0.2 − 15
0 − 20
0 5 10 15 20 − 0.5 0 0.5 1 1.5 2
IO(sink) − Output Sink Current − mA VI − Input Voltage − V
Figure 14 Figure 15

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9

 PACKAGE OPTION ADDENDUM

[Link] 17-Mar-2017

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

TL3116CD ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 3116C

& no Sb/Br)
TL3116CDG4 ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 3116C
& no Sb/Br)
TL3116CDR ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 3116C
& no Sb/Br)
TL3116CPW ACTIVE TSSOP PW 8 150 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 T3116
& no Sb/Br)
TL3116CPWR ACTIVE TSSOP PW 8 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 T3116
& no Sb/Br)
TL3116ID ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 3116I
& no Sb/Br)
TL3116IDG4 ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 3116I
& no Sb/Br)
TL3116IDR ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 3116I
& no Sb/Br)
TL3116IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 3116I
& no Sb/Br)
TL3116IPW ACTIVE TSSOP PW 8 150 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 Z3116
& no Sb/Br)
TL3116IPWR ACTIVE TSSOP PW 8 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 Z3116
& no Sb/Br)
TL3116IPWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 Z3116
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check [Link] for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

[Link] 17-Mar-2017

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

[Link] 29-Apr-2016

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TL3116CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TL3116CPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
TL3116IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TL3116IPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

[Link] 29-Apr-2016

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TL3116CDR SOIC D 8 2500 367.0 367.0 38.0
TL3116CPWR TSSOP PW 8 2000 367.0 367.0 35.0
TL3116IDR SOIC D 8 2500 367.0 367.0 38.0
TL3116IPWR TSSOP PW 8 2000 367.0 367.0 35.0

Pack Materials-Page 2
 PACKAGE OUTLINE
PW0008A SCALE 2.800
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

C
6.6 SEATING PLANE
TYP
6.2

A PIN 1 ID 0.1 C
AREA
6X 0.65
8
1

3.1 2X
2.9
NOTE 3 1.95

4
5
0.30
8X
0.19
4.5 1.2 MAX
B 0.1 C A B
4.3
NOTE 4

(0.15) TYP
SEE DETAIL A

0.25
GAGE PLANE

0.75 0.15
0 -8 0.05
0.50

DETAIL A
TYPICAL

4221848/A 02/2015

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153, variation AA.

[Link]
 EXAMPLE BOARD LAYOUT
PW0008A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

8X (1.5)
8X (0.45) SYMM
(R0.05)
1 TYP
8

SYMM

6X (0.65)
5
4

(5.8)

LAND PATTERN EXAMPLE

SCALE:10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL OPENING
OPENING SOLDER MASK

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

NOT TO SCALE

4221848/A 02/2015
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

[Link]
 EXAMPLE STENCIL DESIGN
PW0008A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

8X (1.5)
SYMM (R0.05) TYP
8X (0.45)
1
8

SYMM

6X (0.65)
5
4

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:10X

4221848/A 02/2015
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

[Link]
 IMPORTANT NOTICE

Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its
semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers
should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
TI’s published terms of sale for semiconductor products ([Link] apply to the sale of packaged integrated
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Reproduction of significant portions of TI information in TI data sheets is permissible only if reproduction is without alteration and is
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remain responsible for using their independent analysis, evaluation and judgment in designing their applications and that Designers have
full and exclusive responsibility to assure the safety of Designers' applications and compliance of their applications (and of all TI products
used in or for Designers’ applications) with all applicable regulations, laws and other applicable requirements. Designer represents that, with
respect to their applications, Designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerous
consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and
take appropriate actions. Designer agrees that prior to using or distributing any applications that include TI products, Designer will
thoroughly test such applications and the functionality of such TI products as used in such applications.
TI’s provision of technical, application or other design advice, quality characterization, reliability data or other services or information,
including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to
assist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in any
way, Designer (individually or, if Designer is acting on behalf of a company, Designer’s company) agrees to use any particular TI Resource
solely for this purpose and subject to the terms of this Notice.
TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI
products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections,
enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specifically
described in the published documentation for a particular TI Resource.
Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that
include the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE
TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY
RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or
endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR
REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO
ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL
PROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM,
INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF
PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL,
DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN
CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949
and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements.
Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such
products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards
and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must
ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in
life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use.
Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life
support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all
medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S.
TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).
Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications
and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory
requirements in connection with such selection.
Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s non-
compliance with the terms and provisions of this Notice.

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