CS222:

X86 ISA & Computer Arithmetic

Dr. A. Sahu
Dept of Comp. Sc. & Engg.
Indian Institute of Technology Guwahati

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 Outline
• CISC
– X86 ISA: Intel architectures history
• Computer Arithmetic
Arithmetic's:
s:
– Integer, Float, Double: ALU, FU‐IFU/SFU/DFU
• Binary
Bi representation
t ti
• Adder/Substractor
/
• Variation of Adder
 VAX instruction with 6 operands
addp6 op1,
op1 op2,
op2 op3,
op3 op4,
op4 op5,
op5 op6
⇒add two packed decimal numbers

op1, op2: length and start addr of number1

op3, op4: length and start addr of number2
op5 op6: length and start addr of sum
op5,
 Intel x86 history
Grown from 4 bit ⇒ 8 bit ⇒ 16 bit ⇒ 32 bit
• 1978: 8086 is announced (16 bit architecture)
• 1980: 8087 floating point coprocessor is added
• 1982: 80286 increases address space to 24 bits,
+instructions
• 1985: 80386 extends to 32 bits,
bits new addressing
modes
• 1989‐1995:
1989 1995: 80486, Pentium, Pentium Pro add a few
instr (designed for higher performance)
• 1997: MMX is added
 Comments on Intel x86
• “This history illustrates the impact of the
golden handcuffs of compatibility”
• “addingg new features as someone might g add
clothing to a packed bag”
• “an
an architecture that is difficult to explain and
impossible to love”
• “what
what the 80x86 lacks in style is made up in
quantity, making it beautiful from the right
perspective
perspective”
 Intel x86 features
• Complexity:
– Instructions
I t ti (~350)
( 350) from
f 1 to
t 17 bytes
b t long
l
– one operand must act as both a src and dst
– one operand can come from memory
– complex addressing modes, e.g., “base or scaled
index with 8 or 32 bit displacement
displacement”
– Permitted instruction ‐ address mode
combinations irregular (lots of special cases, hard
to learn!)
– Effect by each instruction on condition codes is
somewhat complex,
complex irregular
 Intel x86 features – contd.
• Saving grace:
– the most frequently used instructions are
not too difficult to build
– compilers avoid the portions of the
architecture that are slow

• LLarrabee:
b A ManyM Core
C x86
86 Architecture
A hi
for Visual Computing (Craped in 2010)
Bus Interface
C BUS
Unit
SUM Q6
Q5
Q4
Q3
Q2
Q1

CS (Code Seg Reg)

DS (Data Seg Reg )
ES (Extra Seg Reg )
SS (Stack Seg Reg)
IP (Intr
(
Operand
Ptr))
InDirect
Sequencer
Execution
A BUS
Unit
AH AL Temp A
BH BL Temp B
CH CL Temp C
DH DL
SI (Source Idx )
DI (Dest
(
(Dest. Idx))
BP (Base Ptr ) ALU
SP (Stack Ptr)
Z (Flag Reg)
• AX ‐ the accumulator register (divided into AH / AL) AH AL
• BX ‐ the base address register (divided into BH / BL) BH BL
• CX ‐ the count register (divided into CH / CL) CH CL
DH DL
• DX ‐ the data register (divided into DH / DL)
SI (Source Idx )
DI (Dest. Idx)
• SI ‐ source index register. BP (Base Ptr )
• DI ‐ d i i iindex
destination d register.
i SP (St
(Stackk Pt
Ptr))
• BP ‐ base pointer. Z (Flag Reg)
• SP ‐ stack pointer.
CS (Code Seg Reg)
DS (Data Seg Reg )
ES (Extra Seg Reg )
SS (Stack Seg Reg)

IP (Intr Ptr)
31 15 7 0
EAX AH AL
EBX BH BL
ECX CH CL
EDX DH DL
ESI SI (Source Idx )
EDI DI (Dest. Idx)
Extended
EBP BP (Base Ptr )
ESP SP (St
(Stackk Pt
Ptr))
EZ Z (Flag Reg)
ECS CS (Code Seg Reg)
EDS DS (Data Seg Reg )
EES ES (Extra Seg Reg )
ESS SS (Stack Seg Reg)

EIP IP (Intr Ptr)

• 1978: 8086 (16 bit architecture)
• 1980: 8087
• Floating point coprocessor is added
• 1982: 80286
• Increases address space to 24 bits
• 1985: 80386:
• 32 bits Add,
• Virtual Mem & new add modes
• Protected mode (OS support)
• 1989-95: 80486/Pentium/Pro
• Added a few instructions of base MMX
• 1997: Pentium II
• 57 new “MMX” instructions are added,

• 1999: Pentium III:

• Out of Order, added another 70 Streaming SIMD Ext (SSE)

• 2001: Pentium 4
• Net burst, another 144 instructions (SSE2)

• 2003: PI4 HT
HT, Trace Cache
• 2005: Centrino, low power
• 2007:
2007 CCore architecture,
hit t D
Duo
• 2008: Atom, Quad core with HT….
• 2009---:Multi core (Large chip multiprocessor)
 Intel x86 : peculiar feature
Upto 3 “prefixes” for an instruction
• Override default data size
• Override default segment register
• Lock bus for a semaphore
• Repeat
R t the
th ffollowing
ll i iinstruction
t ti
• Override default address size
 RISC /CISC Contribution
• PowerPC : RISC with powerful branch
instructions
• SPARC : RISC with register windows
• VAX : CISC with addressing modes orthogonal
to opcodes
d
• Intel X86 : CISC with code compatibility over
several generations
 Computer Arithmetic:
C ÎAssembly
Î Î Machine
• C : short,
short int,
int long,
long float,
float double
• 16 bit, 32 bit, 32 bit, 32 bit, 64 bit
• Si d/
Signed/Unsigned
i d
• Have a FU in your processor
– Processor is capable to do it in hardware
– 8086: No support of FP, 8087 FP Co processor
• If you don’t have FPU : Write FP in software
– $gcc –mfloat‐soft
mfloat soft –SS test.c
test c
– undefined reference to `__mulsf3' 15
 Representation
• Int’s are not Integers, Float’s are not Reals
• Int : 8, 16, 32, 64 bit (char, short, int, long)
• Real
– Fixed point: N bit Int part . M for real part
(Software Emul)
• User defiened
– Floating point: 32,64 (float‐SingleFP/double‐
doubleFP)
• IEEE 754 format

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 Basic Units of Computer

Data
Instruction
PC Memory Reg#
Register Address
Address
Instruction Reg# FILE
ALU Data
Reg# Memory
Data

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 ALU: Arithmetic and Logic Unit
• Binary arithmetic and ALU design
• Signed operations, overflow
A
• Compare/Shift
R l
Result
• Multiplier design
• Divider design B ALU

• Speeding up addition/subtraction
• Floating point representation
and operations Operation
• Floating point unit design

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