Transmission Gate-Based 9T SRAM Cell MJ20-A07

CHAPTER -1
INTRODUCTION TO PROJECT

1.1 OBJECTIVE

This cell consists of 9 transistors - 6 NMOS (n-type Metal-Oxide-Semiconductor) transistors

and 3 PMOS (p-type Metal-Oxide-Semiconductor) transistors. The core components are cross-
coupled inverters (M1-M4) and access transistors (M5-M9). The cross-coupled inverters, formed by
M1/M2 and M3/M4, store the data. Access transistors M5-M8 connect the inverters to bitlines (BL
and BLB) for read and write operations, with M9 specifically used for writing.

During a read operation, the wordline (WL) is activated, connecting the inverters to the bitlines.
The state of the cell is then determined by sensing the voltage on BL and BLB, with one pulled high
(logic '1') and the other low (logic '0') based on the stored data. For a write operation, the bitlines
are precharged, and the write data is applied along with the WL activation. Depending on the data
and current state, one inverter is reinforced to write the new data. M9 allows forcing a specific state
into the cell.

Advantages of this 9T SRAM cell include improved stability, as the additional transistors reduce
data loss risks, and reduced leakage current due to better isolation of storage nodes. However, there
are trade-offs such as increased area requirement and complexity compared to 6T SRAM cells.
These factors make the 9T SRAM cell suitable for applications where stability, low leakage, and
data integrity are critical, such as low-power designs or applications sensitive to data loss

1.2 INTRODUCTION

With the explosive growth and increasing reach, and influence of interconnecting devices in
everyday lives, the expeditious development of internet market, under the umbrella of ‘internet of
things’ (IoT), brings about connection and data exchange between existing devices mainly through
wireless sensor networks. Its applications range extends from environmental monitoring, biomedical
sensing, smart home appliances, intelligent transportation, remote surveillance etc., with millions of
devices accessing and communicating data according to their requirements. For supporting their

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wide and complex span of operations and capabilities with stringent accuracy requirements and
consequent large memory demand for storing data and instructions, variation resilient and low power
large embedded memory, consisting mainly of static random-access memory (SRAM), are required.
These memories must cater to high standards of reliability and energy efficiency while dealing with
the copious amounts of data and for maintaining longer battery life. Therefore, the robustness of
SRAM memory systems against process, voltage and temperature (PVT) variations and power
efficiency (dynamic as well as static) are two of the principle design constraints.

1.3 PROBLEM STATEMENT

To address the need for improved stability and reduced leakage current in SRAM cells, a 9T
SRAM cell based on transmission gates offers a promising solution. This design comprises 9
transistors, including 6 NMOS and 3 PMOS transistors, arranged to create cross-coupled inverters
(M1-M4) and access transistors (M5-M9). The cross-coupled inverters, formed by M1/M2 and
M3/M4, serve as the storage elements for data.

During a read operation, activating the wordline (WL) connects the inverters to the bitlines (BL
and BLB). The state of the cell is then determined by sensing the voltages on BL and BLB, with one
bitline pulled high (logic '1') and the other low (logic '0') based on the stored data. For a write
operation, the bitlines are precharged to a specified voltage level, and the write data is applied along
with WL activation. Depending on the data and the current state of the cell, one of the inverters is
reinforced to write the new data. Transistor M9 allows for forcing a specific state (0 or 1) into the
cell during write operations.

This 9T SRAM cell design offers several advantages over traditional 6T SRAM cells. Firstly, it
provides improved stability by reducing the risks of data loss due to disturbances. Additionally, the
design minimizes leakage current by effectively isolating the storage nodes. However, it is essential
to balance these benefits with considerations of area and complexity. The additional transistors do
increase the area requirement, and the design becomes more complex compared to 6T SRAM cells.
Nevertheless, the advantages in stability and reduced leakage current make this 9T SRAM cell
particularly suitable for applications where these factors are critical, such as low-power designs or
applications sensitive to data integrity.

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In summary, this 9T SRAM cell design based on transmission gates presents a balanced
approach to improving stability and reducing leakage current in SRAM technology. Its operation
during read and write operations, along with its advantages over traditional 6T SRAM cells, makes
it a promising choice for various applications where data integrity and low power consumption are
paramount.

1.4 EXISTING SYSTEM

INTRODUCTION

IoT connects devices for seamless data exchange, transforming everyday objects into smart
entities. Its rapid growth enhances efficiency and monitoring across various sectors, shaping modern
societies and economies. IoT applications include environmental monitoring, biomedical sensing,
smart home appliances, and more. Millions of devices communicate data, requiring low-power,
variation-resilient large embedded memory like static random-access memory (SRAM) to meet their
operational needs and accuracy requirements. IoT demands robust, low-power embedded memory,
mainly SRAM, to meet accuracy and energy efficiency standards. These systems must handle large
data volumes, ensuring resilience against process, voltage, and temperature variations for prolonged
battery life.

Figure 1.4.1: Schematic of SE10T SRAM cell.

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In the proposed design's write operation, WBL is configured to VDD or GND based on the
data to be written, and WWL is pulled-up to initiate the write cycle. RWL is set to GND to disable
the read path. Depending on whether '1' or '0' is being written, WWLA/WWLB is set to VDD or
GND, respectively. When writing '1' to Q, WBL is set to GND, transferring the desired data from
WBL to QB through the activation of various transistors. Writing '0' to Q involves setting WBL to
VDD, and both WWLA and WWLB are pulled down to cut power from QB. QB is then charged
through WBL-M9, activating specific transistors to discharge Q to ground, effectively writing '0' to
the memory cell.

Figure 1.4.2: Simulation of SE10 SRAM cell.

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Figure 1.4.3: Simulation results of SE10 SRAM cell.

1.5 PROPOSED SYSTEM

The proposed TG9T shown in Fig & Table gives the different control signals for different
operations. During the read operation, one of the bit lines is discharged depending on the data in the
storage nodes, Q and QB. During the write operation, due to the removal of the feedback path, the
cell can write the desired data successfully. In the hold mode, all the access transistors are maintained
in OFF condition while the bit line bar (BLB) and bit line (BL) are set at VDD.

Figure 1.5.1 Proposed 9T schematic.

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International Technology Roadmap for Semiconductors (ITRS) forecasts the fundamental

technical requirements and lays down near and long-term goals for the semiconductor industry.
ITRS predicts variations in device parameters such as channel width (W), channel length (L),

channel doping concentration (NDEP), threshold voltage (Vt), oxide thickness (tOX), and supply
voltage (VDD) at least up to a range of ±10%. For higher accuracy of results, we have performed
Monte–Carlo simulations (with 5000 samples) by varying the aforementioned device/process and
environmental parameters and generating different SPICE model files at 16-nm technology for each
set of parameters utilising the predictive technology model (PTM). The varied device/ process

parameters including W, L, NDEP, Vt, and tOX are assumed to have independent Gaussian
distributions with a 3σ variation of 10%, for evaluation of salient design metrics such as read current
(IREAD), leakage current (ILEAK), read access time (TRA or read delay), write access time (TWA or
write delay), RSNM, WSNM and hold power (HPOWER).

1.6 SYSTEM ARCHITECTURE

Cell: The core memory unit consists of nine transistors. Six transistors form a basic latch design to
store data as a binary state (0 or 1). Three additional transistors act as transmission gates, controlling
the read and write operations to the cell.

Bit lines: Two bit lines carry data and its complement (inverse) during read and write operations.

Word line: A word line controls access to the cell by activating the transmission gates.

Read: When the word line is activated, the appropriate transmission gate connects the bit line to the
latch. The stored voltage level on the bit line is read.

Write: Activating the wordline and applying the desired data voltage and its complement to the
bitlines allows the transmission gates to overwrite the data in the latch.

1.7 REQUIREMENTS
MENTOR GRAPHICS SOFTWARE

Tanner EDA is a suite of tools for the design of integrated circuits. These tools allow you to
enter schematics, perform SPICE simulations, do physical design (i.e., chip layout), and perform
design rule checks (DRC) and layout versus schematic (LVS) checks. 3 tools are used for this

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process: S-edit – a schematic capture tool T-SPICE – the SPICE simulation engine integrated with
S-edit L-edit – the physical design tool Using S-Edit (Schematic Entry Tool) & T-SPICE (Analog
Simulation Tool).

1.7.1 START NEW DESIGN & SETUP LIBRARIES

1.New design and setup libraries

Figure 1.7.1.1: Start of new design and setup libraries.

2. SPICE Models

Figure 1.7.1.2: Setup of SPICE models.

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3. Selecting DC sweep analysis

Figure 1.7.1.3: Selecting DC sweep analysis.

4. Setup properties of transistor

Figure 1.7.1.4: Setup properties of transistor.

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5. Schematic diagram of the transistor

Figure 1.7.1.5: Schematic diagram of the transistor.

6. Power supply and ground

Figure 1.7.1.6: Connect the power supply and set the ground.

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7. DC Analysis

Figure 1.7.1.7: Set the DC Analysis.

8. Export SPICE

Figure 1.7.1.8: Export SPICE netlist.

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9. Symbolic view of inverter

Figure 1.7.1.9: Symbolic view of inverter.

10. Output and Waveforms

Figure 1.7.1.10: Output waveforms of inverter.

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Transmission Gate-Based 9T SRAM Cell MJ20-A07

CHAPTER - 2
LITERATURE SURVEY OF THE PROJECT WORK

2.1 OPTIMIZING SRAM BIT CELL RELIABILITY AND ENERGY FOR IOT
APPLICATIONS

With the continuously changing electronic market, specifications and design requirements
for different applications vary widely. For example, for the Internet of Things (IoTs) and Body
Sensor Nodes (BSNs), robustness and energy efficiency are the most important design constraints;
while for general purpose and graphics (GPU) processors, servers, and other high-end applications,
energy is traded off for higher performance. Generally, IoT devices need to operate in the range of
few KHz to a few MHz depending on the application, but energy is an important concern in all of
these applications. The authors in show the Static Random Access Memory (SRAM) as the major
contributor to the power dissipation of the digital design in UltraLow Power (ULP) Systems-on-
Chip (SoCs). In addition, the need for larger embedded memories (mainly SRAM) is increasing in
highly integrated SoCs to support a wide range of capabilities, thus further tightening the design
constraints on power, performance, and energy. VDD scaling to the sub-threshold region minimizes
the total energy consumption. With VDD scaling, the contribution of the active energy and the
leakage energy to the total energy changes. The active energy (CVDD 2) dominates at higher
voltages, while leakage energy (VDD*ILeak) dominates at sub-threshold voltages.

Thus, an optimal VDD exists that minimizes the total energy of a design, and usually that
VDD lies in the sub-threshold region. Since this optimum point changes for different performance
needs and designs, it is important to explore the design space while varying different knobs to
determine the optimal voltage that minimizes the energy consumption of the design for each
application. In this paper, we explore the design space of SRAM considering the threshold voltage
of its transistors as one of the important design knobs needed to achieve a robust and energy efficient
memory for IoT applications.

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2.2 A 32 KB 10T SUB-THRESHOLD SRAM ARRAY WITH BIT-

INTERLEAVING AND DIFFERENTIAL READ SCHEME IN 90 NM CMOS

Portable applications such as implantable medical devices and wireless sensor networks
require ultra-low power dissipation. Many researchers have explored digital subthreshold logic,as a
possible option to deliver this requirement. The low voltage operation (below 400 mV) of such
designs has been successfully demonstrated in real silicon measurements . However, operating
memory circuits at such a low voltage is more challenging since SRAM yield degrades considerably
at these low voltages. In the subthreshold region, conventional 6T SRAM experiences poor read
stability or weak write ability . Since the read stability and the writability have conflicting design
requirements, it is extremely difficult to operate the 6T SRAM in the subthreshold region. To
overcome this problem, researchers have considered different configuration for SRAM cells. This
technique can mitigate the subthreshold leakage noise current from bit line. Nonetheless, other
leakage components (e.g., junction leakage) still degrade the bit line swing significantly, incurring
functional failures during read access. A virtual ground scheme has been proposed to utilize the
small bit line swing more efficiently. However, the raised virtual ground also reduces the sense
margin of the following inverter buffer and hence, this scheme may not improve the sense margin
effectively.

2.3 A SINGLE-ENDED DISTURB-FREE 9T SUBTHRESHOLD SRAM WITH

CROSS-POINT DATA-AWARE WRITE WORD-LINE STRUCTURE,
NEGATIVE BIT-LINE, AND ADAPTIVE READ OPERATION TIMING
TRACING

Recently, the demand for ultra-low power dissipation battery-operated devices is increasing.
If the performance at low supply voltage (Vdd) can still meet the system requirements, the system
power dissipation can be reduced significantly by scaling down the supply voltage. Fig. 1 shows the
measured oscillation frequency, power dissipation and energy per oscillation of a 399-stage NAND-
type ring oscillator using 65 nm low leakage CMOS process with threshold voltage (Vdd) around
0.5 V. The total power and leakage power decrease drastically with scaling, and leakage power
dominates the total power in deep subthreshold region even in low leakage process. Total Energy
per oscillation decreases first with scaling.

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SRAM is a critical component in memory rich SoC today. The conventional 6T SRAM cell
achieves large storage capability with simple structure, yet suffers from Read disturb, Half Select
disturb, and the conflicting Read/Write requirements . As such, the stability of 6T SRAM degrades
significantly with Vdd scaling, and its dictates the overall system power supply and hence power
consumption.

2.4 A 256-KB 65-NM SUB-THRESHOLD SRAM DESIGN FOR ULTRA-LOW-

VOLTAGE OPERATION

The subthreshold digital circuit design has emerged as a low-energy solution for applications
with strict energy constraints. Analysis of sub-threshold designs has focused on logic circuits.
SRAMs comprise a significant percentage of the total area and total power for many digital chips .
SRAM leakage can dominate total chip leakage, and switching highly capacitive bit lines and word
lines is costly in terms of energy. Lowering for SRAM saves leakage power and access energy. Also,
for system integration, SRAM must become capable of operating at sub-threshold voltages that are
compatible with sub-threshold combinational logic. Overcoming the difficulties of operating an
SRAM in sub-threshold requires both circuit and architectural innovations. The benefits are
significant, however, since low-energy SRAM is essential for enabling ultra-low-energy systems.
This paper describes an SRAM capable of operating in the sub-threshold region.

Previous low-power memories show a trend of lower voltage operation. Exploiting dynamic
voltage scaling (DVS) for SRAM is one motivation for designing a voltage-scalable memory. A
0.18- m 32-kB four-way associative cache offers DVS compatibility from 120 MHz, 1.7 mW at 0.65
V to 1.04 GHz, 530 mW at 2 V. Although DVS can provide power reduction for active memories,
most previous approaches apply voltage scaling primarily to idle blocks by lowering VDD.
Implementations of SRAM using lower in standby are available along with software policies to
determine when to enter the lower leakage mode. Voltage scaling for SRAM promises to continue,
leading to sub-threshold storage modes and even sub-threshold operation for SRAMs operating in
tandem with sub-threshold logic.

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2.5 STATIC NOISE MARGIN VARIATION FOR SUB-THRESHOLD SRAM

IN 65-NM CMOS

Sub-Threshold digital circuit design has emerged as a low energy solution for applications
with strict energy constraints. Analysis of sub-threshold designs has focused on logic circuits .
SRAMs comprise a significant percentage of the total area for many digital chips as well as the total
power . For this reason, SRAM leakage can dominate the total leakage of the chip, and large
switched capacitances in the bit lines and word lines make SRAM accesses costly in terms of energy.
Pushing SRAM operation into the sub-threshold region reduces both leakage power and access
energy. Also, for system integration, SRAM must become capable of operating at sub-threshold
voltages that are compatible with sub-threshold combinational logic. Recent low power memories
show a trend of lower voltages with some designs holding state on the edge of the sub-threshold
region . This scaling promises to continue, leading to sub-threshold storage modes and even sub-
threshold operation for SRAMs operating in tandem with sub-threshold logic.

When the bit cell is holding data, its word line is low so the nMOS access transistors are off.
In order to hold its data properly, the back-to-back inverters must maintain bi-stable operating points.
The best measure of the ability of these inverters to maintain their state is the bitcell’s static noise
margin (SNM). The SNM is the maximum amount of voltage noise that can be introduced at the
outputs of the two inverters such that the cell retains its data. SNM quantifies the amount of voltage
noise required at the internal nodes of a bit cell to flip the cell’s contents.

Although the SNM is certainly important during hold, cell stability during active operation
represents a more significant limitation to SRAM operation. Specifically, at the onset of a read
access, the word line is and the bit lines are still pre charged. The internal node of the bit cell that
represents a zero gets pulled upward through the access transistor due to the voltage dividing effect
across the access transistor and drive transistor . This increase in voltage severely degrades the SNM
during the read operation (read SNM). shows example butterfly curves during hold and read that
illustrate the degradation in SNM during read.

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2.6 A 130 MV SRAM WITH EXPANDED WRITE AND READ MARGINS FOR
SUBTHRESHOLD APPLICATIONS

USING ultra-low supply voltage (VDD) enables suppressing power consumption, gate
leakage, and standby current of a chip to lengthen battery life time for low-power mobile devices .
Some energy-harvesting-based systems generate low supply voltages. Researchers have considered
subthreshold operation as one of the promising low-power approaches for non-high-speed ultra-
low-VDD chips. Due to increasing threshold voltage fluctuations caused by global and local process
variations, on-chip nanometre SRAMs suffer from instability in write and read operations at a lower
supply voltage.

7T cell achieves read-static-noise-margin-free by cutting off a pull-down path during read

operations, but has limited write capability due to single-end write operations. A read-decoupled
(RD) 8T cell, which isolates its read-port from the storage node, is a popular solution for many low-
VDD chips because of its superior read stability. However, RD-8T cells do not significantly increase
the write margin (WM), and still suffer from half-select stability failure during a write operation.
Divided word line schemes prevent disturbance at half-select cells, but do not solve write failures.
Thus, the RD-8T cell can only achieve 0.26 V–0.45 V VDDmin.

This paper proposes a 9T cell to achieve deep subthreshold operation using a data-aware-
feedback-cutoff (DAFC) scheme to enlarge the write margin and dynamic-read-decoupled (DRD)
schemes to prevent read-disturb. The cell area for the near-threshold and subthreshold applications
are 1.64x and 1.8x of the conventional 6T SRAM cell. Fabricated 90 nm 9T 32 Kb macros confirm
that the 9T macro can achieve 130 mV VDDmin. To our knowledge, this work achieves the lowest
VDDmin compared to reported SRAM designs.

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2.7 A STABLE 2-PORT SRAM CELL DESIGN AGAINST SIMULTANEOUSLY

READ/WRITE-DISTURBED ACCESSES
MANY discussions have been held about the stability for an SRAM cell in recent years
against the reduction in the cell-operating margin due to the device fluctuation with scaling after 65-
nm technology node. The useful assist techniques were reported so far to improve the cell-operating
margins, such as the new cell topology and the cell-bias control . However, those discussions were
mainly based on the assist technique for a 1-port SRAM cell which is independently read or write
accessed at a time.

As for a 2-port SRAM which is widely used for an interface between the macro-blocks in
SoC, a simultaneous R/W access has to be guaranteed with keeping enough Icell even though it is
accessed in a same column. This guarantee obligation makes it much more difficult for a 2-port cell
design compared with that of a 1-port cell to realize a simultaneous static noise margin (SNM),
WRTM and Icell.

In this paper, a further consideration was newly demonstrated about the stability for a 2-port
SRAM under the random fluctuation of Vth in 65-nm CMOS technology. The cell-operating margins
under 4- random-Vth fluctuation that corresponds to a 32-Kbit memory capacitance were verified.
And their tolerance against 6- random-Vth fluctuation was also estimated. Moreover, we have
challenged to apply the proposed biasing to a 7T 2-port cell design for area saving with a unique
write-assist scheme. The proposed biasing scheme was implemented in a 32-Kbit 2-port SRAM with
a 65-nm LSTP CMOS, and it demonstrated that:

1) the minimum Icell at a simultaneously R/W-disturbed cell was increased by 2.4 times
while improving WRTM, and thereby the cell size based on the same Icell was reduced by
20%,

2) the minimum SNM at a half-selected cell was improved by 44%, and

3) the proposed 7T 2-port cell saved the cell size by 26% without any decrease in cell current,
each compared with the conventional VDDM control technique under 4- random-Vth
fluctuation at Vdd . Each operating margin also had the tolerance against the 6- random-Vth
fluctuation

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2.8 A LOW-POWER SRAM USING HIERARCHICAL BIT LINE AND

LOCAL SENSE AMPLIFIERS

Due to the high demands on the portable products, power consumption is a major concern in
VLSI chip designs. Especially, the low power static random access memory (SRAM) becomes more
important because the number of memory cells and the bit width continue to be larger. Several
techniques have been proposed to reduce the power consumption of SRAMS. The read power is
reduced by limiting the swing voltages of bit lines and data bus to small voltages during read cycles.
However, the SRAM consumes much larger power during write cycles than read cycles due to the
full swing property in the bit lines and data bus during write cycles. The write swing voltage in data
bus is also reduced by the low swing data bus technique . The low swing signals in data bus are
created by a pulse and then amplified by write amplifiers in a selected block.

These low swing writing techniques significantly reduce the write power consumption in bit
lines. However, they need extra logics in each local row decoder and some dc–dc voltage converters
to precharge or discharge the bit lines. Kanda’s technique also uses seven transistors instead of six
transistors for memory cells. These techniques incur area overhead and speed degradation.
Moreover, the low swing write techniques decrease the noise margins of memory cells because their
memory cells act as sense amplifiers for the write operation. a low-power SRAM using hierarchical
bit line and local sense amplifiers (HBLSA-SRAM) is proposed to reduce the write power
consumption in bit lines without the noise margin degradation. The HBLSA-SRAM saves the write
power by reducing the swing voltage of bit lines and data bus. It utilizes the low swing data bus
technique to reduce the swing voltage of data bus during both read and write cycles. To save the
write power in bit lines, it uses a new hierarchical bit line and local sense amplifiers which reduce
the effective bit line capacitance and the write swing voltage of bit lines. The hierarchical bit line
consists of a bit line and several sub-bit lines.

A bit line write driver generates a low swing signal in the bit line and a selected sub-bit line.
After the selected sub-bit line is disconnected from the bit line, the local sense amplifier amplifies
the low swing signal to the full swing signal. To write data in memory cells, the full swing signal is
used only in the low capacitive sub-bit line whereas the low swing signal is used in the high
capacitive bit line. Therefore, the HBLSA-SRAM not only saves the write power but also does not

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decrease the noise margin. Moreover, its area overhead is smaller than the previous low swing write
techniques.

2.9 A SUB-600-MV, FLUCTUATION TOLERANT 65-NM CMOS SRAM

ARRAY WITH DYNAMIC CELL BIASING
Random threshold voltage variations between neighbouring, small geometry SRAM cell
transistors due to dopant fluctuations , line edge roughness and poly gate grain size variations have
been shown to significantly reduce the DC Read, Write and Retention Margins of CMOS SRAM
cells . These random local variations have also been shown to be influenced by systematic across
chip, wafer and lot variations. Systematic variations of MOSFET channel length across chip, wafer
and lot modulate the local variations by degrading short channel behaviour of cell transistors,
skewing the cell transistor distributions to take on a voltage-dependent and asymmetric form .
Several cell terminal biasing schemes have been reported to improve Read and/or Write
Margins using:

1) dual static supplies

2) a single dynamic cell supply

3) dual dynamic cell supplies

These impact the improvements in Read/Write margin fluctuation of each biasing scheme
uniquely, given the unique combinations of voltages across each cell transistor that each scheme
produces. Several combinations of these techniques are implemented in 65-nm PDSOI hardware.
Section VI discusses hardware measurements of and performance of these experiments.

2.10 A HIGHLY-STABLE NANO METER MEMORY FOR LOW-POWER

DESIGN

As the era of nanoscale devices is becoming a reality, many features of such small devices
(inclusive of performance) are starting to deteriorate: leakage had sincreased, gain has decreased,
and sensitivity to unavoidable small fluctuations in the manufacturing process has dramatically
risen. Power and energy have become the key limitations on many new designs. With the advent of
microprocessors and systems on chips (SoCs), the design of power efficient SRAM structures has

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become highly desirable. One of the most effective approaches to meet this objective is to design
SRAM cells whose operation is ultra-low power. A decrease in supply voltage reduces quadratically
the dynamic power and linearly to the first order leakage power. However, with an aggressive scaling
in technology, substantial problems have already been encountered when the conventional six
transistors (6T) SRAM cell configuration is utilized at an ultra-low power supply; this cell shows
poor stability at very small feature sizes. Moreover, the read static noise margin is small for robust
operation at a feature size of 32nm. SRAM cell configurations with more than 6 transistors to reduce
leakage power and improve stability have been proposed.

Transistor sizing of the 9T SRAM cell for high data stability and good write-ability is first
investigated. Then, an innovative pre charging and bit line balancing scheme for the write operation
in the 9T SRAM cell is also proposed for maximum static power saving in an SRAM array Finally,
the impact of process, voltage, and temperature (PVT) variations on the cell’s power delay product
is analysed to show that the 9T SRAM cell achieves significant power reduction in the presence of
PVT variations.

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CHAPTER - 3

PROJECT METHODOLOGY AND ANALYSIS

A. WORKING PROCEDURE

While traditional SRAM cells rely on 6 transistors for data storage, a variation exists that
utilizes 9 transistors and transmission gates. This 9T SRAM design offers improved isolation
between read/write operations and the memory latch itself. Transmission gates, acting as electronic
switches, are employed during data access. When reading data, a specific control signal activates a
transmission gate, allowing the current voltage of the storage node to be read without affecting the
stored information. During writing, a different control signal activates a separate transmission gate
connected to the incoming data, which overwrites the previous state. This method provides better
isolation compared to traditional designs. Additionally, 9T SRAM cells with transmission gates have
the potential for lower power consumption. Overall, this design offers advantages in isolation and
potentially lower power usage, making it suitable for various integrated circuits demanding high-
density, low-power memory, such as processors and embedded systems.

• The circuit consists of nine transistors, which are labeled MP1 through MP4, MN1 through
MN3, and INV1 and INV2.

• The data is stored in the form of the voltage on the node labelled Q.

• The bit line (BL) is used to read the data from the cell.

• The bit line bar (BLB) is used to write data to the cell.

• The transistors INV1 and INV2 are used to provide feedback to the circuit.

3.1 PROPOSED SE9T SRAM CELL DESIGN

A. Cell Structure

The proposed TG9T is shown in figure gives the different control signals for different
operations. During the read operation, one of the bit lines is discharged depending on the data in the
storage nodes, Q and QB. During the write operation, due to the removal of the feedback path, the
cell is able to write the desired data successfully. In the hold mode, all the access transistors are
maintained in OFF condition while bit line bar (BLB) and bit line (BL) are set at VDD.

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Figure 3.1.1: Schematic of the proposed SE9T SRAM cell.

Figure 3.1.2: Simplified array architecture of the proposed design.

Proposed an SRAM cell to improve write ability, by incorporating a single transistor for
loop-cutting (during the write operation) in the 6T SRAM cell . However, still, this cell has not been

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able to ameliorate the read stability adequately. Attempts to increase the read stability have involved
using read decoupled circuitry. Various SRAM cells utilising this technique have been proposed in
for SRAM cells. They utilise separate read ports to achieve disturbance-free read operation.
However, they suffer from data-dependent bit line leakage and sense margin problem in read mode
or provide extra paths for flowing leakage currents and require a larger cell area .

B. Read operation

In the read operation variability is decreased due to the use of the TGs in the proposed cell.
The reason for this is the averaging effects of the two parallel transistors in the TG. This can be
easily explained by using the inherent characteristics of TG (see Figs. 4-6). The effective resistance
(RE = RN||RP) of TG is best illustrated in Fig. 6. As Vout (VQB in our case) increases, RN [resistance of
N-type metal oxide semiconductor (NMOS)] increases, hence current passing through it decreases,
whereas RP [resistance of P-type metal oxide semiconductor (PMOS)] decreases, hence current
passing through it increases. As can be seen from Fig. 6, the effective resistance of TG remains
almost constant irrespective of the voltage across it and hence current through TG (parallel
combination of NMOS and PMOS) also remains constant . This phenomenon helps in
averaging/stabilising the net current passing through the TG. From this, it can be inferred
that IREAD through TG is more stable than IREAD through NMOS.

Figure 3.1.3: read current path during a read operation.

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Figure 3.1.4: variability of read current (IREAD) versus VDD for 7T , TG9T.

C. Hold Operation

The progress in semiconductor integrated circuit technology is mostly the result of the device
dimension scaling. However, the supply voltage has not been scaled down with the same proportion
as the device dimensions. Consequently, the longitudinal electric field in the pinch-off region, as
well as the transverse electric field across the gate oxide has increased with increase in MOSFET
scaling. When an electron travels from the source to the drain along the channel of a MOSFET, it
becomes energetic and hot. Some of the hot electrons can cross over the barrier of SiO2, giving rise
to the gate leakage current (IG) . Other hot electrons, travel towards the drain and collide with Si
atoms, creating secondary electron–hole pairs by impact ionisation. The electrons are collected by
the positive drain bias, whereas the holes are collected by the negative body bias, giving rise to the
substrate current (IB) .

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Figure 3.1.5: Hold power (HPOWER) versus supply voltage (VDD).

Slightly lower leakage in TG9T is due to a greater number of PMOS devices in it. Why this
happens can be perceived by considering the hot-carrier injection mechanism in short-channel
devices. The crossing of electrons from Si to polysilicon (gate material) through SiO2 is more likely
than the crossing of holes, as electrons possess lower effective mass than that of holes. Moreover,
the barrier height for holes is 4.5 eV whereas that of electrons is 3.1 eV. Thus, a greater number of
PMOS devices in TG9T slightly reduces leakage current as compared to the 7T SRAM cell. The
lower leakage current of TG9T compared to 7T at all corresponding voltages gives rise to higher.

D. Write Operation

In write operation in addition to read stability, write ability is also an important design metric
of an SRAM cell. Write ability of an SRAM cell depends upon the sizes of the pull-up transistor and
access transistor. The ratio between the sizes of the pull-up transistor and access transistor is known
as the pull-up ratio(γratio = βpull-up/βaccess).Generally, γratio ≤ 1.8 is required to maintain good write

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ability . We have maintainedγratio = 1 for all the compared cells. SEDF9T isa read decoupled circuit.
Therefore, there is no sizing conflict between read and write operations. We have taken iso-sized
cells for all the compared structures. WSNM is the design metric through which write ability can be
quantified . Write ability of an SRAM cell is estimated as mentioned . In read and write voltage
transfer characteristics (VTCs) of all four cells are plotted with their respective WSNM values at
nominal VDD of0.7 V. The WSNM of the four cells follows this respective order.

7T and TG9T show improvement in WSNM because of the feedback cutting mechanism.
Furthermore, because of the less drive current, due to TG, TG9T shows lower write ability than 7T.
However, this TG helps achieve narrower spread in WSNM compared to other cells.

E. Proposed 128 × 128 SRAM Memory Array

Each memory cell within the 128 × 128 array consists of nine transistors organized in a
compact layout, offering a balance between area efficiency and performance. The cell comprises six
access transistors and three storage transistors, facilitating stable read and write operations while
minimizing leakage currents.

The write operation in the 9T SRAM cell involves a differential approach, where the data to
be written is applied differentially to the storage nodes, enhancing write stability and noise
immunity. This approach ensures reliable data retention and integrity, even in the presence of
process variations and environmental disturbances.

Figure 3.1.6: Proposed 128 × 128 SRAM memory.

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The compact footprint of the 128 × 128 memory array, coupled with its low-power
characteristics, makes it an ideal candidate for integration into system-on-chip (SoC) designs
targeting mobile devices, wearable electronics, sensor nodes, and other power-constrained
applications. Additionally, the scalability of the 9T SRAM cell architecture facilitates the
development of larger memory arrays with higher density, catering to the evolving demands of
future computing systems.

Figure 3.1.7: Timing diagram of 9T SRAM cell.

Figure 3.1.8: Thin cell layout of TG9T.

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The areas of the structures, layouts of TG9T, 7T, SEDF9T, and FD8T are generated. TG9T
(see the layout ) occupies 18.9% more area than 7T and SEDF9T and the same area as of FD8T. The
higher area consumption in TG9T is due to the presence of TGs in place of NMOS access transistors,
whereas it is so in case of FD8T due to the presence of an extra inverter. The extra decoupled-read
circuitry in case of SEDF9T fits perfectly in the area left by the largely sized pull-down transistors
and thus requires a lower area. Our approach of validation is in line with the approach
adopted .Simulation results using UMC 130 nm CMOS technology are reported in Table. Moreover,
the physical layout has been carried out and extracted parasitic have been used to obtain post-layout
simulation results at the 130-nm technology node which can closely model the real chip behaviour.
The HPOWER of post-layout simulation is found to be lower than pre-layout (schematic) simulation
because of the increased parasitic resistances.

3.2 SRAM PERFORMANCE AND COMPARISON.

The 9T SRAM cell offers superior performance in terms of read and write speeds compared
to its counterparts. This improvement stems from its optimized design, which reduces the impact of
data retention time constraints and enhances write stability through the incorporation of
additional transistors. Consequently, the 9T cell enables faster data access and manipulation,
enhancing overall system responsiveness. In comparison with other SRAM cell architectures, such
as the 6T and 8T cells, the 9T SRAM cell offers a compelling balance of performance, power
efficiency, and reliability. While the 6T cell may excel in area efficiency, the 9T cell outperforms it
in terms of stability and speed. while the 8T cell improves upon certain aspects of the 6T design, the
9T cell typically offers superior performance and power efficiency, making it the preferred choice
for many high-performance computing applications.

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6T SRAM 8T SRAM

Figure 3.2.1: SRAM Performance And Comparison.

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3.3 SIMULATION OF 9T SRAM CIRCUITS AND OPERATION

Figure 3.3.1: Schematic for write 0 opearation

During a write operation, a specific voltage is applied to the Write Lower Bit (WLB) line
and the Write Data Select (WDS) line. In the image, a ‘0’ on the WLB line selects it for the write
operation. When a ‘0’ is applied to the WLB line (Write Lower Bit), it turns on transistor M10
(labeled M12 in the image). This creates a path for current to flow from VSS (ground) through
M10 to the Bit Line Lower (BLB) line, effectively pulling BLB low (to logic ‘0’). By forcing BLB
low, the circuit writes a ‘0’ to the cell. This low voltage on BLB is reflected on the storage node
(Q) of the SRAM cell.

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Figure 3.3.2: Schematic for write 1 operation

When a high voltage is applied to the WLB line (labeled ‘1’ in the image), it turns on
transistor M3 (labeled TW = 64n in the image). This creates a path for current to flow from VDD
(the positive power supply) to the Bit Line Lower (BLB) line, driving BLB high. As current flows
from VDD through M3 to BLB, the BLB line is driven to a high voltage level (logic ‘1’). This high
voltage on BLB is what represents the data being written to the cell. During a write ‘1’ operation,
the RD and CTRL lines are low (grounded), keeping transistors M4 (N4) and M7 (N7) off. This
isolates the data storage nodes from the bit lines.

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Figure 3.3.3 : Schematic for read operation

The Bit Line Read (RBL) line is pre-charged to a high voltage level (close to VDD) before
a read operation begins. Data path creation: With RD high, M7 turns on and creates a path for current
to flow from the cell’s storage node (Q) to the RBL line. If a logic ‘1’ is stored on node Q (as
depicted in the image), the current path through M7 discharges the RBL line. The amount of voltage
discharged from RBL depends on the strength of the ‘1’ stored at Q. By sensing the voltage level
on the RBL line after the read operation, the circuitry can determine the data stored in the cell. A
high voltage on RBL indicates a stored ‘0’, while a discharged RBL indicates a stored ‘1’.

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Figure 3.3.4 : schematic for hold operation

When the word line (WL) is set to low voltage (ground), transistors M5 (N5) and M6 (N6)
are turned off. This disconnects the bit lines (BL and BLB) from the cell’s data storage nodes (Q
and QB). With the bit lines disconnected, the cell’s data is preserved by the feedback mechanism
between the two inverters within the cell. If a ‘1’ is stored on node Q (and ‘0’ on QB), M1 will be
on (pulling Q up to VDD) and M2 will be off (isolating QB). Conversely, if a ‘0’ is stored on Q, M2
will be on (pulling Q down to ground) and M1 will be off (isolating QB). As long as WL remains
low, this feedback loop maintains the stored data on the cell. During hold, the bit lines (BL and
BLB) can be pre-charged to a specific voltage level (often close to VDD) in preparation for a
future read operation.

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• 4X4 SRAM Cell Design

Figure 3.3.5 : AND gate schematic.

The AND gate has two inputs, labeled A and B in the image. Each input can represent a
binary value of 0 or 1. The circuit uses transistors to implement the AND logic. Exactly how many
and what type of transistors are used can vary depending on the specific design, but the schematic
you sent appears to use two NMOS (negative-gate metal-oxide-semiconductor) transistors, likely
configured in series. The AND gate has a single output, labeled Y in the image. The output Y
represents the logical AND of the inputs A and B.

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Figure 3.3.6 : 4 input OR gate schematic.

Inputs: It has four independent binary inputs, commonly labeled A, B, C, and D.

Output: It produces a single binary output, usually labeled Q.

Operation: The output (Q) is HIGH (1) only if at least one of the inputs (A, B, C, or D) is HIGH
(1). If all four inputs are LOW (0), the output is LOW (0).

In simpler terms, as long as there's a "1" on any of the input lines, the output will be a "1".
Only when all inputs are "0" will the output be "0".

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Figure 3.3.7 : Inverter gate schematic.

Inverter:
• The inverter circuit uses a single transistor (labeled M1 in the image) to perform a logical
negation operation on its input.
• There are two terminals for the inverter: an input (labeled A in the image) and an output
(labeled Y in the image).
• When a high voltage (logical 1) is applied to the input (A), the output (Y) of the inverter
becomes low voltage (logical 0). Conversely, when a low voltage (logical 0) is applied to
the input, the output becomes high voltage (logical 1).

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Figure 3.3.8: Decoder schematic.

The circuit likely uses three input lines labeled A, B, and C. Each line can represent a binary
value of 0 or 1. The decoder circuit uses a combination of logic gates, likely NAND gates, to decode
the binary input on the A, B, and C lines. Each output line is connected to a specific combination of
these logic gates. Some decoders include an enable line, which is not shown in the image you sent.
When enabled (usually with a high voltage), the decoder functions normally. When disabled (usually
with a low voltage), all output lines are inactive (low voltage). Only one of the eight output lines (0
to 7) will be active (high voltage) for a given input code on lines A, B, and C. The specific output
line that becomes active depends on the binary value on the input lines. For example, if the binary
value on A, B, and C is 001, then output line number 1 should be active.

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Figure 3.3.9: Schematic of 4*4 SRAM cell.

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B. FLOWCHART

Start: This is the beginning of the flowchart where the process of describing the 9T
SRAM cell begins.

Design Specification: This step involves defining the functionalities and requirements for the digital
circuit.

Schematic Capture: In this stage, a schematic diagram is created using electronic design
automation (EDA) software. The schematic diagram represents the symbols for the electronic
components and their interconnection.

Create Symbol: This step might involve creating a symbol for the digital circuit being designed.
This symbol would be used in schematics to represent the entire circuit.

Simulation: Here, computer-aided simulation (CAS) software is used to examine the behavior of
the designed circuit before it’s physically produced.

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Verification: The results from the simulation are checked against the initial design specifications
to ensure the circuit performs as intended.

Transient Analyses: If the simulation results deviate from the specifications, the designer loops
back to schematic capture to make modifications to the circuit. This creates a loop where the circuit’s
behavior is simulated and verified until it meets the requirements.

Analysis of Power, Delay and Area: Once the circuit meets the specifications through simulation
and verification, this step involves analyzing factors like power consumption, the time it takes for
the circuit to produce an output (propagation delay), and the physical space occupied by the circuit
on the silicon chip (area).

End of Design: If the power, delay, and area meet the design constraints, this signifies the successful
completion of the design process.

End: This indicates the entire design process is complete.

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CHAPTER-4

IMPLEMENTATION
SOFTWARE DESCRIPTIONS

S-Edit is a schematic capture tool. It allows designers to create and edit the schematic
representation of an electronic circuit.

L-Edit is a layout editor used for designing the physical layout of integrated circuits.

A. INTRODUCTION TO S-EDIT AND L-EDIT

S-EDIT AND L-EDIT TECHNOLOGY

S-Edit and L-Edit are integral components in the realm of electronic design automation
(EDA), facilitating the creation, modification, and analysis of electronic schematics and physical
layouts of integrated circuits (ICs). These tools play crucial roles in the design and manufacturing
processes of microchips and other electronic components, offering engineers and designers
powerful capabilities to bring their concepts to fruition.

S-Edit, standing for Schematic Editor, serves as the foundation for capturing electronic
schematics. It provides a user-friendly interface where designers can draw and manipulate the
logical connections between various electronic components. This includes elements such as
transistors, resistors, capacitors, and integrated circuits. S-Edit allows for the creation of complex
hierarchical designs, enabling engineers to organize and manage intricate circuitry effectively.
Moreover, it often integrates with simulation tools, allowing designers to validate and verify their
designs before moving on to the layout phase.

L-Edit, or Layout Editor, complements S-Edit by enabling the physical realization of the
schematics created. L-Edit allows designers to define the precise placement and routing of
components on a semiconductor substrate. This involves specifying the exact dimensions, spacings,
and orientations of the various components to ensure proper functionality and manufacturability. L-
Edit provides advanced features such as design rule checking (DRC) and layout versus schematic

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(LVS) verification, helping designers identify and resolve potential issues early in the design
process.

Both S-Edit and L-Edit are highly customizable and adaptable to the specific requirements
of different design projects. They support a wide range of industry-standard file formats, facilitating
interoperability with other EDA tools and manufacturing processes. Additionally, they often
incorporate scripting and automation capabilities, allowing designers to streamline repetitive tasks
and enhance productivity.

These tools are particularly essential in the semiconductor industry, where the demand for
smaller, faster, and more efficient electronic devices continues to grow. Engineers rely on S-Edit
and L-Edit to optimize the performance, power consumption, and cost-effectiveness of their designs
while meeting stringent design constraints and specifications.

S-Edit and L-Edit are continuously evolving to keep pace with advancements in
semiconductor technology and design methodologies. Developers regularly release updates and new
features to address emerging challenges and enable designers to push the boundaries of innovation.

INTRODUCTION TO S-EDIT

S-Edit is a powerful and versatile text editor designed to meet the needs of programmers,
writers, and anyone who works extensively with text. Offering a wide range of features and
customization options, S-Edit provides a seamless and efficient editing experience for users across
various industries and disciplines.

At its core, S-Edit boasts a clean and intuitive interface, making it easy for users to navigate
and utilize its robust set of tools. Whether you're a novice or a seasoned professional, you'll find S-
Edit's interface to be both user-friendly and highly functional, allowing you to focus on your work
without unnecessary distractions.

One of the key features of S-Edit is its support for multiple programming languages and file
formats. From HTML and CSS to Python and Java, S-Edit provides syntax highlighting and auto-
completion features that streamline the coding process and help minimize errors. Additionally, S-

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Edit's customizable themes and color schemes allow users to tailor the editor to their preferences,
further enhancing productivity and comfort during long editing sessions.

In addition to its support for programming languages, S-Edit also excels as a general-purpose
text editor, offering a suite of tools for writing, editing, and formatting text. Whether you're drafting
a novel, composing an email, or taking notes for a meeting, S-Edit provides the flexibility and
functionality you need to get the job done efficiently.

Another standout feature of S-Edit is its extensive plugin ecosystem, which allows users to
extend the editor's functionality to suit their specific needs. Whether you're looking to integrate
version control systems like Git, enhance code navigation with tools like ctags, or streamline your
workflow with task management plugins, S-Edit's plugin architecture makes it easy to customize
the editor to match your workflow and preferences.

Beyond its feature set, S-Edit also prioritizes performance and reliability, ensuring that users
can work with large files and complex projects without experiencing slowdowns or crashes. With
its efficient resource management and optimized codebase, S-Edit delivers a smooth and responsive
editing experience, even when handling demanding tasks.

S-Edit is a versatile and powerful text editor that caters to the needs of programmers, writers,
and users across various industries. With its intuitive interface, extensive feature set, and
customizable plugin ecosystem, S-Edit provides a seamless editing experience that enhances
productivity and creativity for users of all skill levels. Whether you're writing code, drafting
documents, or managing projects, S-Edit is the ideal tool for getting the job done efficiently
and effectively.

INTRODUCTION TO L-EDIT

L-Edit, short for Layout Editor, is a powerful software tool used in the field of
microelectronics for designing and simulating integrated circuits (ICs). It provides a user-friendly
interface that allows engineers and designers to create, modify, and analyze the layout of ICs with
precision and efficiency.

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At its core, L-Edit enables users to visualize and manipulate various components of an IC
layout, such as transistors, capacitors, resistors, interconnects, and other devices. It offers a wide
range of features and functionalities tailored to meet the complex requirements of modern IC design.

One of the key features of L-Edit is its flexibility in supporting different design
methodologies, including analog, digital, mixed-signal, and radio-frequency (RF) circuits. Whether
designing simple logic gates or complex analog circuits, L-Edit provides the necessary tools and
capabilities to streamline the design process.

The software employs a hierarchical design approach, allowing designers to organize

complex circuits into manageable modules or blocks. This hierarchical structure enhances design
reusability, facilitates collaboration among team members, and simplifies the overall design process.

L-Edit incorporates advanced layout automation techniques to expedite the design process
and ensure design consistency. Users can take advantage of features such as automatic wire routing,
parameterized cells, design rule checking (DRC), and layout versus schematic (LVS) verification to
improve productivity and design accuracy.

Additionally, L-Edit offers comprehensive design rule support, enabling designers to adhere
to fabrication constraints and standards imposed by semiconductor foundries. By performing real-
time DRC checks, the software helps prevent layout errors and ensures designs are manufacturable.

For designers working on leading-edge technologies, L-Edit provides support for advanced
process nodes, including submicron and nanometre scales. It offers precise control over layout
parameters such as transistor sizes, wire widths, and spacing, allowing designers to optimize
performance, power, and area (PPA) metrics.

Integration with other EDA (Electronic Design Automation) tools is another strength of L-
Edit. It seamlessly interoperates with tools for schematic capture, simulation, extraction, and
verification, enabling a cohesive design flow from concept to tape-out.

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L-Edit is a comprehensive and versatile IC layout tool that empowers designers to create
high-quality, manufacturable IC layouts efficiently. With its rich feature set, intuitive interface, and
robust automation capabilities, L-Edit is an indispensable tool in the arsenal of microelectronics
designers striving for innovation and excellence.

B. WORKING OF S-EDIT AND L-EDIT

S-EDIT WORK

Schematic Design: S-Edit primarily focuses on creating and editing schematic designs for
integrated circuits (ICs).

Symbol Creation: It allows users to create and modify symbols representing various electronic
components such as transistors, resistors, capacitors, etc.

Hierarchical Design: S-Edit supports hierarchical design, enabling the creation of complex ICs
by organizing them into hierarchical blocks.

Netlist Generation: It generates netlists, which are textual representations of the connections
between components in the circuit.

Integration with Other Tools: S-Edit often integrates with other EDA (Electronic Design
Automation) tools such as L-Edit for layout design and simulation tools for verifying circuit
functionality.

Schematic Capture: S-Edit allows designers to capture the logical structure of an integrated
circuit (IC) through the creation and manipulation of schematic diagrams.

Symbol Libraries: It provides extensive libraries of predefined symbols for common electronic
components, as well as the ability to create custom symbols for specialized components.

Hierarchical Design: S-Edit enables hierarchical design, allowing designers to break down
complex circuits into manageable blocks and sub-blocks for easier understanding and
organization.

Netlist Extraction: It extracts netlists from schematic diagrams, which serve as input for
downstream processes such as layout design and circuit simulation.

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Simulation Interface: S-Edit often integrates with simulation tools to facilitate pre-layout
simulation, enabling designers to verify the functionality and performance of their circuits before
committing to layout.

L-EDIT WORK

Layout Design: L-Edit specializes in the layout design of ICs, translating schematic designs into
physical layouts of components and interconnections.

Mask Layout: It provides tools for creating the mask layout, which is the blueprint for
manufacturing the IC, including the positions and shapes of components, metal layers, and doping
regions.

Design Rule Checking (DRC): L-Edit includes DRC features to ensure that the layout design
conforms to the manufacturing constraints and specifications.

Layout Versatility: Users can customize the layout according to various fabrication processes,
technology nodes, and design requirements.

Integration with Simulation Tools: L-Edit often integrates with simulation tools to verify the
functionality and performance of the designed layout before fabrication.

Physical Layout Creation: L-Edit translates schematic designs into physical layouts, defining
the precise geometric shapes and arrangements of components on the silicon substrate.

Mask Layout Generation: It generates mask layouts, which are used in the photolithography
process to transfer the circuit pattern onto the semiconductor wafer during fabrication.

Design Rule Checking (DRC): L-Edit performs design rule checking to ensure that the layout
adheres to the manufacturing constraints and specifications imposed by the fabrication process.

Layout Versatility: Designers can configure L-Edit to work with different technology nodes,
process technologies, and foundry-specific design rules, accommodating a wide range of design
requirements.

Integration with Physical Verification Tools: L-Edit often integrates with physical verification
tools such as DRC and LVS (Layout vs. Schematic) tools to detect and resolve layout errors and
inconsistencies early in the design cycle.

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CHAPTER-5

RESULTS
PROJECT OUTPUT RESULTS

Figure 5.1.1: Simulation result for write 0 operation.

Figure 5.1.2: Simulation result for write 1 operation.

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Figure 5.1.3: Simulation result for read operation.

Figure 5.1.4: Simulation result for hold operation.

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Figure 5.1.5: AND output.

Figure 5.1.6: 4 Input OR gate output.

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Figure 5.1.7: Inverter output.

Figure 5.1.8: Decoder output.

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Figure 5.1.9: Result for 4*4 SRAM cell.

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CHAPTER 6

TESTING & DEBUGGING

6.1 Testing:

Define expected behaviour: Before running the simulation, clearly define the expected output
voltages, currents, waveforms, etc., for different inputs and conditions.

Start simple: Begin with basic circuit configurations and gradually add complexity to isolate
potential problems.

Sweep analysis: Utilize LTspice's sweep analysis capabilities to vary component values or input
signals and observe the resulting changes. This helps identify component sensitivity and circuit
behaviour under different conditions.

Monte Carlo analysis: Run a Monte Carlo analysis to account for component value variations and
assess the circuit's robustness.

6.2 Debugging:

Visual inspection: Carefully examine the schematic for incorrect connections, component
placement, or missing elements.

Error messages: Pay close attention to any error messages generated during simulation. These often
provide valuable clues about syntax errors, component limitations, or convergence problems.

DC operating point analysis: Use the DC operating point analysis to check for unexpected bias
voltages or currents that might prevent the circuit from functioning as intended.

Probe voltages and currents: Utilize probes to monitor voltages and currents at various points in
the circuit. Analyze the waveforms for unexpected spikes, oscillations, or incorrect values.

Simulate in steps: Run the simulation in steps (using the .tran statement with a small step size) to
pinpoint the exact time when an issue arises. This can be helpful for identifying transient
response problems.

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Figure 6.2.1: S-Edit tab.

Draw the desired schematic with specific inputs and outputs, then click on run simulation as
highlighted above.

Figure 6.2.2: TSPICE Simulation setup.

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Open Tspice displayed in tabs after clicking the run simulation, the above specified
tab will be opened.

Figure 6.2.3: TSPICE Simulation Status.

If there are any errors or warnings in the schematic, the warnings or errors are
dosplayed as shown above.

Figure 6.2.4: TSPICE Warning display Page.

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By right clicking twice, it shows the line which has that specified error or warning. After
finding out the errors and warnings in the schematic, we can go back to the S-edit and modify the
schematic without any errors and warnings. saving this circuit after modifications and following the
same steps from run simulation gives the required result.

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Transmission Gate-Based 9T SRAM Cell MJ20-A07

ADVANTAGES

Variation Resilience: The additional transistors in the 9T SRAM cell provide better tolerance to
process variations, enhancing reliability in IoT devices.

Low Power Consumption: By utilizing transmission gates, these cells can achieve lower leakage
power compared to conventional 6T SRAM cells, crucial for IoT devices that operate on limited
power sources.

Improved Read Stability: The extra transistors in the cell improve read stability, reducing the
likelihood of data corruption, which is essential for reliable operation in IoT environments.

Enhanced Write Ability: The larger number of transistors can enhance the cell's write ability,
ensuring reliable data storage and retrieval in various operating conditions. Improved Retention
Voltage: The 9T SRAM cell can have a higher retention voltage compared to the 6T SRAM cell,
ensuring data integrity is maintained even in low-power modes or during power supply fluctuations.

Reduced Read Disturbance: The additional transistors in the cell can mitigate read disturb issues
commonly found in 6T SRAM cells, enhancing long-term reliability and endurance, crucial for IoT
devices with frequent read operations.

Better Yield: The enhanced variation resilience and stability of the 9T SRAM cell can lead to better
manufacturing yield, reducing the likelihood of defective memory cells in IoT devices.

Flexible Operation: The 9T SRAM cell's design allows for flexible operation, enabling
customization to meet specific performance, power, and reliability requirements of diverse IoT
applications.

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Transmission Gate-Based 9T SRAM Cell MJ20-A07

DISADVANTAGES

Sensitivity to Noise: The increased complexity and additional components may make the cell more
susceptible to noise, potentially affecting reliability in noisy IoT environments.

Design Challenges: Designing and optimizing transmission gate-based 9T SRAM cells require
expertise and careful consideration of various factors, including process variations, power
constraints, and reliability requirements, posing challenges for designers.

Higher Area Overhead: The additional transistors in the 9T SRAM cell result in a larger cell size,
consuming more silicon area compared to the 6T SRAM cell, which may limit scalability and
increase overall chip cost.

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Transmission Gate-Based 9T SRAM Cell MJ20-A07

CONCLUSION

A TG9T SRAM cell is proposed for IoT application. TG9T has mainly been compared with
other similar-sized SRAM cells, namely, 7T cell, FD8T cell and single-ended read-disturb-free 9T
(SEDF9T) in the study. The proposed cell shows 1.25×/1.53× lower hold power than 7T/SEDF9T
due to lower leakage currents. Furthermore, it consumes 1.17×/1.21× and 1.07×/1.03× lower power
during the read and write operations, respectively, than 7T/FD8T. TG9T achieves better write ability
and read stability with 1.42×/5.3× higher WSNM than FD8T/SEDF9T and 1.40×/1.80× higher
RSNM than 7T/FD8T. The proposed cell also shows less variability in all the parameters discussed
in the study. Furthermore, TG9T can operate at the lowest VDD,min among the compared cells with
an improvement of 1.22×/1.60×/1.88× compared to 7T/FD8T/SEDF9T. All these improvements are
achieved at a cost of slightly higher read/write delay than 7T and FD8T, and lower RSNM than
SEDF9T. Finally, the cell TG9T attains the highest EQM/V2EQM among all the cells compared in
Table 6. Finally, we believe that our proposed TG9T SRAM cell is suitable for low power, robust
and reliable IoT applications.

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Transmission Gate-Based 9T SRAM Cell MJ20-A07

FUTURE SCOPE

The future scope of this research could involve further optimization of the 9T SRAM cell
design to achieve even lower power consumption and faster access times. This could include
exploring material innovations for transistors, incorporating multi-bit storage capabilities, and
investigating techniques for mitigating variability at even smaller technology nodes. Additionally,
research into error correction codes and fault tolerance mechanisms could be integrated to further
enhance the reliability of the SRAM cell for mission-critical IoT applications.

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Transmission Gate-Based 9T SRAM Cell MJ20-A07

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