1B (CSIT-Sem-3) QUANTUM SERIES ee For B.Tech Students of Second Year of All Engineering Colleges Affiliated to A.P.J. Abdul Kalam Technical University, Uttar Pradesh, Lucknow (Formerly Uttar Pradesh Technical University) Dr. Computer Organization & Architecture By Aditya Kumar Quantum — Page — QUANTUM PAGE PVT. LTD. Ghaziabad m New Delhi3B(CSAT-Sem.9) EE — CONTENTS KCS 302 : Computer Or, ganization @ Architectur UNIT - 1: INTRODUCTION Functional units of digital system a (lt erchitecture, types of Buses and bus abiteramterconnectons, vue architeepacessor organization, oneal req Register busand memory eearaeldreaing ae eee stack organizati UNIT-2: ARITHMETIC & LOGIC UNIT “ook ahead carries adders. Multiplication: Signed (2-1 B to 2-25 B) Dooths algorithm and array multiplier. Divisi operand multiplication, Floating point arithmetic operation, Arithmetic ran ae eee Standard for Floating Point Numbers logic unit design. IEEE 3: CONTROL UNIT Fnatruction types, formats, instruction cycles and sub cy i ae Inatiteete) micro operations, execution ofa competein Doan and Cettrol, Reduced Instruction Set Compute Pipelining ea cfero programmed control: micro programme sequescin a horizontal and vertical microprogramming, i concept of UNIT - (4-1 B to 4-30 B) semiconductor RAM memories, 2D & 2 memories. Cache memories: concept g and replacement cal disks UNIT- 4: MEMORY Basic concept and hierarchy, 1/2D memory organization. ROM wr design issues & performance, address mapping anvdliary memories: magnetic disk, magnetic tape and opti Jutual memory: concept implementation (6-1 B to 5-21 B) 1/0 interface, I/O ports InterruPt errupthardware, y and exceptions. Modes of Data Transfer: Programmed DO interrupt initiated 1/0 and Direct Memory Access, 1/0 ‘channels, and processors. Serial Communication: Synchronous & asynchronous Sedard communication interes: 5; INPUT / OUTPUT UNIT - Peripheral devices, types of interrupts communication, SHORT QUESTIONS (Q-1Bto S0-17B) (SP-1 Bto sp-20 B) SOLVED PAPERS (2014-15 TO 2018-19)Introduétig, CONTENTS Part-1 -Part-2 Part-3 Part-4 Part-5 Part-6 Part-7 Introduction : Functional . Units of Digital System and their Interconrection + 1-2B to 15 Bus, Bus Architecture, . 1-5B to 1-68 Types of Buses Bus Arbitration .... +. 1-6B to 1-8B Register, Bus and. . 1-8B to 1-11B Memory Transfer Processor Organization, General Register Organization +. 1-11B to 1-12B Stack Organization .. ..1-13B to 1-178 Addressing Modes... ..1-17B to 1-22BT-Sem-3) Introduction ascent otion : Functional Units of Digital System and thei ir Introd Interconnection, sgn eT Questions-Answers' and Medium Answer Type Questions Long Answer TyPe i Gaatd [Drm block diagram of a computer's CPU showing all sic building blocks such as program counter, accumulator, iota registers, instruction register, control unit ete, such an arrangement ean work as a computer, if to memory, input/output ete. # AKTU 2016-17, Marks 7.5 the bai address and and describe how § connected properly Answer Block diagram of computer’s CPU: RAM Memory ADDRESS BUS sae Memory data address ar | _DATABUS| MDR register register cpubus ¥ : t Accumulator Instruction, IR PC ‘ACC [* (work register) register JA 1 =} Control ALU |, Arithmetic (logic unit Program counter Control lines Fig. 111. ‘A.computer peviorms five major operations ‘These are : Tt accepts data or instructions as input It stores data and instruction. «data as per the instructions. nside a computer. all operations i orm of output 1 a 3. It proce 4, Itcontrol: It gives results in the fo4-3 B (CST Sem) asacomputer, Computer Organization & Archi wort ‘Arrangement of CPU, memory iP} Input Devices ‘Main/Internal ‘Memory Fig. 11.2. . rograms into the a. Input unit : This unit is used for entering data and Pp’ cessing. and instructions computer system by the user for pr unit is used for: storing data b. Storage unit : The storage before and after processing. Output unit : The output unit is used for storing the resul produced by the computer after processing. task of performing operations like arithmetic It as output d. Processing unit : Th , and logical operations is called processing. ‘The Central Processing Unit (CPU) takes data and instructions from the storage unit and makes all sorts of calculations based on the instructions given and the type of data provided. It is then sent back to the storage unit. Que 12, | Explain the functional units of digital system and their interconnections. Answer The main functional units of a digital computer are shown in Fig. 1.2.1. 1. Central Processing Unit (CPU) : a. The CPU is the brain of a computer system. b. This unit takes the data from the input devi i according to the set of instructions called eas a The output of processing of the data is di for use inthe outside world, Te*tedto the output devies 4. CPU has two major parts called ALU and Control Unj nit.Introduction 1-4 B (CSAT-Se! Storage Unit Secondary Program Storage and Data v f Information (Results) Primary Storage —e Indicates flow of instructions and data Arithmetic Logic Unit -~Indicates the control exercised by the control unit Central Processing Unit (CPU) Fig. 1.2.1. Functional unit of digital computer Arithmetic Logic Unit (ALU): 'ALUis responsible for carrying out following operations : 1, Arithmetic operations on data by adding, subtracting, multiplying and dividing one set with another. 2, Logical operations by using AND, OR, NOP and ausive-OR operation which is done by analyzing and evaluating data. b. ALU of a computer system is execution of instructions takes place operation. a the place where actual during processing ii, Control Unit (CU) : This unit is mainly used for generating the electronic control signals for the synchronization of various operations. b. All the relat a. am execution such as , VOwrite, execution through the control signal ted functions for progr: memory read, memory’ write, of instruction, are synchronized generated by the control unit. vesand controlsall the operations ofthe computer. following functions : and data from outside world. puter acceptable form. uter system It manag’ An input unit performs tions and data in com and data to comp’ 2 Input uni a Itace b. It converts th apts (or reads) instruc instructions rted instructions ng c. It supplies the conve! for further proces®1-5B (CSAT-Sem.a, c Omputer Organization & Architecture functions: 3. , a Output unit : An output unit performs following ‘Tt accepts the results produced by a computer which are in codeg form. b he converts these coded results to human acceptable (readable, form, © ~ It supplies the converted results to outside world. 4 Storage unit : A storage unit holds (stores): & Data and instructions required for processing received from inpy, devices). b. Intermediate results of processing. ©. Results for output, before they are released to an output device, PART-2 Bus, Bus Architecture, Types of Buses- Questions-Answers Long Answer Type and Medium Answer Type Questions jue 1.3. | What is a bus in digital system ? Also explain its types. Que1s. ] 1. Abus is a group of wires connecting two or more devices.and providing apath to perform communication. A bus that connects major computer components/modules (CPU, Memory, I/O) is called a system bus. ‘These system buses are separated into three functional groups : i, Data bus: a. The data bus lines are bidirectional. b. The data bus consists of 8, 16, 32 or more parallel lines. ii, Address bus: a. It isaunidirectional bus. b. The address bus consists of 16, 20, 24 or more parallel lines. The CPU sends out the address of the memory location or !O port that is to be written or read by using address bus. iii, Control bus: . a. Control lines regulate the activity on the bus. ‘sincmissniiastiinniill1-6 B (CS/IT-Sem-3) Introduction ‘The CPU sends signals on the of addressed memory device or ortdarig Que 14, | Describe the architecture of bus. Answer 1. The computer bus consists of two parts, the addi era bas Wanaioee setial SaicYwhereac ae alates Gee Cee dress or memory location of where the data should go. transfers ‘The bus provides physical links and the m Sean a leans of communication exchange of signals over the bus. Tig controling the organization ofa single shared bus, eee ee ———————— Control System 7 7 a Address tt Ht i Tt Main v0 v0 memory | | device 1 device n Data | CPU Fig. 1.4.1. Architecture of a single shared bus. 3, The principle use of the system bus is high-speed data transfer between the CPU and memory. 4, Most UO devices are slower than the CPU or the memory. The /O devices are attached to the system bus through external interfaces. 5. ‘The Input/Output (1/0) ports are used to connect various devices to the computer and hence, enable communication between the device and the computer. PART-3 Bus Arbitration. ee Questions-Answers er Type Questions Long Answer Type and Medium Answp(CSIIT-Sem. Computer Organization & Architecture wes] Discuss the bus arbitration OR Write a short note on bus arbitration. sides the selection of current connected to a shareq a Bus arbitration is a mechanism which de master to access bus. 2. Among several masters and slave units that °° bus, it may happen that more than one master oe access to the bus at the same tims ving hij .8. In such situation, bus access is given to the master having highest vo units Will request priority. this: 4. Three different mechanisms are commonly used for ¢P15° i. Daisy chaining : meee er and simple method. a. Daisy chaining method is cheap’ b. All master make use of the same line for bus request. c. The bus grant signal serially propagates through each master until it encounters the first one that isrequesting. ii, Parallel arbitration: The parallel arbitration consists: of Priority encoder and a decoder. In this mechanism, each bus arbiter hasa bus request output line and input line. iii, Independent priority : In this each master has separate pair of bus request and bus grant lines and each pair has a priority assigned to it. Que 1.6. | Discuss the advantages and disadvantages of polling | and daisy chaining bus arbitration schemes. | AKTU 2015-16, Mar! 10) OR Explain daisy changing method. Write its advantages and disadvantages. | ee Daisy chaining : 1. Inthis, all masters make use of the same line for bus request. 2 eee ie aap ee cere parr pa eo a etter sae tse the ganIntroduction 1-8 B(csiT-Sem-3) Highest priority Lowest priority Master 1 Master 2 Master N Bus Bus || ____ Bus access access access Togie logic logic Bus Bus grant grant —_————4 Bus request Controller + Bus busy 1 Fig 1. isy chaining method, ‘Advantages of daisy chaining : 1. Itis asimple and cheaper method. 2, Itrequires the least number of lines and this number is independent of the number of masters in the system. Disadvantages of daisy chaining : 3. The propagation time delay of bus grant signal is proportional to the number of masters in the system, This makes arbitration time slow and hence limits the number of master in the system. 2. The priority of the master is fixed by the physical location of master. 3. Failure of any one master causes the whole system to fail. Advantages of polling bus arbitration : 1. Ifthe one module fails entire system does not fail. 2. The priority can be changed by altering the polling sequence stored in the controller. Disadvantages of polling bus arbitration : 1. It requires more bus request and grant signals (2 x n signals for n modules). 2. Polling overhead can consume a lot of CPU time. Rogier Bus and Memory Transfer. ‘ _ Questions-Answers Long Answer Type and: Medium Answer ‘Type Gash oetare different reg transfer ? What ad) or store (Write) data. Memory transfer means to fetch (Re* she content from MeMOTY locgy: 2. ‘The read operation transfers acopy oft he oni to CPU. . tion from the CPy, format 3. The store operation transfers the word Os content of that loca" specific memory location, destroying P ter M. 4 "The memory word is symbolized by the lo Registers associated for memory transfer + transfor raddreserd 1. There are two registers associated for memory and data register. 3 ory locat 2 ‘The required information is selected from ee address. It is stored in the Address Registet aoe 4 The data is transferred to another register called Data Register (DR) 4. Consider a simple read operation, Read : DR « MIAR] ; j Here, the information is transferred into Data Register ee ee the memory word M selected by the addresses in Address Register (aR The write operation is denoted as, Write : MIAR] <— B Que 18. | Explain the operation of three state bus buffers nd AKTU 2016-17, Marks i show its use in design of common bus. Answer 1. A three state gate is a digital circuit that exhibits three states. 2. Two of the states are signals equivalent to logic 1 and 0, 3. The third state is a high-impedance state 4. The high-impedance state behaves like an open circuit, which meats) that the output is disconnected and does not have logie significance. 6 Three state gates may perform any conventional logic, such as AND ot NAND. 4 6. However, the one most commonly used in the desi rstemis the buffer gate. lesign of a bus sy: 7. The graphic symbol of a three state buffer gate is shown in Fig. 180B (csT-Sem-D) Introduet Output ¥ = A ifC High ifC =0 Normal input A input C Control inpu rigs 8, The control input determines the output state, 1 input is equal to 1, the i 9, When the control nC » the output is enabled and the gate behaves like any conventional buffer, with the output equal to the normal input. 1 input is 0, the output is di 10, When the control ‘put is disabled and the gats high state, regardless of the value in the normal input, —— 11, Alarge number of three state gate outputs can be connected with wires to form a common bus line without endangering loading effects, or Bus line for bit 0 Bo: If Co Do 4s elect {]°! 0 Select ae 7 2 Enable 45°02" 3] Fig. 1.8.2. 12, ‘The outputs of four buffe bus line. 13. The control inputs to the buffers determine which of the four normal inputs will communicate with the bus line. 14, Not more than one buffer may be in the active state at any given time. 15. To construct a common bus for four registers of n bits each using three state buffers, we need n circuits with four buffers in each. 16, Each group of four buffers receives one significant bit from the four registers. 17. Only one decoder is necessary to select between the four registers. are connected together to form a single 4 Que 1.9. | Explain why the single shared bus is so widely used as an interconnection medium in both sequential and parallel computers, What are its main disadvantages ? Answer Single shared bus is so widely used as an interconnection medium in both sequential and parallel computer because of following reasons : ' 1. The shared bus is the simplest and least expensive way of connecting several procs s to a set of memory modules.Computer O; re ganization & Arc] jitectul tion and high band, 2. Itallows compatibility and providesease of? “a, Disadvantages of single shared bus "aot ts throughout ln, 1. The main disadvantage of the shared bus ie iprocessor system, yt the performance boundary for the entire ea js granted, likely cay: because at any time only one memory 900° formance By re cheat fies is often assigned to some processors to remain idle. ory i the memory access traffic, a cache mem = 4 ate ign is that, if the bus fay, ‘Another disadvantage of the shared bus desien 1S Oe fa catastrophie failure results, The entire system will StoP MB Singg no processor will be able to access memory: QEeTIO] What is the benefit of using multiple bus architeotyy, compared to a single bus architecture ? ny | swer Following are the benefits of using multiple bus architecture compared, single bus architecture : . 1. Single bus have long control sequence because only the data item ean transferred over the bus in a clock cycle. To reduce the number of steps needed, most commercial processoe 2. provides multiple internal paths using multiple buses. 3. The introduction of incrementer unit eliminates the need to add port the PC using the main ALU. 4. By providing more paths for data transfer, a significant reduction in the number of clock cycles needed to execute an instruction is achieved. PART-5 Que 1.11, | Explain general-purpose register based organizatio® icate with each other a 1. _In this organization, the registers communi only for direct data transfers, but also while Performing various a ] ee) operations.Introduction wp csitsen®) External input R Re Rg Ry Rs Re By ‘T Load| SEL { tine] 4 Bto8 decoder MUXA MUXB Bus B jae B Bus A Arithmetic logic unit (ALU) }ore ae SELD Output (a) Block diagram 3 3 3 4 SELA | SELB | SELD | OPR (b) Control word /ii11\1. General-purpose register based organization, Seven registers are used for general purpose, the output of each register is connected to two multiplexer (MUXs) inputs. ‘Three select lines are used to select any one of the seven registers and the contents of selected registers are supplied to the inputs of ALU. ‘The buses A and B are used to form the inputs to the common arithmetic logic unit (ALU). ‘The operation to be performed is selected in the ALU andis determined by the arithmetic or logic micro-operation by using function select lines (OPR). ‘The result of the micro-operation is available as output data and also {oes into the inputs of all the registers. Any one of the destination register receives the information from the ‘output bus which is selected by a decoder.S/IT-Sem.8) 1-19 BC Architecture Computer Organization & ‘staok Organization: ve the “organization of register stack king of push and Que 142] What is stack? Gt Ea i ts and explain the with all necessary elements aT Marks pop operations. Answer 1 Astack isan accessed ata time. 2, The point of access is called # 3, The number of elements in the sta 4, Items may only be added or delete 5, Astack is also known asa pushdown ordered set of elements in which only one element can be tack. he top of the s of the stack is variable. ck or length from the top of the stack. list or a Last-In-First-Out (LIFO) Organization of register stack + Consider the organization of a 64-word register stack as illustrated in Fig L121. = Address when stack is fall 1 63 EMPTY L ; EMPIY=1 [ when stack is empty ‘Stack pointer (SP) ws Consists bits) | [XA ? ‘ABCD _| 1 Hale the dato be pushed ° stack or that is popped -—m| eit offfrom the stack ae DR) Fig. 1.12, i 1. Block diagram of 64-word stack.3) 14B (cSIT-Sem-d) Introduction ‘The four separate registers used in the organization are inter register (SP) : It contaj; 2 1. Stack Point ins avalue in binary each of 6 bits, which is Gencaars top of the stack. Here, the stack ster SP com cannot contai wnt ie., value 63. ‘ain a value greater than 2. FULL register :Itcan store 1 bit information, Its set to 1 when the stack is full. . 3, EMPTY register = It can store 1 bit information, It is set to 1 when stack is empty: 4. Data Register (DR) It holds the data to be written into or tobe read from the stack. Working of POP and PUSH: POP (Performed if stack is not empty ice, if EMPTY = 0): DR « MISP] Read item from the top of stack speSP-1 Decrement stack pointer 1f(SP=0)then (EMPTY <1) Check if stack is empty FULLCO Mark the stack not full PUSH (Performed if stack is not full i, if FULL = 0) : ‘SP<-SP+1 Increment stack pointer MISP] « DR Write item on top of the stack If (SP = 0) then (FULL < 1) Check if stack is full EMPTY <0 Mark the stack not empty ‘Que 1.13. | What is a memory stack ? Explain its role in managing subroutines with the help of neat diagrams. [ARTO R016-77, Marks 5 Answer Memory stack: Memrry stack is a series of memory spaces that is used in the processes that is done by processor and is temporarily stored in registers. Role in managing subroutines : 1. The stack supports progrom execution by maintaining automatic process-state data. If the main routine of a program, for example, invokes function a ( ), which in turn invokes function 6 ( ), function 6 ( ) will eventually return control to function a ( ), which in turn will return contro! to the main () function as shown in Fig. 1.13.1. 3, To return control to the proper location, the sequence of return addresses must be stored. 4. Astack is well suited for maintaining this information because it is a dynamic data structure that can support any level of nesting within memory constraints. lllFig? ick ini When a subr tack. execute in the calling routine is pushed onto the s' 6. When the subrouti locati A cation as stack, and program execution jumps to the specified lo inFig. 1.13.9, Low memory Unallocated [| Stack frame for b() | ——| Stack frame for a() Stack frame for main () High memory Fig. 1.13.2. Calling a subroutine. n maintained in the any given instant, In addition to the re! The informatio; the process at 10. When a subrouti; Que 1.14. | What is the stack org: nization? Compare register stad and memory stack. Answer Stack organization : Refer Q- 1.12, Page 1-138, Unit-1 aa rane t instructj, Outine is called, the address of the next 1 10N to i ss is popped from 4 ‘ine returns, this return addre: show’ stack reflects the execution state off b1-16B (CSIT-Sem-5) n register stack and memory stacl Register stack TT ister stacks are momentary | Memory stacks are a series of es for internal processes memory spaces that is used in spa : that are being done by the | the processes that ia dene by processor. Processor and are temporarily stored in registers. Register stack is generally on | Memory stack is on RAM. (CPU). ‘Access to register stackis faster. | Access to memory stack is slower. It is limited in size. __l tis large in size. @ue 1.45, | Explain an accumulator based central processing unit organization with block diagram, Answer Internal bus Flags General purpose registers an (r) <—=[_sP t vi Timing and control unit Fig. 1.15.1, Block diagram of accumulator based CPU organization. 1. ALU: A most generic computer system is composed of a unit to do arithmetic, shift and logical micro-operations commonly known as ALU of CPU. 2 Program Counter (PC) : This keeps track of the instruction address in memory from where the next instruction needs to be fetched. The 3, structions are stored in memory in an order decided by programmer. General purpose registers (R1, R2,R3) :It suggests that the registers are involved in operations like load inputs, store intermediate results of arithmetic, logical and shift micro-operations. The initial inputs are loaded into registers from memory and final results are later moved into memory.1-17B (CSAT-Sen, Computer Organization & Architecture m3) porary 4. Accumulator (ACC) : This block acts as Ae Ue SY Storage register location for all mathematical ee fier instruction is fot, che . Instruction Register IR and Decode! ster. The instruction; from the memory its stored in Instruction Regi iy then decode by the decoder. i i st & Stack pointer (SP) Stack pointer is involved in managing the stacy transfers during and program execution s ; 7. Timing and control unit : This block manages ay ‘CPU, alle a Erents on a timeline between various components of a CI al pow blocks are controlled in a manner to optimize the computational pore, ofthe unit by minimizing the failures ce 8 Flags: Flags are also cei or bits inside registers which are set o cleared for a particular condition on an arithmetic operation. Some of, he most common flags are : . Sign :Is used to identify the sot/reset of most significant bit of the result. . He Carry : Is used to identify, a carry during addition, or borrow during subtraction/comparison, iii, Parity : Set if the parity is even, Refer parity from here. jv. Zero :To identify when the result isenual te zone 9. Bus sub-system : ll the data transforeiniowvocn memory and CPU Feeisters including instruction fetches are carried over bus, Que 1.16. | Explain various types of processor organization. Answer Types of processor organization ; General-purpose register based : Refer Q. 1.1, Page 1-11B, Unit-1 2 Stack based: Refer Q. 1.12, Page 3B, Unit-1 3. Accumulator based : Refer Q. 1.15, Page 1-16B, Un PART-7 | | Addressing Modes Questions-Answ [ =f | Long Answer Type and Medium Answer TyPe Questions bibeee Ses Que L1 7.| Write short note on relative addressing mode . and eet addressing mode. indirec on: Explain the following addressing modes with the help of an example Register indirect &! Immediate ARTU 2014-15, Marks 10 xy simple form of addre Jd contain the effe of the operand: EA=A of the location Operand Fig. 1.17.1. Direct. 2. Adirect address in instruction needs two reference to memory = a Readinstruction _—b. Readoperand ii Displacement addressing = Disp\aery powerful mode of addressing combines the capabilities of ig and register indirect addressing. cfnames depending upon the content of ‘but the basic mechanism is the same. 3, Displacement addressing requires that the instruction have two ‘one of which is explicit. address fields, at leas 4, The value contained in one address field (value =A) is used directly. ference based on opcode, field or an implicit ret e contents are a 5. The other addre: dded to A to produce the refers to a register whos effective address. Instruction pri 4 4 Memory, > ea Operand Registers Fig. 1.17.2. Displacement addressing.Cactputer Organisation & Architecture 1-19 (CSIT-Sem.g) iii Relative addressing : 1. Relative addressing means that the next instruction to be earrieg out is sn offset number of locations away, relative to the addres of the current instruction. 2 Consider this bit of peondo-onte Jump +S if sccumulator = = 2 Code executed if accumulator is NOT = chanp + 5 (unconditional relative jump to avoid the next line of code) cv: onde executed if accumulator accumulator ~ has the value of 2 then the nest instruction is 3 This is called a conditional jump and it isn addressing, iv. Register indirect mode: L_ Register indirect mode is similar to indirect addressing, 2 The only difference is whether the address field refers to a memory location or a register. 3 Thus, for register indirect address, EA = (R) Instruction ing use of relative * R SS Memory hs Fig. 117.3: Register indirect, v. Implied mod: 1. Inthis mode, the operands are specified implicitly of the instruction. All register reference instructions that use an accumulator are implied mode instructior 3. Zeroaddress instructions in a stack-organized computer are implied mode instruction since the operands are implied to be on top of the stack. It is also known as stack addressing mode. the definition Top of stack register Fig. 1.17.4. Implied mode. vi. Immediate mode: 1. __Inthis mode, the operand is specified in the instruction itself. 2. The operand field contains the actual operand to be used in | conjunction with the operation specified in the instruction.Introduction vii Indener cifective address of th 1, The ef fectiv € operand i: hi constant value to the contents of a er icaiaey cided ‘The register used may be either a special regi for this purpost or more commonly, it may be any one of a perhiohary ia registersin the CPU. die 3. It is referred to as an index register. We indi i Bi exe indicate the index mode here X denotes a constant and R is the name of register i 4 The effective address of the operand is aera 5. Inthe process of generating the effective address, the contents of the index register are not changed. : Instruction Ry A T Memory le | fo hae Fig. 1.17.6. Indexed. Example: Address Memory PC = 200 200 [~ Load to AC_[Mode’ 201 | Address = 500 R1— 400 202 | Next instruction XR = 100 399 450 AC 400 700 500 800 600 900 702 325 800 300 Fig. 1.17.7.Immediate operand Indirect address Indexed address Register indirect Que 118.] What is aitterence between implied and immeding, Addressing modes ? Explain with an example. Answer diate implied Tmmet addressing mode addressing mode ; | No operand is specified in the | Operand is specified in the instruction. instruction itself. The operands are contained in an operands field rather than an address field. 2. |The operands are specified implicit in the definition of instruction, | 3. | This mode is used inallregister | This mode is very useful for reference instructions initializing the regi constant value. 4 | Example: ‘Example: The instruction “Complement | ‘The instruction : Accumulator” written as ; | MVL06 CMA. ADD 05 Que 1.19. ] Describe auto increment and auto decrement addressing modes with proper example ? Answer Auto increment mode : 1. _ In this mode the Effective Address EA) ofthe operand isthe content of a register specified in the instruction, 2 After accessing the operands, the contents of this register are incremented to point to the next item in the list, Example : Add (R2) +, ROIntroduction BicsiT Se Here the contents ee ‘i first used as an EA then these are incremented. ent ‘ ; ‘Auto deere i Tn this mode the contents of a register specified in the instruction are decremented. wnts are then used as the i ewe conten tsar 1 effective address of the operand. first deer the contents of R2 are remented ar veoperand ‘which is added to the content of Ro, i fnen aed son fr Gueias,] How addressing mode is significant for referring 2 List and explain different types of addressing modes. AKTU 2016-17, Marks 15 memory de is significant fo i iti 1, Theaddressing mode is s for referring memory asit is a code that tells the control unit how to obtain the Effective Address (EA) from the displacement. Addressing mode is a rule of calculation, or a function that use displacement as its main argument and other hardware component as {gach as PC, registers and memory locations) as secondary arguments and produce the EA as a result. gypes of addressing modes :Refer Q, 1.17, Page 1-17B, Unit-. SS VERY IMPORTANT QUESTIONS Following questions are very important. These questions may be asked in your SESSIONALS as well as UNIVERSITY EXAMINATION. Q.1. Draw a block diagram of a computer’s CPU showing all the basic building blocks such as program counter, accumulator, address and data registers, instruction register, control unit ete., and describe how such an hrrangement can work as a computer, if connected properly to memory, input/output ete. ans: Refer Q. 1.1 Q.2. Write a short note on bus arbitration. Ans: Refer Q. 1.5 nd disadvantages of polling and Q.3. Discuss the advantage jon schemes. daisy chaining bus arbitr Ans, Refer Q. 1.6.1-28B (CSIT-Sem-3) Computer Organization & Architecture id show — ffers an » bus bu! Q4. Explain the operation of three state its use in design of common bus. Ane Refer Q. 1.8, of register stack ization i f @5. What is stack ? Give the organization: n the working o with all necessary elements and exp) push and pop operations. Awe Refer Q. 1.19, a in managing Q.6. What i, 4 memory stack ? Explain its role subroutines with the help of neat diagrams. Aww: Refer Q. 1.13, Q7. Explain various types of processor organization. AM Refer Q. 1.16. Q.8. Explain the following addressing modes with the help of an example each ; i. Direct ii, Register indirect iii, Implied iv. Immediate v. Indexed ANS. Refer Q. 1.17, ing mode is significant for referring memory ? List and explain different types of addressing modes, Aus Refer Q. 1.20, ©©Osq-1B (CSAT-Sem.3) Computer Organization & Architecture Centra] Processing Unit (2 Marks Questions) 14, tei i oint in . What are the various ways of specifying the binary p a register ? ; nrc There are two ways of specifying the binary Pp register which are: . By giving it a fixed position, By employing a floating-point representation. 2 What are the various facts related to bus and bus system ? Various facts related to bus and bus system are: A bus system will multiplex & registers ofn bits each to progluce an n-line common bus, The number of multiplexers needed to. construct the bus is equal to n, the number of bits in each register. i. The size of each multiplexer must be & x 1, since it multiplexes data lines, Give various advantages of polling method, Various advantages of polling method are: The priority can be changed by altering the polling sequence stored in the controller. . Ifthe one module fails, entire syste does not fail Basic components of register transfer logic are; Registers and their functions i. Information Operations Control function What is the relation between bus width and numb, i transferred ? Sr ot bit Bus width isdirectly Proportional to the number of bit y transferre, The wider the data bus, then Sreater will be the number fa bie transferred at one time ute)E (cst-sem) tral Processing Unit ances —— oar memory transfei pas, Memon) transfer involves basic operation like fetch (read) or store emory ste). The fetch operation transfers a copy of content from Jocation to CPU. The store operation transfers the word information from CPU to specific memory location. Define bus transfer. ‘The data transfer between various blocks connected to the common Ak Te eed bus transfer. Common bus system is shared by all the units. explain control word. AKTU 2015-16, Marks 02 Ane Control word is defined as a word whose individual bits represent (rvarious control signals. Therefore each of the control s ps in the control sequence of an instruction defines a unique combination of 0s and 1s. 19, Compare register stack and memory stack. Register stack Memory stack 1. |Astack can be placed in a portion of a logical memory or can be organized as a collection of number of memory words or registers. The stack is implemented as a standalone and —_ also implemented as a random access memory attached to CPU. 2, |The stack pointer register (SP) contains a binary number whose value is equal toaddress of the word that is currently on top of the stack. ‘The implementation of a stack in the CPU is done by assigning a portion of memory to a stack operation. QO