03.10.
2022
VISVESVARAYA TECHNOLOGICAL UNIVERSITY, BELAGAVI
B.E: Electronics & Communication Engineering / B.E: Electronics & Telecommunication Engineering
NEP, Outcome Based Education (OBE) and Choice Based Credit System (CBCS)
(Effective from the academic year 2021 – 22)
VI Semester
Basic VLSI Design
Course Code 21EC653 CIE Marks 50
Teaching Hours/Week (L:T:P:S) 3:0:0:1 SEE Marks 50
Total Hours of Pedagogy 40 Total Marks 100
Credits 3 Exam Hours 3
Course objectives:
Impart knowledge of MOS transistor theory and CMOS technologies
Impart knowledge on architectural choices and performance trade-offs involved in designing and
realizing the circuits in CMOS technology
Cultivate the concepts of subsystem design processes
Demonstrate the concepts of CMOS testing
Teaching-Learning Process (General Instructions)
The sample strategies, which the teacher can use to accelerate the attainment of the various course
outcomes are listed in the following:
1. Lecture method (L) does not mean only the traditional lecture method, but a different type of
teaching method may be adopted to develop the outcomes.
2. Show Video/animation films to explain the functioning of various techniques.
3. Encourage collaborative (Group) Learning in the class
4. Ask at least three HOTS (Higher-order Thinking) questions in the class, which promotes critical
thinking
5. Adopt Problem Based Learning (PBL), which fosters students’ Analytical skills, develop thinking
skills such as the ability to evaluate, generalize, and analyze information rather than simply recall
it.
6. Show the different ways to solve the same problem and encourage the students to come up with
their own creative ways to solve them.
7. Discuss how every concept can be applied to the real world - and when that's possible, it helps
improve the students' understanding.
8. Incorporate programming examples given under Activity based learning.
Module-1
Introduction: A Brief History, MOS Transistors, MOS Transistor Theory, Ideal I-V Characteristics, Non-
ideal I-V Effects, DC Transfer Characteristics (1.1, 1.3, 2.1, 2.2, 2.4, 2.5 of TEXT2).
Fabrication: nMOS Fabrication, CMOS Fabrication [P-well process, N-well process, Twin tub process],
BiCMOS Technology (1.7, 1.8, 1.10 of TEXT1).
Teaching-Learning Chalk and talk method, YouTube videos, Power point presentation
Process RBT Level: L1, L2
Module-2
MOS and BiCMOS Circuit Design Processes: MOS Layers, Stick Diagrams, Design Rules and Layout.
Basic Circuit Concepts: Sheet Resistance, Area Capacitances of Layers, Standard Unit of Capacitance,
Some Area Capacitance Calculations, Delay Unit, Inverter Delays, Driving Large Capacitive Loads
(3.1 to 3.3, 4.1, 4.3 to 4.8 of TEXT1).
Teaching-Learning Chalk and talk method/Power point presentation
Process RBT Level: L1, L2, L3
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Module-3
Scaling of MOS Circuits: Scaling Models & Scaling Factors for Device Parameters
Subsystem Design Processes: Some General considerations, An illustration of Design Processes,
Illustration of the Design Processes: Regularity, Design of an ALU Subsystem, The Manchester Carry-
chain and Adder Enhancement Techniques
(5.1, 5.2, 7.1, 7.2, 8.2, 8.3, 8.4.1, 8.4.2 of TEXT1).
Teaching-Learning Chalk and talk method, YouTube videos, Power point presentation
Process RBT Level: L1, L2, L3
Module-4
Subsystem Design: Some Architectural Issues, Switch Logic, Gate (restoring) Logic, Parity Generators,
Multiplexers, The Programmable Logic Array (PLA)
(6.1 to 6.3, 6.4.1, 6.4.3, 6.4.6 of TEXT1).
FPGA Based Systems: Introduction, Basic concepts, Digital design and FPGAs, FPGA based System
design, FPGA architecture, Physical design for FPGAs (1.1 to 1.4, 3.2, 4.8 of TEXT3).
Teaching-Learning Chalk and talk method, YouTube videos, Power point presentation
Process RBT Level: L1, L2, L3
Module-5
Memory, Registers and Aspects of system Timing: System Timing Considerations, Some commonly
used Storage/Memory elements (9.1, 9.2 of TEXT1).
Testing and Verification: Introduction, Logic Verification, Logic Verification Principles,
Manufacturing Test Principles, Design for testability (12.1, 12.1.1, 12.3, 12.5, 12.6 of TEXT 2).
Teaching-Learning Chalk and talk method/Power point presentation
Process RBT Level: L1, L2, L3
Course outcome (Course Skill Set)
At the end of the course the student will be able to:
1. Demonstrate understanding of MOS transistor theory, CMOS fabrication flow and technology
scaling.
2. Draw the basic gates using the stick and layout diagrams with the knowledge of physical design
aspects.
3. Interpret Memory elements along with timing considerations
4. Demonstrate knowledge of FPGA based system design
5. Interpret testing and testability issues in VLSI Design
6. Analyze CMOS subsystems and architectural issues with the design constraints.
Assessment Details (both CIE and SEE)
The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is 50%.
The minimum passing mark for the CIE is 40% of the maximum marks (20 marks out of 50). A student
shall be deemed to have satisfied the academic requirements and earned the credits allotted to each
subject/ course if the student secures not less than 35% (18 Marks out of 50) in the semester-end
examination (SEE), and a minimum of 40% (40 marks out of 100) in the sum total of the CIE (Continuous
Internal Evaluation) and SEE (Semester End Examination) taken together.
Continuous Internal Evaluation:
Three Unit Tests each of 20 Marks (duration 01 hour)
1. First test at the end of 5th week of the semester
2. Second test at the end of the 10th week of the semester
3. Third test at the end of the 15th week of the semester
Two assignments each of 10 Marks
4. First assignment at the end of 4th week of the semester
5. Second assignment at the end of 9th week of the semester
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Group discussion/Seminar/quiz any one of three suitably planned to attain the COs and POs for 20
Marks (duration 01 hours)
6. At the end of the 13th week of the semester
The sum of three tests, two assignments, and quiz/seminar/group discussion will be out of 100 marks
and will be scaled down to 50 marks
(to have less stressed CIE, the portion of the syllabus should not be common /repeated for any of the
methods of the CIE. Each method of CIE should have a different syllabus portion of the course).
CIE methods /question paper is designed to attain the different levels of Bloom’s taxonomy as per
the outcome defined for the course.
Semester End Examination:
Theory SEE will be conducted by University as per the scheduled timetable, with common question
papers for the subject (duration 03 hours)
1. The question paper will have ten questions. Each question is set for 20 marks.
2. There will be 2 questions from each module. Each of the two questions under a module (with a
maximum of 3 sub-questions), should have a mix of topics under that module.
The students have to answer 5 full questions, selecting one full question from each module.. Marks scored
out of 100 shall be reduced proportionally to 50 marks
Suggested Learning Resources:
Text Books:
1. “Basic VLSI Design”- Douglas A Pucknell & Kamran Eshraghian, PHI, 3rd Edition.
2. “CMOS VLSI Design- A Circuits and Systems Perspective”, Neil H E Weste, David Harris, Ayan
Banerjee, 3rd Edition, Pearson Education.
3. “FPGA Based System Design”, Wayne Wolf, Pearson Education, 2004, Technology and Engineering.
Web links and Video Lectures (e-Resources)
https://nptel.ac.in/courses/117101058
https://nptel.ac.in/courses/117106093
https://youtu.be/9SnR3M3CIm4
https://nptel.ac.in/courses/108/107/108107129/
Activity Based Learning (Suggested Activities in Class)/ Practical Based learning
Wherever necessary Cadence/Synopsis/Menta Graphics tools must be used.
1.Write Verilog Code for the following circuits and their Test Bench for verification, observe the
waveform and synthesize the code with technological library with given Constraints*. Do the initial
timing verification with gate level simulation.
i. An inverter
ii. A Buffer
iii. Transmission Gate
iv. Basic/universal gates
v. Flip flop -RS, D, JK, MS, T
vi. Serial & Parallel adder
vii. 4-bit counter [Synchronous and Asynchronous counter]
2. Design an op-amp with given specification* using given differential amplifier Common source and
Common Drain amplifier in library** and completing the design flow mentioned below:
a. Draw the schematic and verify the following
i) DC Analysis
ii) AC Analysis
iii) Transient Analysis
b. Draw the Layout and verify the DRC, ERC
c. Check for LVS
d. Extract RC and back annotate the same and verify the Design.
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