Digital Logic Design

UNIT-3
Combinational Circuits
CONTENTS
• Analysis of combinational circuits, Design
Procedure – Binary Adders, Subtractors,
decoders, encoders, multiplexers,
demultiplexers, code converters.
• Basic PLD’s-ROM, PROM, PLA, PAL Realizations.

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Digital Logic Circuits
• A digital logic circuit is defined as the one in which voltages are assumed
to be having a finite number of distinct values. These are the basic
circuits used in most of the digital electronic devices like computers,
calculators, mobile phones etc.
• Digital logic circuits are often known as switching circuits, because in
digital circuits the voltage levels are assumed to be switched from one
value to another value instantaneously. These circuits are termed as logic
circuits, as their operation obeys a definite set of logic rules.
• Types of digital logic circuits are combinational logic circuits and sequential
logic circuits.

combinational logic circuit sequential logic circuit

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Analysis of combinational circuits
The analysis of combinational circuits can be
done as:

• Definition and Block diagram of combinational

circuits
• Types of combinational circuits
• Design procedure of combinational circuits

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What are combinational logic circuits?
• Combinational circuits are a basic collection of logic gates.
• The output of a combinational circuit depends on its present inputs only.
Combinational circuits perform a specific information processing operation
fully specified logically by set of Boolean functions.
• A combinational circuit consists of input variables, logic gates and output
variables. The logic gates accept signals from the inputs and generate signals
to the outputs.
• For ‘n’ input variables, there are ‘2n’ possible input combinations. For each
input combination, there is only one possible output combination.

Block diagram of a combinational logic circuit

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Different types of combinational logic circuits
There are three main types of combinational logic
circuits:

• Arithmetic and logical combinational circuits –

Adders, Subtractors, Multipliers, Comparators.
• Data handling combinational circuits – Multiplexers,
Demultiplexers, priority encoders, decoders.
• Code converting combinational circuits – Binary to
Gray, Gray to Binary, Binary to Excess 3, seven-
segment, etc.
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Design Procedure
The design procedure for combinational logic circuits
starts with the problem specification and comprises
the following steps:
• Determine required number of inputs and outputs
from the specifications. Assign letter symbols for input
and output variables.
• Derive the truth table for each of the outputs based on
their relationships to the input.
• Simplify the Boolean expression for each output. Use
Karnaugh Maps or Boolean algebra.
• Draw a logic diagram that represents the simplified
Boolean expression. Verify the design by analyzing or
simulating the circuit.

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Example: Is input greater than or equal to 5?
Specification: Design a circuit that has a 3-bit binary
input and a single output (Z) specified as follows:
– Z = 0, when the input is less than 510
– Z = 1, otherwise
Step1: Determine the inputs and Outputs
– Label the inputs (3 bits) as A, B, C
• A is the most significant bit
• C is the least significant bit
– The output (1 bit) is Z
• Z = 1 -> 1012, 1102, 1112
• Z = 0 -> other inputs

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 A B C Z
Step2: Derive the Truth Table 0 0 0 0
0 0 1 0
0 1 0 0
Step 3: Simplify the Boolean Expression 0 1 1 0
1 0 0 0
From the truth table, one of the following
1 0 1 1
two methods to obtain the simplified
1 1 0 1
Boolean expression. 1 1 1 1
– Use Karnaugh Map to minimize the logic or
– From the truth table, get the Canonical Sum of
Products Boolean expression.
Z = A * ~B * C + A * B * ~C + A * B * C
– Use Boolean Algebra to simplify the Boolean
expression to: Z = (B + C) * A
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Step 4: Draw the logic diagram
Draw a logic diagram that represents the
simplified Boolean expression. Verify the design
by analyzing or simulating the circuit.

Boolean Expression: Z = (B + C) * A

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Arithmetic Circuits
• Combinational Arithmetic Circuits perform
arithmetic functions like Addition, Subtraction
and Multiplication i.e., the logic circuits which are
used for performing the digital arithmetic
operations such as addition, subtraction,
multiplication and division are called ‘arithmetic
circuits’.

• They are structured or array combinational

circuits. For example, an n-bit adder is made up
of a 1-dimensional array of 1-bit full adders.

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Adders
• An adder is a device that will add together two bits and give the
result as the output.
• There are two kinds of adders - half adders and full adders.
– A half adder just adds two bits together and gives a two-bit output.
– A full adder adds two inputs and a carried input from another adder,
and also gives a two-bit output.
Truth Table:
Half adder:

Logic Equations:

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Logic Circuit:
Half adder using Universal gates

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Full adder:

Logic Symbol

Logic Equation:

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Full Adder using two Half Adders:

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Full adder using Universal gates

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 Subtractors
The logic circuits used for binary subtraction, are known as binary
subtractors. There are two kinds of subtractors.
– A half subtractor is a combinational circuit which is used to perform
the subtraction of two bits.
– A full subtractor a combinational circuit that performs the subtraction
of three binary digits.
Truth Table:
Half subtractor:
0–0=0
0 – 1 = 1, borrow 1
1–0=1
1–1=0
Logic Equations:

Logic Circuit:

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Half subtractors using Universal gates

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 Truth Table
Full subtractor:

Logic Symbol

Logic Equation:

Logic diagram:

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Half Adder S = A’B + AB’ = A xor B
C = AB

Full Adder S = ABC + A’B’C + A’BC’ + AB’C’ = A xor B xor C

Co = A’BC + AB’C + ABC’ + ABC = AB + BC + CA = AB + (A xor B)C

Half Subtractor D = A xor B

Bo = A’B

Full Subtractor D = ABC + A’B’C + A’BC’ + AB’C’ = A xor B xor C

Bo = A’B’C + A’BC’ + A’BC + ABC = A’B + A’C + BC = A’B + (A xnor B)C

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Full subtractors using two Half subtractors:

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Full subtractor using Universal gates

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Binary Adder – 4 bit parallel adder

These full adders perform

the addition of two 4-bit
binary numbers. The sum
outputs are provided for
each bit and the resultant
carry (C4) is obtained
from the fourth bit.
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Binary Adder-Subtractor

The circuit consists of 4 full adders since we are performing operation on 4-bit numbers.
There is a control line K that holds a binary value of either 0 or 1 which determines that
the operation being carried out is addition or subtraction.

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 The first full adder has control line directly as its input(input carry C0), The input A0
(The least significant bit of A) is directly input in the full adder. The third input is the
xor of B0 and K (S in fig. But do not confuse it with Sum-S).

The two outputs produced are Sum/Difference (S0) and Carry (C1). If the value of K
(Control line) is 1, the output of B0(xor) K=B0′(Complement of B0). Thus the operation
would be A+(B0′). Now 2’s complement subtraction for two numbers A and B is given
by A+B’. This suggests that when K=1, the operation being performed on the four bit
numbers is subtraction.

Similarly If the Value of K=0, B0 (xor) K=B0. The operation is A+B which is simple
binary addition. This suggests that When K=0, the operation being performed on the
four bit numbers is addition. Then C0 is serially passed to the second full adder as
one of it’s outputs.

The sum/difference S0 is recorded as the least significant bit of the sum/difference.

A1, A2, A3 are direct inputs to the second, third and fourth full adders. Then the third
input is the B1, B2, B3 XORed with K to the second, third and fourth full adder
respectively. The carry C1, C2 are serially passed to the successive full adder as one of
the inputs. C3 becomes the total carry to the sum/difference. S1, S2, S3 are recorded
to form the result with S0.

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 Example: Lets take two 3 bit numbers A=010 and B=011 and input them in the full
adder with both values of control lines.

For K=0 For K=1

B0(xor)K = B0 and C0=K=0 B0(xor)K=B0' and C0=K=1

Thus from first full adder Thus S0=1 and C1=0

= A0+B0
= 0+1 Similarly,
= 1, S1=1 and C2=0
S0=1 S3=1 and C3=1
C1=0
Thus, A = 010 = 2, B = 011
Similarly, = 3
S1=0 with C2=1 Sum(Difference) = 1111 = -1
S2=1 and C3=0

Thus, A = 010 =2, B = 011 = 3

Sum = 0101 = 5
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 Serial Binary Adder
Serial binary adder performs the addition of two
binary numbers in serial form. Serial binary adder
performs bit by bit addition. Two shift registers
are used to store the binary numbers that are to
be added. A single full adder is used to add one
pair of bits at a time along with the carry. The
carry output from the full adder is applied to a D
flip-flop. After that output is used as carry for next
significant bits. The sum bit from the output of
the full adder can be transferred into a third shift
register.

Working Process:
Following is the procedure of addition using serial binary adder:
Step-1: The two shift registers A and B are used to store the numbers to be added.
Step-2: A single full adder is used to add one pair of bits at a time along with the carry.
Step-3: The contents of the shift registers shift from left to right and their output starting from a and b
are fed into a single full adder along with the output of the carry flip-flop upon application of each
clock pulse.
Step-4: The sum output of the full adder is fed to the most significant bit of the sum register.
Step-5: The content of sum register is also shifted to right when clock pulse is applied.
Step-6: After applying four clock pulse the addition of two registers (A & B) contents are stored in sum
register.
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 BCD Adder
BCD stands for binary coded decimal. Consider two 4-bit numbers A and B. The value of A
and B can varies from 0(0000 in binary) to 9(1001 in binary) because we are considering
decimal numbers. The output will varies from 0 to 18, if we are not considering the carry
from the previous sum. But if we are considering the carry, then the maximum value of
output will be 19 (i.e. 9+9+1 = 19). When we are simply adding A and B, then we get the
binary sum. Here, to get the output in BCD form, we will use BCD Adder.

Example 1: Example 2:
Input : A = 0111 B = 1000 Input : A = 0101 B = 1001
Output : Y = 1 0101 Output : Y = 1 0100
Explanation: We are adding A(=7) and Explanation: We are adding A(=5) and
B(=8). B(=9).
The value of binary sum will be The value of binary sum will be
1111(=15). 1110(=14).
But, the BCD sum will be 1 0101, But, the BCD sum will be 1 0100,
where 1 is 0001 in binary and 5 is where 1 is 0001 in binary and 4 is
0101 in binary. 0100 in binary.

Note – If the sum of two number is less than or equal to 9, then the value of BCD sum
and binary sum will be same otherwise they will differ by 6(0110 in binary).
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Now, lets move to the table and find out the logic
when we are going to add “0110”.
We are adding “0110” (=6) only to the second
half of the table.
The conditions are:
If C’ = 1 (Satisfies 16-19)
If S3′.S2′ = 1 (Satisfies 12-15)
If S3′.S1′ = 1 (Satisfies 10 and 11)
So, our logic is C' + S3'.S2' + S3'.S1' = 1

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DECODERS
⚫ A decoder has
− N inputs
N
− 2 outputs
⚫ A decoder selects one of 2N outputs by decoding the
binary value on the N inputs.
⚫ The decoder generates all of the min-terms of the N
input variables.
− Exactly one output will be active for each
combination of the inputs.

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2x4 Decoder:
Functional Table of 2x4 Decoder

Logic Diagram

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2x4 decoder with enable input:
Functional Table Logic Diagram
Inputs Outputs
EN I1 I0 Y3 Y2 Y1 Y0
0 X X 0 0 0 0
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0

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3x8 decoder
Inputs outputs

X Y Z D7 D6 D5 D4 D3 D2 D1 D0

0 0 0 0 0 0 0 0 0 0 1

0 0 1 0 0 0 0 0 0 1 0

0 1 0 0 0 0 0 0 1 0 0

0 1 1 0 0 0 0 1 0 0 0

1 0 0 0 0 0 1 0 0 0 0

1 0 1 0 0 1 0 0 0 0 0

1 1 0 0 1 0 0 0 0 0 0

1 1 1 1 0 0 0 0 0 0 0

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Three-to-eight-line decoder

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3x8 decoder using two 2x4 decoders
• The inputs A0 and A1 are
connected as parallel inputs for
both the decoders and then the
Enable pin of the Second Decoder is
made to act as A2 (third input).

• The Inverted signal of A2 is given to

the Enable pin of first decoder to
get the outputs Y0 to Y3. Here the
outputs Y0 to Y3 are referred as
Lower four min-terms and the
outputs Y4 to Y7 are referred as
higher four min-terms.

• The lower order min-terms are

obtained from the first decoder and
the higher order min-terms are
obtained from the second decoder.

Logic Diagram
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4x16 decoder
Inputs outputs

D C B A Y15 Y14 .. .. Y3 Y2 Y1 Y0

0 0 0 0 0 0 0 0 0 0 0 1

0 0 1 1 0 0 0 0 1 0 0 0

..

0 1 1 1

1 0 0 0

1 0 0 1

1 1 1 0 0 1 0 0 0 0 0 0

1 1 1 1 1 0 0 0 0 0 0 0

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4x16 decoder using 3x8 decoder

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2x4 decoder with active low output

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BCD to Seven Segment decoder
Display devices are used to provide display of numbers, alphabets and symbols in response to
electrical input and are called as Electronic Display Systems. This display device accept input in
the form of BCD number and display the particular number on the display.

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The K-map method can be used to derive the logic expression of the decimal numbers for display.

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Implementation of Full Adder using
Decoder
Inputs Outputs S = ∑m(1,2,4,7)
x y z C S C = ∑m(3,5,6,7)
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
3:8
1 1 1 1 1 Decoder

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 Encoders
⚫ An encoder has
− 2N inputs
− N outputs
⚫ An encoder outputs the binary value of the selected
(or active) input.
⚫ An encoder performs the inverse operation of a
decoder.
⚫ The encoder can be implemented with OR gates whose
inputs are determined directly from the truth table.
Output z is equal to 1 when the input octal digit is 1, 3,
5,or 7. Output y is 1 for octal digits 2, 3, 6, or 7, and
output x is 1 for digits 4, 5, 6, or 7.

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 Octal to Binary Encoder
The encoder can be implemented with OR gates whose inputs are determined directly from
the truth table. Output Y0 is equal to 1 when the input octal digit is 1, 3, 5,or 7. Output Y1 is
1 for octal digits 2, 3, 6, or 7, and output Y2 is 1 for digits 4, 5, 6, or 7.

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 Octal to Binary Encoder
⚫ Issues
− What if more than one input is active?
− (111 000 00)
− What if no inputs are active?
− (000 000 00)
That is the octal to binary encoder has two limitations:
1. Only one input can be active at any given time. If two or more inputs are
equal to 1 at the same time, the O/P is undefined. For example if O2 and O5 are active
simultaneously, the o/p of encoder will be 111 that is equal to binary 7. This does
not represent binary 2 or 5.
2. The output with all 0’s is generated when all inputs are ‘0’, and is also
true when O0 = ‘1’.

The first problem is taken care by a circuit, called as ‘priority encoder’. It establishes a
priority to ensure that only one input is active (High) at a given time.
The second problem is taken care by an extra line in the encoder output, called ‘valid
output indicator’ that specifies the condition that none of the inputs are active.
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 Priority Encoders
⚫ If more than one input is active, the higher-order
input has priority over the lower-order input.
− The higher value is encoded on the output
⚫ A valid indicator, v, is included to indicate whether or
not the output is valid.
− Output is invalid when no inputs are active
⚫ v=0
− Output is valid when at least one input is active
⚫ v=1

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 Boolean Expressions

Inputs Outputs

D3 D2 D1 D0 x y V

0 0 0 0 X X 0

0 0 0 1 0 0 1

0 0 1 X 0 1 1

0 1 X X 1 0 1

1 X X X 1 1 1

Logic Diagram
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 Multiplexers
⚫ A multiplexer has
− N control inputs(Select lines)
− 2N data inputs
− 1 output
⚫ A multiplexer routes (or connects)
the selected data input to the
output.
− The value of the control inputs
determines the data input that
is selected.

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 2X1 Multiplexer
S F
(Select
Line)
0 I0

1 I1

Logic Diagram and

Truth table
Data
inputs
Control Z = S′.I0 + S.I1
input
A two-to-one-line multiplexer connects one of two 1-bit
sources to a common destination. The circuit has two data
input lines, one output line, and one selection line S . When
S = 0, the upper AND gate is enabled and I0 has a path to
the output. When S = 1, the lower AND gate is enabled and
I1 has a path to the output. Y = S′.I0 + S.I1
The multiplexer acts like an electronic switch that selects
one of two sources.
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4X1 Multiplexer A
Select Line
B
O/P
F
(S1) (S0)
0 0 I0
0 1 I1
1 0 I2
1 1 I3

MSB LSB

Z = A′.B'.I0 + A'.B.I1 + A.B'.I2 + A.B.I3

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 8X1 Multiplexer
Select Line O/P
A B C F
(S2) (S1) (S0)
0 0 0 I0
0 0 1 I1
0 1 0 I2
0 1 1 I3
1 0 0 I4
1 0 1 I5
1 1 0 I6
1 1 1 I7

MSB LSB

Z = A′.B'.C'.I0 + A'.B'.C.I1 + A'.B.C'.I2 + A'.B.C.I3 +

A.B'.C'.I4 + A.B'.C.I5 + A'.B.C'.I6 + A.B.C.I7
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 Logic Diagram of 8x1 Multiplexer

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 8X1 MUX using two 4X1 MUXs

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 8X1 MUX using 2X1 MUXs : This consists of 8 inputs and 3 select lines

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16x1 MULTIPLEXER USING Two 8X1 MUX 16x1 MULTIPLEXER USING Five 4X1 MUX

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 Demultiplexers Out0 W
W = A'.B'.I
Out1 X
⚫ A demultiplexer has I In X = A.B'.I
Out2 Y
− N control inputs
− 1 data input Out3 Z Y = A'.B.I
S1 S0
− 2N outputs Z = A.B.I
⚫ A demultiplexer routes (or
connects) the data input to A B
the selected output.
− The value of the
control inputs Select Line Outputs
determines the A B W X Y Z
output that is (S1) (S0)
selected. 0 0 I 0 0 0
⚫ A demultiplexer performs 0 1 0 I 0 0
the opposite function of a 1 0 0 0 I 0
multiplexer. 1 1 0 0 0 I

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 W = A'.B'.I
X = A.B'.I
Y = A'.B.I
Z = A.B.I

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1-line to 4-line Demultiplexer 1-line to 8-line Demultiplexer

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 Designing logic circuits using multiplexers
Using an n-input Multiplexer:
⚫ Use an n-input multiplexer to realize a logic circuit for a
function with n minterms.
− m = 2n, where m = # of variables in the function
⚫ Each minterm of the function can be mapped to an input
of the multiplexer.
⚫ For each row in the truth table, for the function, where
the output is 1, set the corresponding input of the
multiplexer to 1.
− That is, for each minterm in the minterm expansion of the
function, set the corresponding input of the multiplexer to 1.
⚫ Set the remaining inputs of the multiplexer to 0.
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Example: Implement the following function
with multiplexer.
Y = F (A, B, C, D) = Σm (0, 1, 3, 4, 8, 9, 15)

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Using an (n / 2)-input Multiplexer:

⚫ Use an (n / 2)-input multiplexer to realize a logic circuit for a

function with n minterms.
− m = 2n, where m = # of variables in the function
⚫ Group the rows of the truth table, for the function, into (n / 2)
pairs of rows.
− Each pair of rows represents a product term of (m – 1) variables.
− Each pair of rows can be mapped to a multiplexer input.
⚫ Determine the logical function of each pair of rows in terms
of the mth variable.
− If the mth variable, for example, is x, then the possible values are x,
x', 0, and 1.

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Using an (n / 2)-input Mux
Example: F(x,y,z) = Sm(1, 2, 6, 7)

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 Using an (n / 2)-input Mux

Example: F(A,B,C,D) = Sm(1,3,4,11,12,13,14,15)

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Code Converters
Coding was defined as the use of groups of bits to represent items of information that
are multi-valued. Assigning each item of information a unique combination of bits
makes a transformation of the original information. This we recognize as information
being processed into another form. Moreover, we have seen that there are many
coding schemes exist. Different digital systems may use different coding schemes. It is
sometimes necessary to use the output of one system as the input to other.
Therefore a sort of code conversion is necessary between the two systems to make
them compatible for the same information.

A code converter is a combinational logic circuit that changes data presented in one
type of binary code to another type of binary code.’ A general block diagram of a code
converter is shown in Fig.
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 Example: 4-bit Binary to Gray code conversion
It has four inputs (B3 B2 B1 B0) representing
4-bit binary numbers and four outputs (G3
G2 G1 G0) representing 4-bit gray code.

Now all the gray outputs distantly solved

with respect to binary inputs From the
truth table; the logic expressions for the
gray code outputs can be written as

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The above expressions can be simplified using K-map

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Now the above expressions can be implemented using X-OR gates to yield the
desired code converter circuit shown in Fig.

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 Example: XS-3 to BCD code converter
The block diagram of an XS-3 to BCD code
converter is shown in Fig. It has four
inputs (E3, E2, E1, E0) representing 4 bit
XS-3 number and four outputs (B3B2 B1
B0) representing 4-bit BCD code.

XS-3 codes are obtained from BCD code by

adding 3 to each coded number. Moreover
4 binary variables may have 16
combinations, but only 10 are listed. The six
not listed are don’t care-combinations.
Since they will never occur, we are at liberty
to assign to the output variable either a 1
or a 0, whichever gives a simpler circuit. In
this particular example, the unused i/o
combinations are listed below the truth
table.
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 The expressions for BCD outputs (B3
B2 B1 B0) can be implemented for
terms of inputs (E3 E2 E1 E0) to form
a XS-3 to BCD code converter circuit.
The implementation is left as an
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PARITY BIT GENERATOR

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PARITY BIT GENERATOR Odd parity generator
Even parity generator

Functional Table
Functional Table

Logic Diagram
Logic Diagram
This can be drawn by finding Boolean Expression through 3 variable K-Map
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 PARITY BIT GENERATOR/CHECKER

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 PROGRAMMABLE LOGIC DEVICES(PLD’s)

• Contains an array of AND gates and OR

gates

• Advantages:
➢ Low cost
➢ Design a larger circuit
➢ Reprogramming
(Modify the design)
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TYPES OF PLD’s:

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PROM
• Contains an fixed AND array & Programmable OR
array gates.

• AND gate will generate 2n product terms by using

2n AND gates having n inputs each by using
nx2n decoder. So, this decoder generates ‘n’ min
terms.

• OR GATE: we can program any number of required

product terms, since all the outputs of AND gates
are applied as inputs to each OR gate. Therefore, the
outputs of PROM will be in the form of sum of min
terms
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PAL
• Contains an Programmable AND array &
Fixed OR array gates.

• Each AND gate has both normal and complemented

inputs of variables. So, based on the requirement,
we can program any of those inputs. So, we can
generate only the required product terms by using
these AND gates.

• OR GATE: So, the number of inputs to each OR gate will

be of fixed type. Hence, apply those required product
terms to each OR gate as inputs. Therefore, the outputs
of PAL will be in the form of sum of products form.
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 PAL PROGRAMMING TABLE
Product Inputs Outputs
Terms
X1 X2 X3 F1 F2
P1(X1X2X3’) 1 1 0

P2(X1’X2X3) 0 1 1

P3(X1’X2’) 0 0 -
P4(X1X2X3) 1 1 1

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 PAL PROGRAMMING TABLE
Product Inputs Outputs
Terms
X1 X2 X3 F1 F2
P1(X1X2X3’) 1 1 0 1 -

P2(X1’X2X3) 0 1 1 1 -

P3(X1’X2’) 0 0 - - 1
P4(X1X2X3) 1 1 1 - 1

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PLA
• Contains an Programmable AND array & Programmable
OR array gates.

• Each AND gate has both normal and complemented

inputs of variables. So, based on the requirement, we
can program any of those inputs. So, we can generate
only the required product terms by using these AND
gates.

• OR GATE: we can program any number of required product

terms, since all the outputs of AND gates are applied as
inputs to each OR gate. Therefore, the outputs of PLA will
be in the form of sum of min terms

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 PLA PROGRAMMING TABLE
Product Inputs Outputs
Terms
X Y Z A B
P1(XY) 1 1 - 1 -
P2(XZ’) 1 - 0 1 1
P3(XY’) 1 0 - - 1
P4(YZ) - 1 1 - 1

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Implement the following function using PLA and draw its Programming Table

Solution:

PLA Programming Table

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 Implement the following functions using PAL.

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 Implement the following functions using 3-input, 3 product terms and 3 output PAL.

F1(A, B, C) = σ(0,1,6,7)
F2(A, B, C) = σ(1,2,4,6)
F3(A, B, C) = σ(2,6)

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 Implement the following functions using PROM.

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 References
• https://www.elprocus.com/different-types-of-digital-logic-circuits/
• https://technobyte.org/sequential-combinational-logic-circuits-types/
• Kumar, A. Anand. Switching Theory and Logic Design. PHI Learning Pvt.
Ltd., 2014.
• http://electronics-course.com/combinational-logic-design
• https://electronicscoach.com/half-adder.html
• https://www.gatevidyalay.com/tag/full-adder-using-nand-gates/
• A.K. Singh, Foundation Of Switching Theory And Logic Design, New Age
International (P) Limited, 2007.
• https://www.geeksforgeeks.org/digital-electronics-logic-design-tutorials/
• M Morris Mano, Michael D. Ciletti. Digital design: with an introduction to
the verilog HDL, Pearson Publishing, 2013.

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