Chapter 2: Programmable Logic Device
Logic circuit design review
• Sum of Product
• To get the desired canonical SOP expression we will add the minterms
(product terms) for which the output is 1.
• F = A’B + AB’ + AB
• Product of Sums (POS)
• To get the desired canonical POS expression we will multiply the maxterms
(sum terms) for which the output is 0.
• F = (A+B) . (A’+B’)
Simple Programmable Logic Device (SPLD)
• Programmable Array Logic (PAL)
• Generic Array Logic (GAL)
• The structure of PAL and GAL is composed of the programmable AND
followed by the programmable OR gate.
• PAL, GAL can be used to configure the Sum of Product logic circuit.
Input lines
Input buffer
A B A B A A B B
A B A B A
Fix connection
B
Product
2
X 2 X=AB+AB+AB
X=AB+AB+AB term
lines
2
Fuse blown Fuse intact
(noconnection) (connection)
Example of PAL configuration
PAL /GAL
Macrocell
Or array
I1
OR Output
I2 Programmable logic O1
GATE
I3 logic array
PAL: one time OR Output
programmable GATE logic O2
GAL:
reprogrammable
OR Output
logic O3
GATE
In-1 OR Output
In logic Om
GATE
Macrocell
Tristate control Tristate control
From Output/input
From output and gate
and gate array
array
Tristate control
From Output/input
and gate
array
Programmable fuse
Complex Programmable Logic Device (CPLD)
• CPLD is consist of SPLDs
Logic Array Logic Array
I/O block (LAB) block (LAB) I/O
SPLD SPLD
Logic Array Logic Array
I/O block (LAB) block (LAB) I/O
PIA
SPLD SPLD
Programmable
Interconnect
Logic Array array Logic Array
I/O block (LAB) block (LAB) I/O
SPLD SPLD
Logic Array Logic Array
I/O block (LAB) block (LAB) I/O
SPLD SPLD
Field Programmable Gate Array)
Programmable Configurable Logic Block (CLB)
interconnections
IO IO IO IO
block block block block
IO IO
block block
CLB CLB CLB CLB
IO IO
block block
CLB CLB CLB CLB
IO IO
block block
CLB CLB CLB CLB
IO IO
block block
IO IO IO IO
block block block block
FPGA
CLB
CLB CLB
Logic module Logic module
Logic module Logic module
Logic module Logic module
Local Local
interconnect interconnect
Logic module Logic module
Global column
Global row
interconnect
interconnect
Logic Module – Lookup table (LUT)
Logic section LUT
Memory cells
A 2A1A0 1
A0 SOP
A 2A1A0 0
A1 output
I/O A 2A1A0 0
A2 LUT Associated A0 A 2A1A0 1 SOP
logic A1
A2 A 2A1A0 0 output
An-1
Logic module A 2A1A0 1
A 2A1A0 0
A 2A1A0 1 A2 A1 A0 A2 A1 A0 A2 A1 A0 A2 A1 A0
LUT
A2 A1 A0 A2 A1 A0 A2 A1 A0 A2 A1 A0 A2 A1 A0
Logic section LUT
Memory cells
A2A1A0 0
A2A1A0 1
A2A1A0 0
A0 A2A1A0 1
A1 SOP
A2 A2A1A0 1 output
A2A1A0 1
A2A1A0 1
A2A1A0 0
