Lecture-10

Field Effect Transistors (FET)

(Part-ii)
Martha T/Giorgis
Addis Ababa University
Addis Ababa Institute of Technology
School of Electrical and Computer Engineering

Applied Electronics I
ECEG-2131

2019/20AY, Semester-I
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 Overview

Overview

1 Overview

2 Objective
Enhancement-Type MOSFET

3 DC Biasing
FET Biasing
D-Type MOSFET Biasing
E-Type MOSFET Biasing

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 Objective

Lecture Objectives

In this lecture you will learn the following:

The structure and operation of the pn junction
A basic semiconductor structure that implements the diode and
plays a dominant role in semiconductors.

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 Objective

Enhancement-Type MOSFET Construction

The Drain (D) and Source (S)

connect to the to n-doped
regions.
The Gate (G) connects to the
p-doped substrate via a thin
insulating layer of SiO2
There is no channel
The n-doped material lies on a
p-doped substrate that may
have an additional terminal
connection called the
Substrate (SS)

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 Objective Enhancement-Type MOSFET

For VGS = 0, ID = 0 (no channel).

For VDS some positive voltage, and
VGS = 0, two reverse biased p-n
junctions and no significant flow
between drain and source.
For VGS > 0 and VDS > 0, the
positive voltage at gate pressure
holes to enter deeper regions of the
p-substrate, and the electrons in
p-substrate will be attracted to the
positive gate.
The level of VGS that results in the
significant increase in drain current
is called threshold voltage (VT ).
For VGS < VT , ID = 0mA.

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 Objective Enhancement-Type MOSFET

Basic Operation of the E-Type MOSFET

The enhancement-type MOSFET operates only in the enhancement mode.

VGS is always positive.
As VGS increases, ID increases
As VGS is kept constant and
VDS is increased, then ID
saturates (IDSS ) and the
saturation level, VDSsat is
reached
VDSsat can be calculated by:

VDSsat = VGS − VT

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 Objective Enhancement-Type MOSFET

E-Type MOSFET Transfer Curve

To determine ID given VGS : ID = k(VGS − VT )2

Where: VT = threshold voltage or voltage at which the MOSFET turns on
k, a constant, can be determined by using values at specific point and the
formula:
ID(ON )
k=
(VGS(ON )−VT )2
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 Objective Enhancement-Type MOSFET

E-Type MOSFET Transfer Curve

ID(ON )
k= ID = k(VGS − VT )2
(VGS(ON )−VT )2
Substituting ID(on) = 10mA when VGS(on) = 8V from the characteristics:
10mA
k= = 0.278 × 10−3 A/V 2 → ID = 0.278 × 10−3 (VGS − 2)2
(8 − 2)2
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 Objective Enhancement-Type MOSFET

p-Channel E-Type MOSFETs

The p-channel enhancement-type MOSFET is similar to the n-channel,

except that the voltage polarities and current directions are reversed.

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 Objective Enhancement-Type MOSFET

MOSFET Symbols

Figure 1: Symbols for (a) n-channel enhancement-type MOSFETs and (b)

p-channel enhancement-type MOSFETs.
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 Objective Enhancement-Type MOSFET

Basic Current Relationships

For all FETs:

IG ∼
= 0A
ID = IS
For JFETS and D-Type MOSFETS:

VGS 2
 
ID = IDSS 1 −
VP

For E-Type MOSFETs:

ID = k(VGS − VT )2

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 DC Biasing FET Biasing

Fixed-Bias Configuration

IG ∼
= 0A
VDS = VDD − ID RD
VS = 0, VD = VDD , VGS = −VGG
VGS 2
 
ID = IDSS 1 − Figure 2: Network for dc analysis.
VP
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 DC Biasing FET Biasing

VGS 2
 
ID = IDSS 1 −
VP

Figure 3: Plotting Shockley’s equation. Figure 4: Finding the solution for the
fixed-bias configuration.
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 DC Biasing FET Biasing

Example (1)
Find VGSQ , IDQ , VDS , VD , VG , VS .

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 DC Biasing FET Biasing

Example (1)
Find VGSQ , IDQ , VDS , VD , VG , VS .

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 DC Biasing FET Biasing

Self-Bias Configuration

Figure 5: DC analysis of the self-bias

configuration.
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 DC Biasing FET Biasing

VGS = −ID RS
 2
ID = IDSS 1 − VVGS
P

−ID Rs 2
 
ID = IDSS 1 −
VP

ID R s 2
 
ID = IDSS 1 +
VP
By squaring and rearranging, ID
has the form:
2
ID + k1 ID + k2 = 0 [Solve for ID ]
Figure 6: DC analysis of the self-bias
configuration.
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 DC Biasing FET Biasing

Self-Bias Configuration - graphical solution

Sketch the transfer curve.

Draw the line:

VGS = −ID RS

The Q-point is located where

the line intersects the transfer
curve.
Use the value of ID at the
Q-point (IDQ ) to solve for the
other voltages:
VDS = VDD − ID (RS + RD )
V S = ID R S
VD = VDS + VS
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 DC Biasing FET Biasing

Voltage-Divider Bias

IG = 0A Figure 7: Redrawn network for dc

IR1 = IR2 analysis.

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 DC Biasing FET Biasing

Voltage-Divider Bias

VG is equal to the voltage across

divider resistor R2 :
R2 VDD
VG =
R1 + R2
Using Kirchhoff’s Law:

VGS = VG − ID RS

The Q-point is established by

plotting a line that intersects the
transfer curve. Figure 8: Redrawn network for dc
analysis.

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 DC Biasing D-Type MOSFET Biasing

D-Type MOSFET Bias Circuits

Depletion-type
MOSFET bias circuits
are similar to those used
to bias JFETs.
The only difference is
that depletion-type
MOSFETs can operate
with positive values of
VGS and with ID values
that exceed IDSS .

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 DC Biasing E-Type MOSFET Biasing

E-Type MOSFET Bias Circuits

The transfer characteristic

for the e-type MOSFET is
very different from that of a
simple JFET or the d-type
MOSFET.

ID = k(VGS − VT )2

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 DC Biasing E-Type MOSFET Biasing

Example (2)
Find VGSQ , IDQ

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 DC Biasing E-Type MOSFET Biasing

Example (2)
Solution:
First evaluate k
ID(on) 3mA
k= 2
= = 0.12mA
(VGS(on) − VGS(T h) ) (10V − 5V )2

The Drain Current, ID is

ID = k(VGS − VT )2 = 0.12 × 10−3 (VGS − 5)2

Calculating VG ,

R2 VDD (18M Ω)(40V )

VG = = = 18V
R1 + R2 22M Ω + 18M Ω
Using Kirchhoff’s Law:

VGS = VG − ID RS = 18V − ID (0.82kΩ)

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 DC Biasing E-Type MOSFET Biasing

Example (2)
By Substituting VGS in the drain current, ID , equation.
ID = 0.12 × 10−3 (18V − ID (0.82kΩ) − 5)2
Solving for IDQ , IDQ = 6.725mA
Substituting to calculate VGSQ , VGSQ = 12.49V
Solving graphically

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 DC Biasing E-Type MOSFET Biasing

Questions?

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