Problems 175 PROBLEMS ‘Answers to problems masked with * appear atthe end ofthe book. Where appropriate, alogic design ‘and its related HDL medeling problem ave cros referenced. AL Considerthe combinstional circuits showa in Fig. P41 (HDL — see Problem 4.49) a h FIGURE P4.1 (a) Desive the Boolean expressions for, through Ty Evaluate the cutputs Fy ad F326 fune- tion of the four inputs. (&) Lstike eth table with 16 binary sombinations of the four inp variables. Then list the ie nary values for T; through 7, andoutpuss Fy and F in the table. (6) Plotthe Boolean output fanctions obtained in part (b) on maps and show that the implied Boolean expressions are euivalert tothe ones obtained in part (a). 4.2 Oban te simplified Boolean expressions for outputs F and G in terns ofthe input variables in the circuit of Fig. P&2, 4.3 For the circuit shown in Fig, 4.26 (Section 4.11), () Writ the Boolean functions forte four outputs in terms of the input variables. {(oy"HE te circuit i listed in truth table, bow many rows and columns would there be ie the ‘abi?44 46 47 4a 49 Design a combinational circuit with three inputs and one outpet. (@) The outputs 1 when the binary valve of te input is es than 3. The output is 0 otherwise (b) The output is when the binary valve of the inputs is an odd number. Design a combinational circuit with three inputs, , ys and z. and three output, A, B, and C, When the binary input is, 1.2, or 3, the binary output is two greater than the input. When the binary input is 4.5. 6,0 7, the binary outputs thre les than the inp. Armujority circuit isa combinational circuit whose output is equal 1 ifthe input variables have more I's than 0's. The output is O otherwise, (a)" Design athre-input majority circuit by finding the circuits th able, Boolean equation, and logic diagram. (©) Write and verify a Verilog dataflow model ofthe cireuit Design a combinational circuit that converts a four-it Gray code Table 1-6) toa fou-bit bina ty number. a)” Implement the circuit with exclusive-OR gates, (©) Using a case statement, write and verify Verilog model of the circuit. Design a code converter that conversa decimal digit from the 8, 4. ~2. ~1 cade to BCD (see ‘Table 1), (HDL —see Problem 4.50.) ‘An ABCD-io-seven-segment decoder is a combinational circuit that converts a decimal digit in BCD t an appropriate cove forthe selection of segments in an indicator used to display the dee- ‘al digit i a fart forr, The seven outputs of the decoder (a,b,c df. §) sles the cot responding segments inthe display, as shown in Fig. P&.%a). The numeric display choses to represent the decimal digit is shown in Fig. P494b). Using a tut able and Karnaugh maps d- sign the BCD-to-seven-segment decoder, using a minimum numberof gies. The six invalid com> ‘binatons should result ina Bank display. CHDL—see Problem 41.) (b) Numerical designation for display 410° Design a four-it combinational cicuit 2's complementer. The output generates the 2's comple= ment of the input binary number.) Show that the circuit can be constructed with exclusive-OR ates. Can you predict what the output functions are fora five-bit 2's complementer? 4.07 Using four half-adders (HDL — see Problem 42), (a) Design a fourbit combinational circuit increment (a circuit that adds 1 toa fourbit bina- ry number), (b) Design a four-it combinational circuit decrementer (a circuit that subvracts 1 from a four- bit binary number), 4.02 (a) Design a halfsubwactor circuit with inputs x and y and outputs Diff and Bw. The cireuit subiracts the bits x — y and places the difference in Diff and the Borrow in Bo(b)* Design a fall-subtractor circuit with three inputs, x, y, Bip and two outputs Diff and By The circuit subtracts x ~ y ~ Big, where Bi isthe input borrow, By isthe output borrow, and Diffis the difference. 4.13° The adder-subtractor circuit of Fig. 4.13 has the following values for mode input M and data ine puts and MAB (a) 0 O11 O10 (&) 0 1000 1001 (©) 1 1100 1000 (@) 1 O01 1010 (e) 1 0000 O001 Ineach case, determine the values ofthe four SUM outputs, the carry C, and overflow V. (HDL— ‘see Problems 4,37 and 4.40.) 14° Assume thatthe exclusive-OR gate has & propagation delay of 10ns and thatthe AND or OR gates hhave a propagation delay of 5 ns. What isthe otal propagation delay time in the four-bit adder of Fig. 4.127 4.15 Derive the two-level Boolean expression for the output carry C shown in.the lookahead carry gen- erator of Fig. 4.12. }6 Define the carry propagate and carry generate as Raat G = AB, respectively. Show that the output carry and output sum ofa full adder becomes Cina = (C/G: + PLY 5, = (PG')@C, “The logic diagram of the first stage of a four: is shown in Fig. P4.16. Identify the P;’ and full adder, .— D> o——§p-—l pt FIGURE P4.’ First stage of a parallel adder it paralle| adder as implemented in IC type 74283 i terminals and show thatthe circuit implements a G