Introduction to VHDL
E. Casas, Page 1 of 56
November 4, 1998
Introduction to VHDL for Design and Modeling
Integrated Microelectronics Engineering, Module 1 November 4, 1998 Part 1: VHDL for Design Ed Casas
Continuing Education in Engineering
University of British Columbia
Introduction to VHDL
E. Casas, Page 2 of 56
November 4, 1998
VHDL
a Very complicated Hardware Description Language
luckily, only a small subset is needed for design VHDL is used for design (covered this morning) and simulation (covered this afternoon)
Continuing Education in Engineering
University of British Columbia
Introduction to VHDL
E. Casas, Page 3 of 56
November 4, 1998
Outline
Introduction (AND gate)
Vectors and Buses Selected Assignment (3-to-8 decoder) Conditional Assignment (4-to-3 priority encoder) Sequential Circuits (ip-op) State Machines (switch debouncer) Signed and Unsigned Types (3-bit counter)
University of British Columbia
Continuing Education in Engineering
Introduction to VHDL
E. Casas, Page 4 of 56
November 4, 1998
Components, Packages and Libraries Using Components
Type Declarations Tri-State Buses
Continuing Education in Engineering
University of British Columbia
Introduction to VHDL
E. Casas, Page 5 of 56
November 4, 1998
First VHDL Example
-- An AND gate library ieee ; use ieee.std_logic_1164.all; entity example1 is port ( a, b: in std_logic ; c: out std_logic ) ; end example1 ; architecture rtl of example1 is begin c <= a and b ; end rtl ;
Continuing Education in Engineering
University of British Columbia
Introduction to VHDL
E. Casas, Page 6 of 56
November 4, 1998
VHDL Syntax
not case sensitive
comments begin with -statements end with ; signal/entity names: letter followed by letters, digits, _ details on library and use statements later
Continuing Education in Engineering
University of British Columbia
Introduction to VHDL
E. Casas, Page 7 of 56
November 4, 1998
Entities and Architectures
the entity names the device
the entity declares the input and output signals the architecture describes what the device does every statement in the architecture executes concurrently
Continuing Education in Engineering
University of British Columbia
Introduction to VHDL
E. Casas, Page 8 of 56
November 4, 1998
Schematic for Example 1
not surprisingly, synthesizing example1 creates:
Continuing Education in Engineering
University of British Columbia
Introduction to VHDL
E. Casas, Page 9 of 56
November 4, 1998
Exercise (Expressions)
Exercise: Write the VHDL description of a half-adder, a circuit that computes the sum, sum, and carry, carry, of two one-bit numbers, a and b.
Continuing Education in Engineering
University of British Columbia
Introduction to VHDL
E. Casas, Page 10 of 56
November 4, 1998
Vectors
one-dimensional arrays used to model buses
usually declared with decreasing indices:
a : std_logic_vector (3 downto 0) ;
constants enclosed in double quotes:
a <= "0010" ;
Continuing Education in Engineering
University of British Columbia
Introduction to VHDL
E. Casas, Page 11 of 56
November 4, 1998
Vector Operations
can take slices (e.g. x(3 downto 2))
can concatenate (e.g. a & b) logic operators (e.g. a and b) apply bit-by-bit
Continuing Education in Engineering
University of British Columbia
Introduction to VHDL
E. Casas, Page 12 of 56
November 4, 1998
Exercise (Vectors)
Exercise: Write a VHDL expression that shifts x, an 8bit std logic vector declared as x : std logic vector (7 downto 0) ;, left by one bit and sets the least-signicant bit to zero.
Continuing Education in Engineering
University of British Columbia
Introduction to VHDL
E. Casas, Page 13 of 56
November 4, 1998
Selected Assignment
models operation of multiplexer
one value selected by controlling expression can implement arbitrary truth table always use an others clause we can declare local signals in architectures
Continuing Education in Engineering
University of British Columbia
Introduction to VHDL
E. Casas, Page 14 of 56
November 4, 1998
VHDL for 3-to-8 Decoder
-- 3-to-8 decoder library ieee ; use ieee.std_logic_1164.all; entity decoder is port ( a, b, c : in std_logic ; y : out std_logic_vector (7 downto 0) ) ; end decoder ;
Continuing Education in Engineering
University of British Columbia
Introduction to VHDL
E. Casas, Page 15 of 56
November 4, 1998
VHDL for 3-to-8 Decoder (Architecture)
architecture rtl of decoder is signal abc : std_logic_vector (2 downto 0) ; begin abc <= a & b & c ; with abc select y <= "00000001" when "000", "00000010" when "001", "00000100" when "010", "00001000" when "011", "00010000" when "100", "00100000" when "101", "01000000" when "110", "10000000" when others ; end rtl ;
Continuing Education in Engineering University of British Columbia
Introduction to VHDL
E. Casas, Page 16 of 56
November 4, 1998
Schematic of 3-to-8 Decoder
Continuing Education in Engineering
University of British Columbia
Introduction to VHDL
E. Casas, Page 17 of 56
November 4, 1998
Conditional Assignment
models if/then/else, but is concurrent
expressions tested in order only value for rst true condition is assigned
Continuing Education in Engineering
University of British Columbia
Introduction to VHDL
E. Casas, Page 18 of 56
November 4, 1998
VHDL for 4-to-3 Encoder
-- 4-to-3 encoder library ieee ; use ieee.std_logic_1164.all ; entity encoder is port ( b : in std_logic_vector (3 downto 0) ; n : out std_logic_vector (2 downto 0) ) ; end encoder ;
Continuing Education in Engineering
University of British Columbia
Introduction to VHDL
E. Casas, Page 19 of 56
November 4, 1998
VHDL for 4-to-3 Encoder (Architecture)
architecture rtl begin n <= "100" when "011" when "010" when "001" when "000" ; end rtl ; of encoder is
b(3) b(2) b(1) b(0)
= = = =
1 1 1 1
else else else else
Continuing Education in Engineering
University of British Columbia
Introduction to VHDL
E. Casas, Page 20 of 56
November 4, 1998
4-to-3 Encoder
Continuing Education in Engineering
University of British Columbia
Introduction to VHDL
E. Casas, Page 21 of 56
November 4, 1998
Exercise (Selected Assignment)
Exercise: If we had used a selected assignment statement, how many lines would have been required in the selected assignment?
Continuing Education in Engineering
University of British Columbia
Introduction to VHDL
E. Casas, Page 22 of 56
November 4, 1998
Sequential Circuits
the process statement can generate ip-ops or registers
details of process covered later
Continuing Education in Engineering
University of British Columbia
Introduction to VHDL
E. Casas, Page 23 of 56
November 4, 1998
VHDL for D Flip-Flop
-- D Flip-Flop library ieee ; use ieee.std_logic_1164.all; entity dff is port ( d, clk : in std_logic ; q : out std_logic ) ; end dff ;
Continuing Education in Engineering
University of British Columbia
Introduction to VHDL
E. Casas, Page 24 of 56
November 4, 1998
VHDL for D Flip-Flop (Architecture)
architecture rtl of dff is begin process(clk) begin if clkevent and clk = 1 then q <= d ; end if ; end process ; end rtl ;
Continuing Education in Engineering
University of British Columbia
Introduction to VHDL
E. Casas, Page 25 of 56
November 4, 1998
Schematic of dff
the synthesized result:
Continuing Education in Engineering
University of British Columbia
Introduction to VHDL
E. Casas, Page 26 of 56
November 4, 1998
Exercise (Sequential Circuits)
Exercise: What would we get if we replaced d and q with signals of type std logic vector?
Continuing Education in Engineering
University of British Columbia
Introduction to VHDL
E. Casas, Page 27 of 56
November 4, 1998
State Machines
use combinational logic to compute next state and outputs
use registers to hold current state
Continuing Education in Engineering
University of British Columbia
Introduction to VHDL
E. Casas, Page 28 of 56
November 4, 1998
Finite State Machine
input current state output next state
combinational logic register clock
Continuing Education in Engineering
University of British Columbia
Introduction to VHDL
E. Casas, Page 29 of 56
November 4, 1998
Switch Debouncer State Diagram
raw=1 raw=0 00 raw=0 state 00 01 10
Continuing Education in Engineering
raw=1
01 raw=0 output 0 0 1
10
raw=1
University of British Columbia
Introduction to VHDL
E. Casas, Page 30 of 56
November 4, 1998
VHDL for Switch Debouncer
-- Switch Debouncer library ieee ; use ieee.std_logic_1164.all ; entity debounce is port ( raw : in std_logic ; clean : out std_logic ; clk : in std_logic ) ; end debounce ;
Continuing Education in Engineering
University of British Columbia
Introduction to VHDL
E. Casas, Page 31 of 56
November 4, 1998
VHDL for Switch Debouncer (Architecture)
architecture rtl of debounce is signal currents, nexts : std_logic_vector (1 downto 0) ; begin -- combinational logic for next state nexts <= "00" when raw = 0 else "01" when currents = "00" else "10" ; -- combinational logic for output clean <= 1 when currents = "10" else 0 ;
Continuing Education in Engineering
University of British Columbia
Introduction to VHDL
E. Casas, Page 32 of 56
November 4, 1998
VHDL for Switch Debouncer (process)
-- sequential logic process(clk) begin if clkevent and clk = 1 then currents <= nexts ; end if ; end process ; end rtl ;
Continuing Education in Engineering
University of British Columbia
Introduction to VHDL
E. Casas, Page 33 of 56
November 4, 1998
Schematic of Debouncer
Continuing Education in Engineering
University of British Columbia
Introduction to VHDL
E. Casas, Page 34 of 56
November 4, 1998
Exercise (State Machine)
Exercise: Identify the components in the schematic that were created (instantiated ) by different parts of the VHDL code.
Continuing Education in Engineering
University of British Columbia
Introduction to VHDL
E. Casas, Page 35 of 56
November 4, 1998
Arithmetic Types
allow us to treat logic values as numbers
arithmetic and comparison operators available multiply and divide may not synthesize
Continuing Education in Engineering
University of British Columbia
Introduction to VHDL
E. Casas, Page 36 of 56
November 4, 1998
VHDL for 3-bit Counter
-- 3-bit Counter library ieee ; use ieee.std_logic_1164.all ; use ieee.std_logic_arith.all ; entity counter is port ( count_out : out unsigned (2 downto 0) ; clk : in std_logic ) ; end counter ;
Continuing Education in Engineering
University of British Columbia
Introduction to VHDL
E. Casas, Page 37 of 56
November 4, 1998
VHDL for Up/Down Counter (Architecture)
architecture rtl of counter is signal count, nextcount : unsigned (2 downto 0) ; begin nextcount <= count + 1 ; process(clk) begin if clkevent and clk=1 then count <= nextcount ; end if ; end process ; count_out <= count ; end rtl ;
Continuing Education in Engineering
University of British Columbia
Introduction to VHDL
E. Casas, Page 38 of 56
November 4, 1998
Arithmetic Types (ctd)
can use arithmetic types to implement a counter as a state machine
cant read port signals of type out
Continuing Education in Engineering
University of British Columbia
Introduction to VHDL
E. Casas, Page 39 of 56
November 4, 1998
Exercise (Arithmetic Types)
Exercise: Write the architecture for a 16-bit adder with two signed inputs, a and b and a signed output c.
Continuing Education in Engineering
University of British Columbia
Introduction to VHDL
E. Casas, Page 40 of 56
November 4, 1998
Components
allows design re-use
like an entity, a component denes interface, not functionality denitions usually saved in packages (les) packages are stored in libraries (directories)
Library Package component component Package component component
Continuing Education in Engineering
University of British Columbia
Introduction to VHDL
E. Casas, Page 41 of 56
November 4, 1998
VHDL for Component Declaration
package name is flipflops
declares the rs component:
package flipflops is component rs port ( r, s : in bit ; q : out bit ) ; end component ; end flipflops ;
compiling this le creates the package
Continuing Education in Engineering
University of British Columbia
Introduction to VHDL
E. Casas, Page 42 of 56
November 4, 1998
Using Packages and Libraries
library and use statements make contents of packages available
e.g. to access the DSP package in the ALTERA library:
library altera ; use [Link] ;
Continuing Education in Engineering
University of British Columbia
Introduction to VHDL
E. Casas, Page 43 of 56
November 4, 1998
Using Components
a component instantiation statement:
places a copy of the component in the design is a concurrent statement describes how the component connects to other signals is structural design
Continuing Education in Engineering
University of British Columbia
Introduction to VHDL
E. Casas, Page 44 of 56
November 4, 1998
VHDL for XOR2 Component Declaration
the xor2 component is described in a package:
-- define an xor2 component in a package library ieee ; use ieee.std_logic_1164.all ; package xor_pkg is component xor2 port ( a, b : in std_logic ; x : out std_logic ) ; end component ; end xor_pkg ;
Continuing Education in Engineering
University of British Columbia
Introduction to VHDL
E. Casas, Page 45 of 56
November 4, 1998
VHDL for Parity Generator
-- Parity function built from xor gates library ieee ; use ieee.std_logic_1164.all ; use work.xor_pkg.all ; entity parity is port ( a, b, c, d : in std_logic ; p : out std_logic ) ; end parity ;
Continuing Education in Engineering
University of British Columbia
Introduction to VHDL
E. Casas, Page 46 of 56
November 4, 1998
VHDL for Parity Generator (Architecture)
architecture rtl of parity is -- internal signals signal x, y : std_logic ; begin x1: xor2 port map ( a, b, x ) ; x2: xor2 port map ( c, x, y ) ; x3: xor2 port map ( d, y, p ) ; end rtl ;
Continuing Education in Engineering
University of British Columbia
Introduction to VHDL
E. Casas, Page 47 of 56
November 4, 1998
Schematic of Parity Generator
Continuing Education in Engineering
University of British Columbia
Introduction to VHDL
E. Casas, Page 48 of 56
November 4, 1998
Exercise (Component Instantiation)
Exercise: Label the connections within the parity generator schematic with the signal names used in the architecture.
Continuing Education in Engineering
University of British Columbia
Introduction to VHDL
E. Casas, Page 49 of 56
November 4, 1998
Type Declarations
can declare new signal types (e.g. new bus widths, enumeration types for state machines)
usually placed in a package
Continuing Education in Engineering
University of British Columbia
Introduction to VHDL
E. Casas, Page 50 of 56
November 4, 1998
VHDL for Type Declarations
to create a package called dsp_types:
package dsp_types is type mode is (slow, medium, fast) ; subtype sample is std_logic_vector (7 downto 0) ; end dsp_types ;
Continuing Education in Engineering
University of British Columbia
Introduction to VHDL
E. Casas, Page 51 of 56
November 4, 1998
Tri-State Buses
tri-state (high-impedance) often used in buses
assigning the value Z to a signal of type out tri-states that output
Continuing Education in Engineering
University of British Columbia
Introduction to VHDL
E. Casas, Page 52 of 56
November 4, 1998
VHDL for Tri-State Buffer
-- Tri-State Buffer library ieee ; use ieee.std_logic_1164.all ; entity tbuf is port ( d : in std_logic_vector (3 downto 0) ; q : out std_logic_vector (3 downto 0) ; en : in std_logic ) ; end tbuf ;
Continuing Education in Engineering
University of British Columbia
Introduction to VHDL
E. Casas, Page 53 of 56
November 4, 1998
VHDL for Tri-State Buffer (Architecture)
architecture rtl of tbuf is begin q <= d when en = 1 else "ZZZZ" ; end rtl ;
Continuing Education in Engineering
University of British Columbia
Introduction to VHDL
E. Casas, Page 54 of 56
November 4, 1998
Schematic of Tri-State Buffer
Continuing Education in Engineering
University of British Columbia
Introduction to VHDL
E. Casas, Page 55 of 56
November 4, 1998
VHDL for Demo Circuit
-- demonstration design light chaser library ieee ; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use [Link] ; entity demo is port ( clk : in std_logic ; led : out std_logic_vector (7 downto 0) ) ; end demo;
Continuing Education in Engineering
University of British Columbia
Introduction to VHDL
E. Casas, Page 56 of 56
November 4, 1998
VHDL for Demo Circuit (Architecture)
architecture rtl of demo is signal count : unsigned (2 downto 0) ; signal scount : std_logic_vector (2 downto 0) ; signal ledN : std_logic_vector(7 downto 0) ; begin c1: counter port map ( count, clk ) ; scount <= std_logic_vector(count); d1: decoder port map ( scount(2), scount(1), scount(0), ledN ) ; led <= not ledN ; end rtl ;
Continuing Education in Engineering
University of British Columbia
