Verilog code :

 Parity encoder :
1. Dataflow modelling:

module parity_encoder (
input [7:0] data_in,
output parity_out
);

assign parity_out = ^data_in;

endmodule
2. Behavioural modelling:
module parity_encoder(
input [N-1:0] data_in, // N-bit input data
output reg parity_bit // Output parity bit
);

always @(*) begin

integer i;
integer count;

// Initialize count to 0
count = 0;
 // Count the number of '1's in the input data
for (i = 0; i < N; i = i + 1) begin
if (data_in[i] == 1'b1) begin
count = count + 1;
end
end

// Parity bit is set to 1 if the count is odd, else 0

if (count % 2 == 1) begin
parity_bit = 1'b1;
end
else begin
parity_bit = 1'b0;
end
end

endmodule
3. Gate-Level modelling:
module parity_encoder(input [7:0] data, output parity);

wire [3:0] xor_result;

wire xor_out;

assign xor_result = data[0] ^ data[1] ^ data[2] ^ data[3] ^ data[4] ^ data[5] ^ data[6] ^ data[7];
assign xor_out = xor_result[0] ^ xor_result[1] ^ xor_result[2] ^ xor_result[3];

assign parity = xor_out;

endmodule

Parity Decoder :
1. Structural Modeling:
module ParityDecoderStructural (
input [3:0] in_data,
output out
);

wire xor_output;

assign xor_output = in_data[0] ^ in_data[1] ^ in_data[2] ^ in_data[3];

assign out = ~xor_output;

endmodule
2. Behavioural modelling:
module ParityDecoderBehavioral (
input [3:0] in_data,
output out
);

reg out;

always @(*) begin

out = ~(in_data[0] ^ in_data[1] ^ in_data[2] ^ in_data[3]);
end
endmodule
3. Gate-Level modelling:
module ParityDecoderGateLevel (
input [3:0] in_data,
output out
);

wire xor_output;

assign xor_output = in_data[0] ^ in_data[1] ^ in_data[2] ^ in_data[3];

assign out = ~xor_output;

endmodule

 Carry Lookahead Adder (CLA) :

1. Structural Modeling:

module cl_adder_structural (
input [3:0] A,
input [3:0] B,
output [4:0] SUM,
output C_OUT
);

wire [3:0] G, P;
wire [4:0] C;
// Generate and Propagate signals
genvar i, j;
generate
for (i = 0; i < 4; i = i + 1) begin : gen_block
assign G[i] = A[i] & B[i];
assign P[i] = A[i] | B[i];
end
endgenerate

// Carry calculation
assign C[0] = 1'b0;
genvar k;
generate
for (k = 1; k < 5; k = k + 1) begin : gen_block2
assign C[k] = G[k-1] | (P[k-1] & C[k-1]);
end
endgenerate

// Output SUM and Carry Out

assign SUM = A + B + C[1:4];
assign C_OUT = C[4];

endmodule
2. Behavioural modelling:
module cl_adder_behavioral (
input [3:0] A,
input [3:0] B,
 output [4:0] SUM,
output C_OUT
);

// Carry bit
reg C_OUT;
// Internal signals for intermediate calculations
reg [4:0] sum_temp;

// Behavioral implementation
always @* begin
sum_temp = A + B;
C_OUT = sum_temp[4];
end

assign SUM = sum_temp;

endmodule
3.Data flow modelling:
module cl_adder_dataflow (
input [3:0] A,
input [3:0] B,
output [4:0] SUM,
output C_OUT
);

assign {C_OUT, SUM} = A + B;

endmodule
1. .Data flow modelling:
module magnitude_comparator_dataflow (
input [3:0] A,
input [3:0] B,
output A_greater, // A > B
output B_greater, // B > A
output equal // A = B
);

assign {A_greater, B_greater, equal} = (A > B) ? 3'b100 : (A < B) ? 3'b010 : 3'b001;

endmodule

2. Behavioural modelling:
module magnitude_comparator_behavioral (
input [3:0] A,
input [3:0] B,
output A_greater, // A > B
output B_greater, // B > A
output equal // A = B
);

// Behavioral implementation
always @* begin
if (A > B) begin
A_greater = 1'b1;
B_greater = 1'b0;
equal = 1'b0;
end else if (A < B) begin
A_greater = 1'b0;
B_greater = 1'b1;
equal = 1'b0;
end else begin
A_greater = 1'b0;
B_greater = 1'b0;
equal = 1'b1;
 end
end

endmodule

3. Structural Modeling:

module magnitude_comparator_structural (
input [3:0] A,
input [3:0] B,
output A_greater, // A > B
output B_greater, // B > A
output equal // A = B
);

assign A_greater = (A > B);

assign B_greater = (A < B);
assign equal = (A == B);

endmodule

 Parallel Adder/Subtractor
1. Structural Modeling:
module parallel_adder_subtractor_structural (
input [3:0] A,
input [3:0] B,
input subtract, // 0 for add, 1 for subtract
output [4:0] SUM
);

wire [3:0] B_comp;

wire C_IN;
wire [4:0] SUM_temp;

assign B_comp = subtract ? (~B + 1) : B;

assign C_IN = subtract;

// Ripple Carry Adder

ripple_carry_adder adder_inst (
.A(A),
 .B(B_comp),
.C_IN(C_IN),
.SUM(SUM_temp)
);

assign SUM = SUM_temp;

endmodule

// Ripple Carry Adder Module

module ripple_carry_adder (
input [3:0] A,
input [3:0] B,
input C_IN,
output [4:0] SUM
);

wire [3:0] C_out;

assign SUM[0] = A[0] ^ B[0] ^ C_IN;
assign C_out[0] = (A[0] & B[0]) | (A[0] & C_IN) | (B[0] & C_IN);

genvar i;
generate
for (i = 1; i < 4; i = i + 1) begin : gen_block
assign SUM[i] = A[i] ^ B[i] ^ C_out[i-1];
assign C_out[i] = (A[i] & B[i]) | (A[i] & C_out[i-1]) | (B[i] & C_out[i-1]);
end
endgenerate

assign SUM[4] = C_out[3];

endmodule

2. Data Flow Modeling:

module parallel_adder_subtractor_dataflow (
input [3:0] A,
input [3:0] B,
input subtract, // 0 for add, 1 for subtract
output [4:0] SUM
);
 assign SUM = subtract ? A - B : A + B;

endmodule

3. Behavioral Modeling:

module parallel_adder_subtractor_behavioral (
input [3:0] A,
input [3:0] B,
input subtract, // 0 for add, 1 for subtract
output [4:0] SUM
);

// Behavioral implementation
always @* begin
if (subtract == 1'b1)
SUM = A - B;
else
SUM = A + B;
end

endmodule

 4-Bit Magnitude comparator

1. Structural Modeling:

module magnitude_comparator_structural (

input [3:0] A,

input [3:0] B,

output A_greater, // A > B

output B_greater, // B > A

output equal // A = B

);
wire [3:0] A_xor_B;

wire [3:0] A_and_B;

assign A_xor_B = A ^ B;

assign A_and_B = A & B;

assign A_greater = |(A & A_xor_B);

assign B_greater = |(B & A_xor_B);

assign equal = ~(A_greater | B_greater | |(A_and_B));

endmodule

2. Data Flow Modeling:

module magnitude_comparator_dataflow (

input [3:0] A,

input [3:0] B,

output A_greater, // A > B

output B_greater, // B > A

output equal // A = B

);

assign {A_greater, B_greater, equal} = (A > B) ? 3'b100 : (A < B) ? 3'b010 : 3'b001;

endmodule

3. Behavioral Modeling:

module magnitude_comparator_behavioral (
 input [3:0] A,

input [3:0] B,

output A_greater, // A > B

output B_greater, // B > A

output equal // A = B

);

// Behavioral implementation

always @* begin

if (A > B) begin

A_greater = 1'b1;

B_greater = 1'b0;

equal = 1'b0;

end else if (A < B) begin

A_greater = 1'b0;

B_greater = 1'b1;

equal = 1'b0;

end else begin

A_greater = 1'b0;

B_greater = 1'b0;

equal = 1'b1;

end

end

endmodule

 Shift Registers - SISO, SIPO, PISO,PIPO

1.SISO (Serial-In Serial-Out):

module siso_shift_register (

input clk, // Clock input

input reset, // Reset input

input serial_in, // Serial input

output reg serial_out // Serial output

);

reg [3:0] register;

always @(posedge clk or posedge reset) begin

if (reset)

register <= 4'b0000;

else

register <= {register[2:0], serial_in};

end

assign serial_out = register[3];

endmodule

2. SIPO (Serial-In Parallel-Out):

module sipo_shift_register (

input clk, // Clock input

input reset, // Reset input

 input serial_in, // Serial input

output reg [3:0] parallel_out // Parallel output

);

reg [3:0] register;

always @(posedge clk or posedge reset) begin

if (reset)

register <= 4'b0000;

else

register <= {register[2:0], serial_in};

end

assign parallel_out = register;

endmodule

3. PISO (Parallel-In Serial-Out):

module piso_shift_register (

input clk, // Clock input

input reset, // Reset input

input [3:0] parallel_in, // Parallel input

output reg serial_out // Serial output

);

reg [3:0] register;

reg counter;

always @(posedge clk or posedge reset) begin

if (reset)

register <= 4'b0000;

else if (counter < 4)

register <= parallel_in;

else

register <= {register[2:0], 1'b0};

if (counter < 4)

counter <= counter + 1;

end

assign serial_out = register[3];

endmodule

4. PIPO (Parallel-In Parallel-Out):

module pipo_shift_register (
input clk, // Clock input
input reset, // Reset input
input [3:0] parallel_in, // Parallel input
output reg [3:0] parallel_out // Parallel output
);

reg [3:0] register;

always @(posedge clk or posedge reset) begin

 if (reset)
register <= 4'b0000;
else
register <= parallel_in;
end

assign parallel_out = register;

endmod

 Counters

1. 1. Structural Modeling:

module counter_structural (
input clk, // Clock input
input reset, // Reset input
output reg [3:0] count // Counter output
);

wire clk_inv;

// Invert the clock signal

assign clk_inv = ~clk;

// D Flip-Flop instances for each bit of the counter

D_FF dff_inst0 (.clk(clk), .reset(reset), .D(count[0]), .Q(count[0]));
D_FF dff_inst1 (.clk(clk), .reset(reset), .D(count[1]), .Q(count[1]));
D_FF dff_inst2 (.clk(clk), .reset(reset), .D(count[2]), .Q(count[2]));
D_FF dff_inst3 (.clk(clk), .reset(reset), .D(count[3]), .Q(count[3]));

endmodule

// D Flip-Flop module
module D_FF (
input clk, // Clock input
input reset, // Reset input
input D, // Data input
output reg Q // Output
);

always @(posedge clk or posedge reset) begin

if (reset)
Q <= 1'b0; // Reset Q to 0
else
Q <= D; // Update Q with D on clock edge
end

endmodule

2. 2. Data Flow Modeling:

module counter_dataflow (
input clk, // Clock input
input reset, // Reset input
 output reg [3:0] count // Counter output
);

always @(posedge clk or posedge reset) begin

if (reset)
count <= 4'b0000; // Reset count to 0
else
count <= count + 1; // Increment count on clock edge
end

endmodule

3. 3. Behavioral Modeling:

module counter_behavioral (
input clk, // Clock input
input reset, // Reset input
output reg [3:0] count // Counter output
);

// Behavioral implementation
always @(posedge clk or posedge reset) begin
if (reset)
count <= 4'b0000; // Reset count to 0
else
count <= count + 1; // Increment count on clock edge
end
endmodule