Birla Institute of Technology & Science, Pilani
Work Integrated Learning Programmes Division
Digital Learning Handout
Course Title VLSI DESIGN
Course No(s) MEL ZG621 / ES ZG621
Credit Units 5
Credit Model 3 + 2 (3-theory, 2-lab)
Content Author S. Gurunarayanan / Pawan Sharma
Instructor-In-Charge SANJAY VIDHYADHARAN
Course description: The course covers introduction to NMOS and CMOS circuits; NMOS and CMOS
processing technology; CMOS circuits and logic design; circuit characterization and performance
estimation; structured design and testing; symbolic layout systems; CMOS subsystem design; system case
studies.
Course Objectives:
CO1 To understand the need and importance of digital VLSI design in CMOS integrated circuits.
CO2 To understand the behavior of static and dynamic CMOS circuits, voltage transfer characteristics,
transient behavior, clock behavior, area and layout estimation techniques
CO3 To analyze the clock generation techniques, impact of spatial and temporal variations of the clock
signals.
CO4 To study low power design techniques, effect of interconnect parasitic to minimize the overall
power dissipation in the circuit.
CO5 To design the CMOS based circuits at the sub system level, using different topologies for adders
and multipliers.
CO6 To study and design the basic cells of semiconductor memory using low power design
techniques.
CO7 To learn use of CAD tools to design and verify behavior of CMOS circuits
Text Book(s):
T1 CMOS Digital Integrated Circuits, Analysis and Design, 3rd edition, Sung-Mo Kang and Yusuf
Leblebici, Tata McGraw- Hill Edition, 2003
T2 Digital Integrated Circuits, A Design Perspective, Jan M Rabaey, Anantha Chandrakasan, Borivoje
Nikolic, 2nd edition, Prentice Hall, 2005.7
Reference Book(s) & other resources:
R1 Essentials of VLSI Circuits and Systems, Kamran Eshraghian, Douglas A Pucknell, Sholeh
Eshraghian, Prentice Hall India, 2009
R2 CMOS VLSI Design, A Circuits and Systems Perspective, 4th edition, Neil H E Weste, David
Money Harris, Pearson
R3 CMOS Logic Circuit Design, Uyemura, John P., Springer, 1999, ISBN: 9780792384526
R4 Principles of CMOS VLSI Design, A Systems Perspective, Neil H Weste, Kamran Eshraghian,
second edition, Pearson Education India, 2010
R5 1. Digital Integrated Circuit Design, by Ken Martin, OUP (USA) Engineering © 2000 (560 pages)
Citation, ISBN: 9780195125849
2. Low Power Methodology Manual: For System-on-Chip Design, by Michael Keating and etal.,
Springer © 2007 (302 pages) Citation, ISBN:9780387718187
Learning Outcomes:
No Learning Outcomes
LO1 Understand the fundamental concepts of CMOS logic to form a strong basis both for the
conceptual understanding and the development of CMOS designs.
LO2 Understand the static and dynamic operation principles, analysis and design of basic inverter
circuits; and the structure and operation of combinational and sequential logic gates.
LO3 Learn the issues of on-chip interconnect modeling and interconnect delay calculation
LO4 Understand methodologies and design practices to reduce the power dissipation of large-scale
digital integrated circuits.
LO5 Understand the design and operation of static and dynamic memory types and comparisons of
their performance characteristics.
LO6 Efficient use of electronic design automation tools to design and verify digital VLSI systems.
Experiential Learning Components:
The students can use open source Electric VLSI Design System CAD tool to design and verify behaviour
of CMOS circuits. The CAD tool can be used to learn all aspects of CMOS circuit design like draw
schematic, SPICE simulation, layout, DRC, LVS checks and generate the GDS II format.
Content Structure
Contact List of Topic Sub-Topics Reference
Hour
Historical perspective of VLSI design T2 – 1.1
Overview of VLSI design methodologies T1 – 1.4
Introduction to VLSI Design Flow T1 – 1.5
1
VLSI Design VLSI Design Styles T1 – 1.8
VLSI Design Quality T1 – 1.9
Issues in Digital Integrated Circuit Design T2 – 1.2
Structure and operation of MOS transistor T1 – 3.1 to 3.3,
under external bias R2 – 2.1, 2.2
MOS MOSFET current - voltage characteristics T1 -3.4, R2 – 2.5
2 Transistor Scaling models and factors Manufacturing R1 – 5.1, 5.2, T2
Characteristics CMOS ICs – 2.2
MOSFET scaling and small geometry effects T1 – 3.5
MOSFET capacitances T1 – 3.6
Fabrication Fabrication process flow: basic steps T1 -- 2.1, 2.2
Process and CMOS n-well process T1 – 2.3
3 Design Rules Layout design rules T1 – 2.4
of MOS Full custom mask layout design T1 – 2.5
Transistor
MOS Inverter: Resistive Load Inverter T1 – 5.2
4 Static Inverters with n-type MOSFET load T1 – 5.3
Characteristics CMOS inverter T1 – 5.4, T2-5.2
MOS Delay time definitions and calculation T1 – 6.1-6.3
Inverters: Inverter design with delay constraints T1 – 6.4
5
Switching Switching power dissipation of CMOS T1 – 6.7
characteristics inverters
MOS logic circuits with depletion nMOS load T1 – 7.2
Combinational
CMOS logic circuits T1 – 7.3, 6.2.1
6 MOS Logic
Complex CMOS logic circuits T1 – 7.4, R2-9.2
Circuits
CMOS transmission gates T1 – 7.5, R1-6.2
Timing metrics for sequential circuits T2 – 7.1
Behaviour of bi-stable elements T1 – 8.2
Sequential SR latch circuit T1 – 8.3
7 MOS Logic Clocked latch and flip-flop circuits T1 – 8.4
Circuits CMOS D-latch and edge-triggered flip-flop T1 – 8.5
Latch vs register based pipeline T2 – 7.5.1
NORA-CMOS T2 – 7.5.2
Review Review of Contact Hours 1-7
8
Session
Basic principles of pass transistor circuits T1 – 9.1-9.2
Dynamic Voltage bootstrapping T1 – 9.3
9
Logic Circuits Synchronous dynamic circuit techniques T1 – 9.4, 9.5
High performance dynamic CMOS circuits T1 – 9.6
Overview of power consumption T1 – 11.1, 11.2
Low power design through voltage scaling T1 – 11.3
Low power
Estimation and Optimization of switching T1 – 11.4
10 Digital VLSI
activity
Design
Reduction of switched capacitance T1 – 11.5
Adiabatic logic circuits T1 – 11.6
Electrical wire models T2 – 4.3, 4.4
Interconnect
Capacitive parasitic T2 – 9.2
11 Parasitic
Resistive parasitic T2 – 9.3
Inductive parasitic T2 – 9.4
Clock signal Timing classification of digital systems T2 – 10.2
Generation Synchronous design, timing basics, skew and T2 – 10.3
12 and jitter, Clock distribution, Latch based clocking R2 – 13.4
Distribution
Design of Data path in digital processors architectures T2 – 11.2
VLSI Adder architectures T2 – 11.3
13 Arithmetic Multiplier architectures T2 – 11.4
modules The shifter architectures T2 – 11.5
Aspects of Read Only Memory circuits T1 – 10.4
Memory Static RAM circuits T1 – 10.3
14 Design Design of Dynamic RAM cells T1 – 10.2
Memory peripheral circuits T2 – 12.3
Validation and Fault types and models T1 – 15.1, 15.2
Controllability and observability T1 – 15.3
15 Test of
Ad hoc testable design techniques T1 – 15.4
Manufactured
Scan based techniques T1 – 15.5
Circuits Built-in self-test (BIST) techniques T1 – 15.6
Review Review of Complete Syllabus
16
Session
Laboratory Component
Sr. No. Experiment Title Reference
1. A tutorial on setting up Electric Overview of CAD Tool
2. Fabrication Process and Design Rules of
Layout and Design of Resistive Voltage Divider
MOS Transistor
3. IV Curves of MOS transistors MOS Transistor Characteristics
4. Design and Layout of CMOS inverter MOS Inverter: Static Characteristics
5. VLSI Design and layout of CMOS NAND gate Combinational MOS Logic Circuits
6. Design and Layout of ring oscillator Combinational MOS Logic Circuits
7. D flip-flop schematic design Sequential MOS Logic Circuits
8. D flip-flop layout design Sequential MOS Logic Circuits
Evaluation Scheme
Legend: EC = Evaluation Component; AN = After Noon Session; FN = Fore Noon Session
No Name Type Duration Weight Day, Date, Session, Time
EC-1* Quiz Online 1 week 10 % February 19-28, 2024
Assignment/Lab Online 10 days 20 % March 19-28, 2024
Assignment
EC-2 Mid-Semester Test Closed 2 hours 30 %
Book Sunday, 17/03/2024 (FN)
EC-3 Comprehensive Exam Open Book 2 ½ 40 % Sunday, 19/05/2024 (FN)
hours
EC1* (20% - 30%): Quiz (optional): 5-10 %, Lab Assignment/Assignment: 20% - 30%
Syllabus for Mid-Semester Test (Closed Book): Topics in Session Nos. 1 to 8
Syllabus for Comprehensive Exam (Open Book): All topics (Session Nos. 1 to 16)
Important links and information:
Elearn portal: https://elearn.bits-pilani.ac.in
Students are expected to visit the Elearn portal on a regular basis and stay up to date with the latest
announcements and deadlines.
Contact sessions: Students should attend the online lectures as per the schedule provided on the
Elearn portal.
Evaluation Guidelines:
1. EC-1 consists of either two Assignments or three Quizzes. Students will attempt them
through the course pages on the Elearn portal. Announcements will be made on the portal,
in a timely manner.
2. For Closed Book tests: No books or reference material of any kind will be permitted.
3. For Open Book exams: Use of books and any printed / written reference material (filed or
bound) is permitted. However, loose sheets of paper will not be allowed. Use of calculators
is permitted in all exams. Laptops/Mobiles of any kind are not allowed. Exchange of any
material is not allowed.
4. If a student is unable to appear for the Regular Test/Exam due to genuine exigencies, the
student should follow the procedure to apply for the Make-Up Test/Exam which will be
made available on the Elearn portal. The Make-Up Test/Exam will be conducted only at
selected exam centres on the dates to be announced later.
It shall be the responsibility of the individual student to be regular in maintaining the self study
schedule as given in the course handout, attend the online lectures, and take all the prescribed
evaluation components such as Assignment/Quiz, Mid-Semester Test and Comprehensive Exam
according to the evaluation scheme provided in the handout.
