2.
BCD to Seven Segment Display
AIM: To design, Design a BCD to Seven segment circuit using Verilog and result is display
it on FPGA seven segment display.
Tools used:
1. Vivado tool
2. Vivado Simulator
3. EDGE ARTIX7
Logic Diagram:
Program:
module bcd_seven_segment (bcd, seg );
//Declare inputs, outputs and internal variables.
input [3:0] bcd;
output [6:0] seg;
reg [6:0] seg;
//always block for converting bcd digit into 7 segment format
always @(bcd)
begin
case (bcd) //case statement
0 :seg = 7'b0000001;
1 :seg = 7'b1001111;
2 :seg = 7'b0010010;
3 :seg = 7'b0000110;
4 :seg = 7'b1001100;
5 :seg = 7'b0100100;
6 :seg = 7'b0100000;
7 :seg = 7'b0001111;
8 :seg = 7'b0000000;
9 :seg = 7'b0000100;
//switch off 7 segment character when the bcd digit is not a decimal number.
default :seg = 7'b1111111;
endcase
end
endmodule
module bin2bcd(
input [3:0] bin_in,
output reg [3:0] tens,
output reg [3:0] ones
);
always @* begin
tens <= bin_in / 10;
ones <= bin_in % 10;
end
endmodule
module seg_display(
input clk,
input [3:0] digit_1,
input [3:0] digit_2,
//input [3:0] digit_3,
// input [3:0] digit_4,
// input [3:0] digit_5,
// input [3:0] digit_6,
output reg [7:0] cathode,
output reg [3:0] anode
);
// We need to switch between the digits as fast as possible...we will use 1 KHz clk
reg [17:0] count_next;
reg [17:0] count_reg=0;
always@(posedge clk)
count_reg <= count_next;
always@(*)
count_next = count_reg + 1;
always@(*)
begin
case(count_reg [17:16])
2'b00:
begin
case(digit_1)
4'd0: cathode = {7'b0000001,1'b1};
4'd1: cathode = {7'b1001111,1'b1};
4'd2: cathode = {7'b0010010,1'b1};
4'd3: cathode = {7'b0000110,1'b1};
4'd4: cathode = {7'b1001100,1'b1};
4'd5: cathode = {7'b0100100,1'b1};
4'd6: cathode = {7'b0100000,1'b1};
4'd7: cathode = {7'b0001111,1'b1};
4'd8: cathode = {7'b0000000,1'b1};
4'd9: cathode = {7'b0000100,1'b1};
endcase
anode = 4'b1110;
end
2'b01:
begin
case(digit_2)
4'd0: cathode = {7'b0000001,1'b1};
4'd1: cathode = {7'b1001111,1'b1};
4'd2: cathode = {7'b0010010,1'b1};
4'd3: cathode = {7'b0000110,1'b1};
4'd4: cathode = {7'b1001100,1'b1};
4'd5: cathode = {7'b0100100,1'b1};
4'd6: cathode = {7'b0100000,1'b1};
4'd7: cathode = {7'b0001111,1'b1};
4'd8: cathode = {7'b0000000,1'b1};
4'd9: cathode = {7'b0000100,1'b1};
endcase
anode = 4'b1101;
end
// default:
//begin
// anode = 8'b11111111;
//end
endcase
end
endmodule
Test bench module
module bcd_seven_segment_tb;
reg [3:0] bcd;
wire [6:0] seg; // Instantiate the Unit Under Test (UUT)
bcd_seven_segment uut ( .bcd(bcd), .seg(seg));
//Apply inputs
initial
begin
bcd=4'b0011; #20
bcd=4'b0111;#20
bcd=4'b1001;#20
bcd=4'b0100;#20
bcd=4'b0111;
end
endmodule
constraint file
set_property IOSTANDARD LVCMOS33 [get_ports clk_0]
set_property IOSTANDARD LVCMOS33 [get_ports {anode_0[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {anode_0[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {anode_0[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {anode_0[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {bin_in_0[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {bin_in_0[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {bin_in_0[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {bin_in_0[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {cathode_0[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {cathode_0[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {cathode_0[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {cathode_0[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {cathode_0[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {cathode_0[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {cathode_0[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {cathode_0[0]}]
set_property PACKAGE_PIN N11 [get_ports clk_0]
set_property PACKAGE_PIN F2 [get_ports {anode_0[3]}]
set_property PACKAGE_PIN E1 [get_ports {anode_0[2]}]
set_property PACKAGE_PIN G4 [get_ports {anode_0[1]}]
set_property PACKAGE_PIN G5 [get_ports {anode_0[0]}]
set_property PACKAGE_PIN M2 [get_ports {bin_in_0[3]}]
set_property PACKAGE_PIN M4 [get_ports {bin_in_0[2]}]
set_property PACKAGE_PIN L4 [get_ports {bin_in_0[1]}]
set_property PACKAGE_PIN L5 [get_ports {bin_in_0[0]}]
set_property PACKAGE_PIN G2 [get_ports {cathode_0[7]}]
set_property PACKAGE_PIN G1 [get_ports {cathode_0[6]}]
set_property PACKAGE_PIN H5 [get_ports {cathode_0[5]}]
set_property PACKAGE_PIN H4 [get_ports {cathode_0[4]}]
set_property PACKAGE_PIN J5 [get_ports {cathode_0[3]}]
set_property PACKAGE_PIN J4 [get_ports {cathode_0[2]}]
set_property PACKAGE_PIN H2 [get_ports {cathode_0[1]}]
set_property PACKAGE_PIN H1 [get_ports {cathode_0[0]}]
Block based design
Simulation Results:
Result:
The BCD to seven segment circuit is designed using Verilog HDL. Simulation and FPGA
implementation is performed using Vivado tool. Functional verification of the design is performed
using a Verilog HDL test bench.
