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Energy Consumption of Channel Decoders for OFDM-based UWB Systems

Conference Paper · October 2007

DOI: 10.1109/ICUWB.2007.4380986 · Source: IEEE Xplore

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 Energy Consumption of Channel Decoders for
OFDM-based UWB Systems
Timo Lehnigk-Emden, Christian Brehm, Torben Brack, Norbert Wehn Friedbert Berens, Cem Derdiyok
Microelectronic System Design Research Group, University of Kaiserslautern, STMicroelectronics N.V.,
Erwin-Schroedinger Str., 67663 Kaiserslautern, Germany 1228 Plan-les-Ouates, Geneva, Switzerland
{lehnigk,brehm,brack,wehn}@eit.uni-kl.de {friedbert.berens,cem.derdiyok}@st.com

Abstract— Ultra Wide Band (UWB) systems are designed for

short range transmission with very high throughput demands
(480 Mbit/s). Current UWB systems specify convolutional codes
(CC) for channel coding. However, it was already shown that
more sophisticated Low-Density Parity-Check Codes (LDPC) can
outperform CC. This gain of communications performance comes
with the penalty of a higher implementation complexity.
Fig. 1. WIMEDIA UWB simulation chain
In this paper, the currently specified convolutional code and
an LDPC code are compared concerning their decoders’ im- become the channel coding scheme of choice for years to
plementation complexity with special emphasis on its energy
consumption. In this context, we evaluate an advanced iteration
come.
control for LDPC decoders in the environment of the future Many UWB applications are in the consumer and portable
WIMEDIA UWB industry standard. The number of iterations is domain. Hence energy consumption is of great relevance. It
directly related to the LDPC decoder’s energy consumption. Both is often argued that the complexity of an LDPC decoder is
decoders are implemented on a rapid prototyping platform to much higher than the complexity of a Viterbi decoder. Thus,
evaluate the energy consumption of LDPC decoding compared to
CC decoding. Measurements show that the energy consumption
it is assumed that the energy consumption of LDPC decoding
of both decoders are nearly identical while LDPC codes come is also larger than the decoding process of a convolutional
along with a more than 3 dB better communications performance. code.
Index Terms— LDPC, energy, low power, iteration control, In this paper, the energy consumption of an LDPC decoder
implementation, WIMEDIA, UWB, decoder, architecture, FPGA is investigated. On system level we exploit an advanced
iteration control scheme which is investigated in a WIMEDIA
UWB environment. Simulations show the saving of iterations
I. I NTRODUCTION without losing any communications performance. Thus itera-
tion control can efficiently be exploited to save energy in the
The existing WIMEDIA UWB standard [1] for short range decoding process.
devices specifies a data rate of up to 480 Mbit/s within a The dynamic energy consumption of decoder architectures
range of around 2 m. The currently deployed channel coding is mainly determined by the internal capacitances, register and
scheme is based on traditional convolutional code (CC) with memory accesses and toggling rates which are strongly data
a constraint length K = 7 and code rates between 1/3 and dependent. Hence it is important to use a sufficiently large
3/4. By using an LDPC code as channel code, a very large and representative data set for energy estimation. Software
coding gain can be achieved [2][3][4][5]. It was shown that simulations are inappropriate: energy models of simulations on
the implementation complexity in sense of silicon area of high abstraction levels are too inaccurate, on the other hand,
such an LDPC decoder is below 0.3 mm2 using a 65 nm simulations on gate or transistor levels require an enormous
technology from STMicroelectronics [6]. Due to those facts large computation time. Hence we decided to use a rapid
we are going to propose the LDPC decoder to incorporate prototype environment and to perform real measurements.
into the WIMEDIA UWB standard. Both decoder systems, i.e. CC and LDPC decoder, are mapped
LDPC codes were invented by Gallager in 1963 [7]. They onto this platform which is based on a Xilinx Virtex-4 FPGA.
were almost forgotten for nearly 30 years because of their im- The platform is fed with data extracted from the UWB
plementation complexity and rediscovered by MacKay in the simulation chain [2]. It is well known that energy values
mid-90s and enhanced to irregular LDPC codes by Richardson from FPGAs can not be one-to-one transfered to an ASIC
et. al. in 2001 [8]. Now they are to be used for forward error implementation. But the purpose of our investigation is the
correction in a vast number of upcoming standards like DVB- relative comparison between a CC and LDPC decoder and it
S2 [9], WiMax (IEEE 802.16e) [10], and wireless LAN (IEEE is a feasible assumption that the relative comparison is also
802.11n) [11]. Providing very high decoding throughput and valid for an ASIC implementation.
outstanding communications performance, they will probably The paper is structured as follows: Section II gives a short
 Parameter Value
A. WIMEDIA Convolutional Code and Viterbi Algorithm
Data rate 53Mbit/s to 960Mbit/s
Data carriers 100 The WIMEDIA UWB standard system currently uses a non
FFT size 128 points systematical convolutional code with rate 1/3 which can be
Symbol Duration 312.5ns (incl. Guard)
Channel Coding CC with K = 7
adapted by puncturing (erasing some parity bits) to the rates
11/32 , 1/2 , 5/8 and 3/4. The encoder is a simple 6-step shift
LDPC Code
Carrier Modulation QPSK, DCM, 16-QAM register with the following taps for the parities p1 to p3 in
Channel Models CM1, CM2, CM3, CM4 polynomial form:
TABLE I p1 = {1, 0, 1, 1, 0, 1, 1}
WIMEDIA P HYSICAL LAYER PARAMETERS
p2 = {1, 1, 1, 0, 1, 0, 1}
overview over the WIMEDIA UWB system, followed by p3 = {1, 1, 1, 1, 0, 0, 1}
an introduction to LDPC codes and its decoding algorithms The decoding of the CC code at the receiver is done by the
in Section III. Section IV concentrates on the custom-built soft input Viterbi algorithm, which means that the decoder uses
LDPC code for the operation an an UWB system. Section V soft-information for decoding but the results are hard decoded
introduces into the various iteration control techniques whereas bits. The Viterbi algorithm (VA) was introduced in 1967 as
Section VI describes the architecture of our LDPC decoder. a method to decode binary convolutional codes [12]. The VA
Results of software simulations, implementation complexity finds the most likely sequence of state transitions (a path)
and power measurements are presented in the Section VII. through a trellis with a finite number of N states S (m) , given
Section VIII concludes the paper. by the sequence of received symbols y. In other words the
VA gives us the most likely codeword which was sent. This
II. WIMEDIA UWB S YSTEM M ODEL property is known as Maximum Likelihood (ML) decoding.
The basic
idea of the VA is quite simple. A branch
The WIMEDIA UWB standard is based on a multiband m,m
metric γk,k+1 is assigned to each possible state transition
OFDM air interface with and without frequency hopping. The (m) (m
)
Sk → Sk+1 . In each decoding cycle and for all states the
overall US UWB band ranging from 3.1 GHz to 10.6 GHz
path with the best sum of the transition metrics, called the
is split into 14 subbands using 528 MHz of bandwidth with
local survivor, is selected. The decision bits indicating the
128 OFDM subcarriers. The subbands are grouped to form
local survivor for each state and each trellis cycle are stored
5 band groups. Four of them contain 3 subbands and one
in a survivor memory. In a proceeding traceback step the local
consists of 2 subbands. In this paper we will focus on the
survivors are read from this memory back in time to extract
first band group ranging from 3.1 GHz to 4.8 GHz. In order to
the most likely sequence.
evaluate the communications performance of the WIMEDIA
UWB standard a SystemC based simulation chain has been III. LDPC C ODES
implemented for the full data path of the system. The basic LDPC codes are linear block codes defined by a sparse
structure of the simulation chain and thus the WIMEDIA binary matrix H, called the parity check matrix. The set of
UWB transmission and receiver chain is depicted in Figure 1. valid codewords C satisfies
The WIMEDIA uses a standard convolutional coding
scheme with a constraint length of K = 7. For the purpose of HxT = 0, ∀x ∈ C. (1)
this paper an LDPC encoder has been added to the standard A column in H is associated to a codeword bit, and each
chain. After the channel coding the coded data stream is row corresponds to a parity check. A nonzero element in
interleaved and then mapped onto QPSK symbols for the lower a row means that the corresponding bit contributes to this
data rates and DCM or 16-QAM symbols for the higher data parity check. The complete code can best be described by a
rates ranging from 300 Mbit/s to 960 Mbit/s. These symbols Tanner graph [8], a graphical representation of the associations
are then used in the OFDM modulator to generate the OFDM between code bits and parity checks. Code bits are shown
symbols to be transmitted over the channel. The channel as so called variable nodes (VN) drawn as circles, parity
models used correspond to the IEEE 802.15.3a channels CM1 checks as check nodes (CN) represented by squares, with
to CM4 [1][2]. The needed hopping sequences for the TFI edges connecting them accordingly to the parity check matrix.
mode are generated by the channel models. Figure 2 shows a Tanner graph for a generic LDPC code with
In the receiver the signal is demodulated and equalized N variable and M check nodes with a resulting code rate of
using an MMSE equalizer with an ideal LLR calculation. R = (N − M )/N .
In the presented simulation results ideal channel estimation The number of edges supplying each node is called the node
is assumed. The resulting demapped and deinterleaved soft- degree. If the node degree is constant for all CNs and VNs,
information is then processed by the channel decoder which the corresponding LDPC code is called regular, otherwise it
is either a Viterbi decoder or an LDPC decoder. is called irregular. Note that the communications performance
The key parameters of the WIMEDIA UWB system are of an irregular LDPC code is known to be generally superior
depicted in Table I. to which of regular LDPC codes. The degree distribution
 with λch the corresponding channel LLR of the VN and λl
the LLRs of the incident edges. The check node LLR update
can be done in an either optimal or suboptimal way, trading
off implementation complexity against communications per-
formance. For our studies only the suboptimal way is relevant.

C. Suboptimal Decoding
The simplest suboptimal check node algorithm is the well-
known Min-Sum algorithm [14], where the incident message
with the smallest magnitude determines the output of all other
Fig. 2. Tanner graph for an irregular LDPC code messages:
of the VNs f[dmax ,...,3,2] gives the fraction of VNs with a c −1
d
v
certain degree, with dmaxv the maximum variable node degree. λk = sign(λl ) · min (|λl |). (3)
l=0,l
=k
The degree distribution of the CNs can be expressed as l=0,l
=k
max
g[dmax
c ,dmax
c −1] with dc the maximum CN degree, meaning The resulting performance comes close to the optimal Sum-
that only CNs with two different degrees occur [13]. Product algorithm only for high rate LDPC codes (R ≥ 3/4)
To obtain a good communications performance of an LDPC with relatively large CN degree dc . It can be further optimized
code the degree distribution should be optimized with respect by multiplying each outgoing message with a message scaling
to the codeword size N . The degree distribution can be factor (MSF) of 0.75. For lower code rates the communications
optimized by density evolution as shown in [13]. Furthermore, performance strongly degrades.
the resulting Tanner graph should have cycles as long as
possible to ensure that the iterative decoding algorithm works D. Layered Decoding
properly. A cycle in the Tanner graph is defined as the shortest Layered decoding applies a different message schedule than
path from a VN back to its origin without traveling an edge the classical two-phase decoding. It was originally proposed
twice. Especially cycles of length four have to be avoided [8]. by Mansour [15] and denoted as turbo decoding message
IV. UWB LDPC C ODES passing (TDMP), then it was referred to as layered decoding
A. UWB LDPC Code Design by Hocevar [16]. The basic idea is to process a subset of CNs
and to pass the newly calculated messages immediately to the
Fulfilling the latency constraints of the UWB system (less
corresponding VNs. The VNs update their outgoing messages
than 2 µs) in conjunction with a small resulting decoder silicon
in the same iteration. The next CN subset will thus receive
area was one of the major prerequisites. To guarantee these
newly updated messages which improves the convergence
we had to design an ultra sparse LDPC code [2][6]. The
speed and therefore increases communications performance
chosen degree distribution is f[3,2] = { 3/4, 1/4} for the variable
for a given number of iterations [17]. In Section VI we present
nodes and g[11] = {1} for the check nodes. It is important to
a partly-parallel architecture for layered decoding, processing
note that an LDPC code with a denser degree distribution,
each of these subsets in parallel.
i.e. f[6,3,2] = { 1/4, 1/2, 1/4} and g[14] = {1} can gain up to
0.5 dB in terms of communications performance compared to V. I TERATION C ONTROL
our chosen one. However, the resulting decoder would result
Iterative decoding algorithms show an inherent dynamic
in a twice as large silicon area compared to our approach.
behavior, i.e. the number of iterations strongly depends on
Furthermore, the layered constraint could not be preserved
the signal-to-noise ratio which changes over time. Instead of
which would involve a high throughput penalty.
using a fixed number of iterations, the number of iterations can
B. Decoding Algorithm be controlled by an intelligent iteration control mechanism. In
LDPC codes can be decoded using the message passing al- [18] it was shown that iteration control is the most efficient
gorithm [7]. It exchanges soft-information iteratively between technique for energy saving in a turbo decoder system without
variable and check nodes. Updating the nodes can be done sacrificing communications performance. The arguments are
with a canonical, two-phased scheduling: In the first phase also valid for LDPC decoding.
all variable nodes are updated, in the second phase all check An efficient iteration control has to distinguish between
nodes respectively. The processing of individual nodes within decodable and undecodable blocks. LDPC codes already pro-
one phase is independent and can thus be parallelized. The vide an implicit stopping criterion for decodable blocks by
exchanged messages are assumed to be log-likelihood ratios simply checking for an all-zero syndrome if a codeword has
(LLR). Each variable node of degree dv calculates an update been successfully decoded, see Equation 1. Normally only this
of message k according to: stopping criterion is used in state-of-the-art implementations.
v −1
d
More advanced stopping criteria tackle especially the unde-
λk = λch + λl , (2) codable codewords. As soon as a codeword is most certainly
l=0,l
=k too corrupted to be successfully decoded, the decoder stops
its decoding process. This approach puts the LDPC decoder The input channel values as well as the extrinsic information
in idle mode (i.e. clock gating is activated on gate level) in in the message RAM are represented by 6 bit values, an
low SNR regions instead of wasting the maximum number of a posteriori message in the channel RAM is represented
iterations all the time and thus wasting energy. We apply the by 9 bit. This quantization parameters could be changed to
stopping criterion presented in [19] to evaluate the achievable further reduce the resulting VLSI area at the possible cost of
energy savings for the WIMEDIA UWB environment. This communications performance.
stopping criterion is based on a monitoring of the variable
nodes reliability (V N R). VII. R ESULTS
dm In this section simulation results of iteration control in the

v −1

N −1
Λ m
= λm + λm V NR = |Λ |
m WIMEDIA UWB simulation chain are given. Furthermore
ch l , (4)
l=0 m=0
implementation results on the rapid prototyping platform and
energy measurement results are presented.
The V N R is the sum of the absolutes of all intermediate
VN results. The calculation of this value has a very low A. Simulation Results
implementation complexity. The decoding process is stopped if We selected the 16-QAM case with an air data rate of 960
the V N R does not change or decreases within two successive Mbit/s and the 128 point FFT for our simulations. The input
decoding iterations. The stopping criterion has to be switched quantization is 6 Bit for the LDPC and 4 Bit for the Viterbi
off when the V N R passes a threshold (V N Rof f ) which is decoder, which leads to a communications performance loss
SNR dependent. This threshold has to be determined only less than 0.2 dB in comparison to a floating point implemen-
once for each code rate [20]. With an appropriate V N Rof f tation. This is a good compromise between implementation
the loss in communications performance can be decreased to complexity and communications performance degradation.
zero. For more detailed information on this criterion the reader Figure 3 shows the average number of iterations for various
is referred to [20]. SNRs with the inherent LDPC stopping criterion only and
VI. LDPC D ECODER A RCHITECTURES the combined criteria for decodable and undecodable blocks
This chapter gives a summary of the decoder architecture, presented in the previous section. We can make the following
more detail can be seen in [2]. A partly parallel architecture observations:
template is sufficient to ensure the throughput for the UWB • In the error floor SNR region (above 23 dB) the inherent
LDPC decoder. A parallelization of P is established, which stopping criterion reduces the number of iterations for
means that P edges are processed per clock cycle. To ensure decodable blocks to 3.
code rate and codeword size flexibility the functional nodes • In the waterfall SNR region (15 to 23 dB) the combined
are realized in a serial manner. Thus each functional unit can criteria yields a maximum average number of iterations of
accept one message per clock cycle as already mentioned. only 5.5. That means that the iteration control mechanism
The mapping of the VNs and CNs to the functional units is can save up to 32% of iterations which yields a substantial
determined by the given code structure. Efficient mapping of energy saving.
the nodes to the functional units can be always guaranteed • The detection mechanism for undecodable blocks gives
by designing LDPC codes using permuted identity matrices. the highest gain in the non-convergence SNR region
Always I VNs/CNs with the connection described by an I-by- (below 15 dB). It saves up to 4.5 iterations, i.e. 45%,
I identity matrix are allocated to I distinct VFU and I distinct assuming a maximum number of 8 iterations.
CFU respectively. This was shown by many LDPC decoder The threshold V N Rof f for the iteration control for unde-
realizations ([21][22][23][24]) as well as in the case of DVB- codable blocks is selected in such a way that the commu-
S2 LDPC decoding [25]. The parallelization P is determined nications performance loss is lower than 0.01 dB, which is
by the identity matrix size I [2]. depicted in Figure 4. This figure shows that the coding gain
A permutation network has to realize the permutation of of the LDPC code compared to the convolution code is more
the identity matrix what can be done by a barrel shifter. To than 4 dB at a PER of 10−3 for this configuration setup.
reach reasonable communications performance and minimize
the area consumption, the check nodes are implemented with B. Implementation Results
an optimized version of the Min-Sum algorithm (Section IV- As already addressed in the introduction, we used a rapid
C). prototyping environment for energy estimation. This rapid
It applies layered decoding as described in Section IV-D at prototype environment is based on a Virtex-4 FPGA. To allow
which the VN processing can be done within the check node a fair comparison with our LDPC decoder, we used the Xilinx
block (CNB). This is achieved by storing the input information Viterbi IP core [26]. The Xilinx Viterbi decoder is a highly
of the CFU in a FIFO and adding the new extrinsic information optimized IP block. Both decoders were configured such that
to the corresponding input message in the FIFO. Thus the they show the same throughput.
correct a posteriori information is passed back to the channel The Viterbi and LDPC decoder were both implemented
memory which holds always the updated VN information. This using the Xilinx ISE 9.1 tool chain. High effort and area
basic concept was first presented in [15]. optimization was selected in conjunction with a 100 MHz
 8
Number of Iterations with enhanced stopping criterion
LDPC Code f[3,2] = { 3/4, 1/4}
Number of Iterations with inherend stopping criterion only g[11] = {1}
7
Codeword Size 1200 bit
Code Rate 3/4
6
Parallelism 30
Quantization 6 bit
Number of average Iterations

5
Algorithm MinSum+MSF,
Layered Decoding
4
Iterations 8
Comm. Perform. see Figure 4, [2]
3
Xilinx FPGA Virtex-4 XC4VLX60-10 @100 MHz
LUTs 9,497
2
FlipFlops 4,310
Slices 5,996
1
non−convergence
BRAMs 13
waterfall error−floor
Region Region region Throughput 100 Mbit/s
0
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
Eb/N0 / dB
TABLE II
Fig. 3. Average number of iteration of the LDPC decoder vs. SNR I MPLEMENTATION RESULTS FOR UWB-LDPC DECODER
0
10

CC Code CC Code non-systematic

LDPC w inherend stopping criterion only
LPDC w advanced stopping criterion
rate 1/3
Codeword Size 1200 bit
Code Rate 1/3 to 3/4
−1
Implementation style parallel
10
identical performance
Input Quantization 4 bit
of both LDPC codes
Algorithm Soft input Viterbi
Comm. Perform. see Figure 4, [2]
PER

Xilinx FPGA Virtex-4 XC4VLX60-10 @100 MHz

LUTs 3,547
10
−2 FlipFlops 1,537
Slices 2,613
BRAMs 3
waterfall error−floor Throughput 100 Mbit/s
Region region

−3
TABLE III
10
15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Eb/N0 / dB I MPLEMENTATION RESULTS FOR X ILINX CC V ITERBI DECODER
Fig. 4. Communications performance of LDPC code with and without
advanced stopping criterion vs. CC code decoder consumes the same energy as the CC running with
7.5 iterations. In Figure 6 the mean energy consumption for
clock frequency constraint. Table II shows the results for the decoding per block vs. the singal to noise ratio is figured out.
LDPC decoder and the design space parameters. Table III In case of using only the inherent stopping criterion the LDPC
shows the corresponding parameters for the CC decoder. Input code only in the non-convergence region needs more energy
and output RAMs which have the same size for both decoders for decoding in mean. Combining the energy/iteration with
are included in these numbers. the iteration numbers of Figure 3, the LDPC decoder with
Both decoders achieved an equal net throughput of iteration control consumes in all cases less energy in mean than
100 Mbit/s, or 1 bit/clock cycle. Since the LDPC decoder is the Viterbi decoder for decoding one codeword. Moreover the
highly scalable, its throughput can be easily increased [2]. convolutional decoder requires a channel interleaver to reach
a reasonable communications performance. This interleaver
C. Energy Measurements Results
consumes additional energy which has to be added to the
We measured the core power of the decoders including the Viterbi energy consumption of the CC itself.
input and output RAMs for each decoder respectively. Before
starting the measurements the input RAM was loaded with
representative data extracted from the UWB simulation chain. Summarizing the energy consumption of the LDPC decoder
After loading we started the decoding process and measured is smaller than the energy consumption of the Viterbi decoder
the power and the decoding time to calculate the energy for the same throughput assuming realistic data sets. Since we
consumption, i.e. reading the input RAMs and writing the measured the energy on an FPGA rapid prototyping board,
results into the output RAM are included in the corresponding the absolute values can not be directly transferred to an
energy budget. ASIC implementation. However it is feasible to conclude that
Figure 5 shows the measured energy consumption of the two the relative energy behavior of both decoders in an ASIC
decoders. Since the LDPC decoding is an iterative process, implementation is the same, i.e. the LDPC decoder consumes
we measured the energy for varying numbers of decoding less energy than a Viterbi decoder in an ASIC implementation,
iterations, ranging from 2 to 8. It can be seen that the LDPC too.
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x 10
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