University Visvesvaraya College of Engineering

K R Circle, Devaraj Urs Rd, Bengaluru

Mini-Project Work
“UART Protocol Using Xilinx Vivado”

Submitted in partial fulfilment for the award of Degree of

BACHELOR OF ENGINEERING
in
ELECTRICAL AND COMMUNICATION ENGINEERING

Submitted by
Rajeev G Y (20GAECE039) Under the Guidance of
Lohith R (20GAECE020) Dr B K Venugopal
Tharun Achari (20GAMEC054) Professor, Dept. of ECE, UVCE
Mallikarjun K (20GAEEE078)
 ACKNOWLEDGEMENT

We would like to thank our guide B K Venugopal, Professor, Electronics and Communication Department,
University Visvesvaraya College of Engineering, Bengaluru for guiding untiringly all through my tenure.

We would like to thank Dr. B P Harish, Head of the Department, Electronics and Communication ,
University Visvesvaraya College of Engineering, Bengaluru for this opportunity to present this Mini
Project on “UART Protocol Using Verilog” of our choice and interest.

We extend my gratitude to Dr. H N Ramesh ,Interim Director, University Visvesvaraya College of

Engineering, Bengaluru, for his encouragement and support.

We are fortunate for being part of University Visvesvaraya College of Engineering, the institution that stood
by our side and assisted us towards successfully completing the Mini Project. We also take this opportunity
to thank the Department of Electronics and Communication, University Visvesvaraya College of
Engineering for their tremendous help and guidance.

Rajeev G Y (20GAECE039)
Lohith R (20GAECE020)
Tharun Kumar Achari (20GAECE054)
Mallikarjun Karalatti (20GAECE021)
 ABSTRACT

This mini project presents the design and simulation of a Universal Asynchronous
Receiver/Transmitter (UART) protocol using Verilog HDL and Xilinx Vivado. The UART protocol
is a serial communication protocol that allows asynchronous communication between two devices. It
is widely used in embedded systems and microcontrollers for communication with peripherals such
as modems, keyboards, and serial displays.

The Universal Asynchronous Receiver/Transmitter (UART) protocol is a serial communication

protocol that is widely used in industries such as industrial automation, automotive, consumer
electronics, medical devices, aerospace and defense, telecommunications, networking, security,
point-of-sale systems, building automation, transportation, and energy. UART is a relatively simple
protocol to implement, and it is supported by a wide range of microcontrollers and other electronic
devices. This makes it a versatile and cost-effective solution for a wide range of communication
applications.The transmitter module works by first generating a start bit. The start bit is a low pulse
that is used to signal the beginning of a data transmission. After the start bit, the transmitter module
transmits the data bits one by one. The data bits are transmitted in the most significant bit (MSB) first
order. After the data bits, the transmitter module transmits one or two stop bits. The stop bits are high
pulses that are used to signal the end of a data transmission.

This mini project demonstrates the feasibility of designing and simulating a UART protocol using
Verilog HDL and Xilinx Vivado. The UART design can be used in embedded systems and
microcontrollers to communicate with serial peripherals.
 TABLE OF CONTENTS

CHAPTER CONTENT

CHAPTER 1: INTRODUCTION
1.1 Introduction

1.2 Communication

1.3 Baud Rate

1.4 UART Protocol

CHAPTER 2: METHODOLOGY
3.1 Introduction To Xilinx

3.2 Design Code

3.3 Testbench

CHAPTER 3: RESULTS

4.1 Simulation
 DEPARTMENT OF ELECTRONICS AND COMMUNICATION

VISION

Imparting Quality Education to achieve Academic Excellence in Electronics and Communication

Engineering for Global Competent Engineers.

MISSION

 Create state of art infrastructure for quality education.

 Nurture innovative concepts and problem solving skills.
 Delivering Professional Engineers to meet the societal needs.

PROGRAM EDUCATIONAL OBJECTIVES

 Prepare graduates to be professionals, Practicing engineers and entrepreneurs in the field of Electronics
and communication.

 To acquire sufficient knowledge base for innovative techniques in design and development of
systems.

 Capable of competing globally in multidisciplinary field.

 Achieve personal and professional success with awareness and commitment to ethical and social
responsibilities as an individual as well as a team.
 Graduates will maintain and improve technical competence through continuous learning process.

PROGRAM SPECIFIC OUTCOMES

 PSO1: Core Engineering: The graduates will be able to apply the principles of Electronics and
Communication in core areas.
 PSO2: Soft Skills: An ability to use latest hardware and software tools in Electronics and
Communication engineering.
 SO3: Successful Career: Preparing Graduates to satisfy industrial needs and pursue higher studies
with social-awareness and universal moral values.
 CHAPTER 1
INTRODUCTION
CHAPTER 1

INTRODUCTION
1.1 Introduction

Very-large-scale integration (VLSI) is the process of designing and manufacturing integrated circuits (ICs)
with millions or billions of transistors on a single chip. VLSI is used to create a wide variety of electronic
devices, including microprocessors, memory chips, telecommunications chips, and consumer electronics.
VLSI has revolutionized the electronics industry by making it possible to create complex and powerful
electronic devices at a low cost. VLSI is also used to create custom ICs for specific applications, such as
medical devices, aerospace systems, and military equipment.

The Universal Asynchronous Receiver/Transmitter (UART) is a serial communication protocol that is used
to transmit and receive data between two devices. It is a very simple protocol, but it is also very versatile and
can be used in a wide variety of applications.

One of the most common uses of UART is in embedded systems. Embedded systems are small, specialized
computers that are found in a wide variety of devices, such as cars, appliances, and industrial controllers.
UART is used to connect the embedded system to other devices, such as sensors, actuators, and displays.
UART is a very versatile and widely used communication protocol. It is essential for many modern
technologies and is used in a wide variety of devices, from cars to smartphones to medical devices.

Xilinx Vivado is a software suite that is used to design and simulate VLSI systems. Vivado includes a
library of pre-designed IP cores, including a UART core.

To simulate a UART communication protocol in Vivado, simply instantiate the UART core in your design
and connect it to the appropriate signals. Once your design is complete, you can simulate it to test its
functionality.

1.2 Communication

Communication in electronics is the transmission of information from one point to another using electronic
signals. Electronic signals can be analog or digital.

Analog communication uses signals that can vary continuously over time. This means that the signal can
take on any value within a certain range. Analog signals are often used to represent physical quantities, such
as sound, light, and temperature.

Digital communication uses signals that can only take on two values, such as high and low, or 0 and 1. This
makes digital signals much easier to process and transmit than analog signals. Digital signals are often used
to represent text, data, and images.

Analog communication systems typically use analog modulation techniques to transmit the analog signal
over a communication channel. Analog modulation techniques involve changing the amplitude, frequency,
or phase of a carrier signal to represent the analog signal.

Digital communication systems typically use digital modulation techniques to transmit the digital signal
over a communication channel. Digital modulation techniques involve encoding the digital signal into a
sequence of symbols, which are then transmitted over the communication channel.
Digital signal is further divided into two types with respect to use of clocks which are:

 Synchronous communication

 Asynchronous communication

Synchronous communication uses a clock signal to synchronize the sender and receiver. This means
that the sender transmits the data at a predetermined rate, and the receiver uses the clock signal to determine
when to sample the data. Synchronous communication is typically used in high-speed applications where
data integrity is important, such as in digital communication systems and computer networks.

Asynchronous communication does not use a clock signal to synchronize the sender and receiver.
Instead, the sender transmits the data at its own pace, and the receiver uses start and stop bits to determine
the beginning and end of each data byte. Asynchronous communication is typically used in low-speed
applications where data integrity is less important, such as in serial communication ports and modems.

1.3 Baud Rate

Baud rate, also known as symbol rate, is the unit of measurement for the number of discrete symbol changes
made to the transmission medium per second in a digitally modulated signal. It is measured in bauds (Bd).It
is often confused with bit rate, which is the number of bits transmitted per second. However, the two are not
necessarily the same. For example, if a modulation scheme uses two symbols to represent a single bit, then
the baud rate will be twice the bit rate.

Baud rate is an important factor in determining the maximum speed at which data can be transmitted over a
communication channel. It is also used to calculate the bandwidth requirements for a transmission.

The most frequently used Baud rate for asynchronous communication is 9600 baud and is used for serial
communication. Baud rate is a critical concept in telecommunications and digital electronics. It is used to
design and configure communication systems and devices.

1.4 UART Protocol

UART stands for Universal Asynchronous Receiver/Transmitter. It is a serial communication protocol

that is widely used in embedded systems, microcontrollers, and other electronic devices. UART
communication is asynchronous, which means that the transmitting and receiving devices do not need to
share a common clock signal. Instead, the start and stop bits are used to frame the data bytes and
synchronize the communication. UART communication uses two wires: one for transmitting data and the
other for receiving data. The data is transmitted bit by bit, with the start bit preceding the data bytes and the
stop bit following the data bytes. The start bit is a low voltage signal that indicates the beginning of a new
data byte. The stop bit is a high voltage signal that indicates the end of a data byte.

UART communication can be simplex, half-duplex, or full-duplex. Simplex communication is one-way

communication, where only one device can transmit data at a time. Half-duplex communication is two-way
communication, but only one device can transmit data at a time. Full-duplex communication is two-way
communication, where both devices can transmit and receive data simultaneously.
The baud rate is the speed at which data is transmitted over the UART interface. The baud rate is measured
in bits per second (bps). The most common baud rates for UART communication are 9600 bps, 19200 bps,
38400 bps, 57600 bps, and 115200 bps.

UART communication is a simple and reliable way to transmit data between two devices. It is widely used
in a variety of applications, including:

 Serial communication between microcontrollers and other embedded devices

 Communication between computers and peripherals such as modems and printers
 Communication between devices in industrial control systems
 Communication between devices in the Internet of Things (IoT)

UART communication is a versatile and widely used protocol. It is a key component of many electronic
devices and systems.

Here are some of the advantages of using UART communication:

 Simple to implement and configure

 Reliable and efficient
 Widely supported by a variety of devices and systems
 Low cost

Here are some of the disadvantages of using UART communication:

 Limited bandwidth
 No error checking (optional parity bit can be used)
 Asynchronous communication, so both devices must be configured to use the same baud rate
 CHAPTER 2
METHODOLOGY
CHAPTER 2
METHODOLOGY

2.1 Introduction To Xilinx

Xilinx Vivado Design Suite is a comprehensive software suite for the design and implementation of Xilinx
FPGAs and adaptive SoCs. It includes a wide range of tools for design entry, synthesis, place and route,
timing closure, verification, and debugging. Vivado is also highly integrated with Xilinx's IP Integrator tool,
which enables designers to quickly and easily integrate pre-defined IP blocks into their designs.

Vivado supports design entry in traditional HDL languages, such as VHDL and Verilog. It also supports a
graphical user interface-based tool called the IP Integrator, which enables designers to quickly and easily
integrate pre-defined IP blocks into their designs. Xilinx Vivado Design Suite is a powerful and
comprehensive software suite for the design and implementation of Xilinx FPGAs and adaptive SoCs. It is
used by engineers and researchers around the world to create a wide range of applications, from high-
performance computing to machine learning to automotive systems.

2.1 Design Code

The design Code is written using Verilog as a descriptive language.

1. timescale 1ns / 1ps
2.
3. module top(
4. input clk,
5. input start,
6. input [7:0] txin,
7. output reg tx,
8. input rx,
9. output [7:0] rxout,
10. output rxdone, txdone
11. );
12.
13. parameter clk_value = 100_000;
14. parameter baud = 9600;
15.
16. parameter wait_count = clk_value / baud;
17.
18. reg bitDone = 0;
19. integer count = 0;
20. parameter idle = 0, send = 1, check = 2;
21. reg [1:0] state = idle;
22.
23. ///////////////////Generate Trigger for Baud Rate
24. always@(posedge clk)
25. begin
26. if(state == idle)
27. begin
28. count <= 0;
29. end
30. else begin
31. if(count == wait_count)
32. begin
33. bitDone <= 1'b1;
34. count <= 0;
35. end
36. else
37. begin
38. count <= count + 1;
39. bitDone <= 1'b0;
40. end
41. end
42.
43. end
44.
45. ///////////////////////TX Logic
46. reg [9:0] txData;///stop bit data start
47. integer bitIndex = 0; ///reg [3:0];
48. reg [9:0] shifttx = 0;
49.
50.
51. always@(posedge clk)
52. begin
53. case(state)
54. idle :
55. begin
56. tx <= 1'b1;
57. txData <= 0;
58. bitIndex <= 0;
59. shifttx <= 0;
60.
61. if(start == 1'b1)
62. begin
63. txData <= {1'b1,txin,1'b0};
64. state <= send;
65. end
66. else
67. begin
68. state <= idle;
69. end
70. end
71.
72. send: begin
73. tx <= txData[bitIndex];
74. state <= check;
75. shifttx <= {txData[bitIndex], shifttx[9:1]};
76. end
77.
78. check:
79. begin
80.
81.
82. if(bitIndex <= 9) ///0 - 9 = 10
83. begin
84. if(bitDone == 1'b1)
85. begin
86. state <= send;
87. bitIndex <= bitIndex + 1;
88. end
89. end
90. else
91. begin
92. state <= idle;
93. bitIndex <= 0;
94. end
95. end
96.
97. default: state <= idle;
98.
99. endcase
100.
101. end
102.
103. assign txdone = (bitIndex == 9 && bitDone == 1'b1) ? 1'b1 : 1'b0;
104.
105.
106. ////////////////////////////////RX Logic
107. integer rcount = 0;
108. integer rindex = 0;
109. parameter ridle = 0, rwait = 1, recv = 2, rcheck = 3;
110. reg [1:0] rstate;
111. reg [9:0] rxdata;
112. always@(posedge clk)
113. begin
114. case(rstate)
115. ridle :
116. begin
117. rxdata <= 0;
118. rindex <= 0;
119. rcount <= 0;
120.
121. if(rx == 1'b0)
122. begin
123. rstate <= rwait;
124. end
125. else
126. begin
127. rstate <= ridle;
128. end
129. end
130.
131. rwait :
132. begin
133. if(rcount < wait_count / 2)
134. begin
135. rcount <= rcount + 1;
136. rstate <= rwait;
137. end
138. else
139. begin
140. rcount <= 0;
141. rstate <= recv;
142. rxdata <= {rx,rxdata[9:1]};
143. end
144. end
145.
146.
147. recv :
148. begin
149. if(rindex <= 9)
150. begin
151. if(bitDone == 1'b1)
152. begin
153. rindex <= rindex + 1;
154. rstate <= rwait;
155. end
156. end
157. else
158. begin
159. rstate <= ridle;
160. rindex <= 0;
161. end
162. end
163.
164.
165. default : rstate <= ridle;
166.
167.
168. endcase
169. end
170.
171.
172. assign rxout = rxdata[8:1];
173. assign rxdone = (rindex == 9 && bitDone == 1'b1) ? 1'b1 : 1'b0;
174.
175.
176. endmodule
177. //////////////////////////////////
2.1 Testbench Code

Testbench code is a type of code that is used to verify the functionality of a hardware design. It is
written in Verilog

1. module tb;
2.
3. reg clk = 0;
4. reg start = 0;
5. reg [7:0] txin;
6. wire [7:0] rxout;
7. wire rxdone, txdone;
8.
9. wire txrx;
10.
11. top dut (clk, start, txin, txrx,txrx, rxout, rxdone, txdone );
12. integer i = 0;
13.
14. initial
15. begin
16. start = 1;
17. for(i = 0; i < 10; i = i + 1) begin
18. txin = $urandom_range(10 , 200);
19. @(posedge rxdone);
20. @(posedge txdone);
21. end
22. $stop;
23. end
24.
25. always #5 clk = ~clk;
26.
27. endmodule
CHAPTER 3
RESULT
3.1 Simulation

After writing the design code for UART Communication Protocol, now we add Testbench to verify the
working of the Design code. The behaviour of the UART can be seen in both in digital and analog waveform
which verifies its working.
The behaviour can be explained in the below waveform.

The above simulation the message to be transferred at ‘txin’ is given that is ‘42’ and it is received at the
receiver ‘rxout’. This is transferred serially with fixed baud rate.