PIDcontrollerIPCoreusermanual

Author:ZhuXu
Email:[email protected]


Introduction
The PID controller IP core performs digital proportional–integral–derivative
controller (PID controller) algorithm. The algorithm first calculates the error
between a measured value (PV) and its ideal value (SP), then use the error as an
argumenttocalculatethemanipulatevalue(MV).TheMVwilladjusttheprocessto
minimize the error. It can be used to calculate duty cycle for PWM (Pulse Width
Modulation).


Features
• 16-bitsignedcoefficientanddatainput:Kp,Ki,Kd,SPandPV.
• 32-bitsignedu(n)output.
• Containing one high speed 32-bit prefix-2 Han-Carlson adder and one high
speedpipelined16x16-bitmultiplier.
• Latency from input of PV to finished calculation and update of u(n) is 17clock
cycles.
• Ki,Kp,Kd,SP,PVcanbeupdatedanytimeafterreset.
•  After every update of Kp or Kd, register Kpd which stores Kp+Kd will be
calculatedandupdated.
• AftereveryupdateofPV,calculationandupdateofe(n),e(n-1),sigmaandu(n)
willbetriggeredinsequence.
• OverflowregisterrecordsoverflowsignalswhencalculatingKpd,e(n),e(n-1),u(n)
andsigma.
• Using2278of4608(49%)CoreCells inActelA2F200M3FFPGAandrunningat
100MHzclockfrequency.
• WishboneB4compliantinterface.Support16-bit,32-bitand64-bitbuswidth.


PIDcontrollerdescription
BelowdescribethealgorithmofPIDcontroller.

Analog
APIDismadeofthreebasicblockswhoseoutputsare:
• Proportionaltotheinput
• Theintegraloftheinput

1
• Thederivativeoftheinput

Figure1showstheblockdiagramofagenericsystemcontrolledbyPIDcontroller.
The goal of the PID block is to generate an output u(t) that drives the systemat
hand (the “PLANT”) so that its output [y(t) or PV, Process Value] matches a
referencesignal[x(t)orSP,SetPoint].TheinputtothePIDistheerrorbetweenthe
reference signal (ideal or desired behavior of the PLANT) and the real output
behavior.Obviously,thetargetistogettheerrorasclosetozeroaspossible.


Figure1:agenericsystemcontrolledbyPID

TheequationthatdescribesthePIDcontrollerbehaviorincontinuoustimedomain
isshowninequation1.



Equation1


Digital
Transformequation1intodiscretetimedomainwegetequation2.

n
u (n )  (K p  K d )e(n )  K i  e( j)  K d e(n  1)
j1

Equation2

Fromequation2wecanconstructthealgorithm′sblockdiagramshowninfigure2.


2
 Figure2:digitalPIDcontrolleralgorithm



Operation

Coefficients and Data Update
Coefficients(Kp,Ki,Kd,PV)andmeasuredprocessvalue(PV)arestoredindifferent
registersthatbereadandwrittenanytimeafterresetbyahostthroughWishbone
slave interface. Normally, Kp, Ki, Kd, PV are updated right after reset before
continuouslyupdateofPV.Youalsocanupdatecoefficientsrandomlyfordynamic
tuning.Writingactiontospecificregistersmentionedabovewon‛tberesponded
untilfinishedcalculationofthelastu(n).

Calculation of u(n)
Calculation of u(n) will be triggered every time PV is updated. The calculation
procedureisdemonstratedinfigure3.

Update of overflow register
OverflowregisterrecordsanyoverflowsignalinpreviouscalculationsofKpd,e(n),
e(n-1),u(n)andsigma.Itwillbeupdatedaftereveryadditionoperation.Ifanyof
the5overflowregisterbitsisset,thenthefinalu(n)isincorrect.

3
 Figure3:calculationprocedureofu(n)

Registers
Address for
Name 16-bit/32-bit/64-bit bus Width Access Description
width
Kp Base+0x0/0/0 16 R/W StorescoefficientKp
Ki Base+0x2/4/8 16 R/W StorescoefficientKi
Kd Base+0x4/8/10 16 R/W StorescoefficientKd
SP Base+0x6/C/18 16 R/W StoresreferenceSP
PV Base+0x8/10/20 16 R/W StoresPV
Kpd Base+0xA/14/28 16 R StorescoefficientKp+Kd
err[0] Base+0xC/18/30 16 R Storese(n)
err[1] Base+0xE/1C/38 16 R Storese(n-1)
un Base+0x10/20/40 32 R Storesu(n)
n

sigma Base+0x12/24/48 32 R Stores K i  e( j) 

of[0]==1ifKpdoverflows,
of[1]==1iferr[0]overflows,
of Base+0x14/28/50 5 R of[2]==1iferr[1]overflows,
of[3]==1ifunoverflows,
of[4]==1ifsigmaoverflows

4
I/Oports
TheIPcorehasaWishboneSlaveInterfaceandanotherinterfacefordirect32-bit
u(n)output.

Wishbone Slave Interface
It′sWishboneB4compliant.
Name in
Name Wishbone Size Direction Description
B4
i_clk CLK_I 1 input Clockinput
i_rst RST_I 1 input Resetinput
i_wb_cyc CYC_I 1 input Indicatesvalidbuscycle(coreselect)
i_wb_stb STB_I 1 input Indicatesvaliddatatransfercycle
i_wb_we WE_I 1 input Writetransactionwhenassertedhigh
i_wb_adr ADR_I 16 input Addressinput
i_wb_data DAT_I 16/32/64 input Datainput
Acknowledgment output (indicates
o_wb_ack ACK_O 1 output
normaltransactiontermination)
o_wb_data DATA_O 16/32/64 output Dataoutput

Direct 32-bit u(n) output
Name Size Direction Description
o_un 32 output u(n)output
o_valid 1 output Indicatesvalido_un