Microelectronic Circuits

EEE F244
BITS Pilani
Pilani Campus Anu Gupta
 BITS Pilani
Pilani Campus

Single Stage Amplifiers

Device gain
 Learnings
• MOSFET Intrinsic gain

• (CSA/ CEA), (CGA/ CBA), (SF/ EF)– schematics with active

passive load, (NMOS/ PMOS Config)

• small signal model, gain / o/p swing , input/ output

impedances calculation

• Types of active load

• CSA- SD/ CEA-ED---- Gm, Rout, Rin , gain calculations

• Cascode amplifier-Modification in CSA- SD/ CEA-ED for high Gm

• Two stage amplifier

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maximum Amplifier Voltage gain
= intrinsic gain of device
𝟏 𝑾 𝟐
𝑰𝑫 = 𝝁𝒏 𝑪𝒐𝒙 𝑽𝑮𝑺 − 𝑽𝑻
𝟐 𝑳

𝒗𝒐𝒖𝒕 𝒊𝒐𝒖𝒕 𝒗𝒐𝒖𝒕

𝑨𝒗 = = ×
𝒗𝒊𝒏 𝒗𝒊𝒏 𝒊𝒐𝒖𝒕
= 𝑮𝒎 × 𝑹𝒐𝒖𝒕
For device---
𝑮 𝒎 = 𝒈𝒎 , 𝑹𝒐𝒖𝒕 = 𝒓𝒐
Anu Gupta BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Max gain/ frequency of
MOSFET device as amplifier
Intrinsic voltage gain
[𝑔𝑚 𝑟𝑜 ]
Transit frequency
1 𝑔𝑚
𝑓𝑇 =
2𝜋 𝐶𝑔𝑠

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Small signal parameters
Id, gm, [gm/ Id]

1 𝑊 2
𝐼𝐷 = 𝜇𝑛 𝐶𝑜𝑥 𝑉𝐺𝑆 − 𝑉𝑇
2 𝐿

𝑊
𝑔𝑚 = 𝜇𝑛 𝐶𝑜𝑥 𝑉𝐺𝑆 − 𝑉𝑇
𝐿

Anu Gupta BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Small signal parameters
Id, gm, [gm/ Id]

1 𝑊 2
𝐼𝐷 = 𝜇𝑛 𝐶𝑜𝑥 𝑉𝐺𝑆 − 𝑉𝑇 1 + λ𝑉𝐷𝑆
2 𝐿

𝑾
𝒈𝒎 = 𝝁𝒏 𝑪𝒐𝒙 𝑽𝑮𝑺 − 𝑽𝑻 𝟏 + 𝝀𝑽𝑫𝑺
𝑳

𝟏 + 𝝀𝑽𝑫𝑺 typically neglected in manual calculations

for convenience
Anu Gupta BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
How to maximise gain in an amplifier at
given power constraint???

• We need to maximise gm for required

power dissipation or Ibias

• How to choose gm ???

𝑔𝑚
• Define a new figure of merit  shd.
𝐼𝐷
be large

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Guideline--To increase intrinsic gain by design,
choose L large

Keep L large
Keep Id small
1 1
∝ ; λ=
𝜆 𝐼𝐷 𝐿
Example---
Keeping (w/L) constant
L’= 4L, W’= 4W, I’ = I Vgs --same
Intrinsic gain= 4 times increase
Intrinsic gain’ ≈ [4] original intrinsic gain by properly
choosing L values
Cgs increases , so Transit freq. reduces

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Effect of technology scaling on
intrinsic gain (C E SCALING)
MOS scaled down by constant electric field scaling
strategy

(α > 1: usually α =1.33) All dimensions scale

down by a factor α:

All voltages scale down by a factor α

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Effect of increasing L on CSA
gain

Keeping I constt.-----

 L1, L2 scaled up by α, (ro1, ro2) increase

 W1, W2 also increase to keep ratio constant, so

gm remains same

 Hence CSA gain increases by ≈ α

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Effect of increasing only L

• Keeping I constt-----
L scaled up by α, ro increases
L scaled up, W also increases to keep
ratio constant, so gm remains same
Hence, intrinsic gain increases by α
Vgs increases, so Swing reduces
Effect of technology scaling on intrinsic gain (C E SCALING)

• Keeping W/L constt----- Vdd decreases by ,say, α

 L scaled down by α, W also decreases to keep ratio

constant,

 Cox, increases by α-----Id decreases by α---gm remains

constt.

 λ increases by α, Id decreases by α---ro constt.

 Hence intrinsic gain does not change

What do we really want??

What we really want from MOS transistor??

– Large gm without investing much current (less

power consumption)

– Large gm without having large Cgs (wide fT)

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Method 2 to maximise gain in an
amplifier at given power constraint

• We need to maximise gm for required

power dissipation or Ibias

• How to choose gm ???

𝑔𝑚
• Define a new figure of merit  shd.
𝐼𝐷
be large

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 gm/ Id—
Trans-conductance generation efficiency

1) It is strongly related to the performances (gain/ transit

frequency )of analog circuits

2) It gives an indication of the device operating region.

3) It provides a tool for calculating required transistors

dimensions

The gm/ID ratio is a measure of the efficiency to translate

current (hence power) into trans-conductance; i.e., the
greater the gm / ID value, the greater the trans-conductance
we obtain at a constant current value.
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Figure of merit [gm/ Id]
1 𝑊 2
𝐼𝐷 = 𝜇𝑛 𝐶𝑜𝑥 𝑉𝐺𝑆 − 𝑉𝑇
2 𝐿
𝑊
𝑔𝑚 = 𝜇𝑛 𝐶𝑜𝑥 𝑉𝐺𝑆 − 𝑉𝑇
𝐿
𝑔𝑚 2
=
𝐼𝐷 𝑉𝐺𝑆 − 𝑉𝑇
• Choose bias current using power consumption constraint
• If Choose small Vov. , then (W/L) increases for given
current , Si area increases, Cgs increases

• Hence, fT decreases???
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gm/ID value
graphs

• gm/ID Vs gm

• gm/ID Vs ID / (W/L)

• gm/ID Vs VOV

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 Intrinsic gain in terms of
gm ID
𝐴𝑉 = 𝑔𝑚 𝑟𝑜
𝑔𝑚
=− 𝑉𝐴
𝐼𝐷

1 𝑔𝑚
𝑓𝑇 =
2𝜋 𝐶𝑔𝑠
For amplifier,
UGB
1 𝑔𝑚
𝑓𝑈𝐺𝐵 =
2𝜋 𝐶𝐿
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Information from gm/Id plot

Anu Gupta
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Anu Gupta
Anu Gupta
 BITS Pilani
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Common Source/ Emitter Amplifier

CSA
CEA
CSA amplifier
with Drain-to Gate feedback bias

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CSA amplifier
with Potential Divider Bias

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CSA with current mirror bias

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Small signal analysis

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PMOS CSA

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Common Source

Bias point
Given--Kn’= 80uA/v2, Vt=1v, Vdd= 5v

Suppose, we want Id= 100uA, Vds= 2.5v,

This gives ----

Rd= 25k

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Design of common source amplifier
for gain specification
• To set gain
• Av= 30 = - gm [ RD || ro ]

• ro=1/ λId = 1M ohm; λ= .01V-1

• gm= 1.2 mA / V = 2 Id / Vov

• Hence, Vov= 0.166V [designers choice depends on

VDD, Small value for small supply ]
gm= 1.2 mA / V = Kn’ (w/L) Vov

• W/L= 90.3, Vgs= 1.166V

Practical Design steps

• Sketch VTC
• Choose bias current, choose a w/L
• Find corresponding Vgs, Vds, re calculate Rd,
w/L
• Draw the schematic in eda tool
• Set voltages by applying sources
• Do .dc analysis
• Check all dc current and voltages
• Apply ac , check ac output. Do .ac analysis

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i/o phase relation ship

Lagging Phase Difference

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Voltage Amplifier model of
CSA

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 BITS Pilani
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CSA/ CGA/ CDA

CEA/ CBA/ CCA
Low Frequency Operation
CSA/ CGA/ CDA

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Direct/ capacitively coupled
CGA

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Diff. ---- Low frequency / high
frequency performance

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MOSFET Capacitances

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Anu Gupta
Gain calculation
Small signal model

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CDA/ SF —
Av variation

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 BITS Pilani
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Rin, Rout, o/p voltage swing

ICMR, OCMR
GAIN and SWING
Compatibility
What if gain is high but not sufficient voltage
swing ?

• Output will be distorted as MOSFET slips in

LINEAR/ CUTOFF region

• Hence, output voltage swing calculation is

important

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Output voltage swing under dynamic
state
• Constraint---MOS must
remain in saturation
• Vo max≈Vdd
• Vomin Vgs-Vt
• OCMR-Output DC level[Vdd-IdRd]

Vdd= 3V
Reduced upper swing

Dc level

Reduced lower swing

Vgs-Vt = 0.2
For symm. signal—dc level shd. be in the middle for max swing
ICMR, OCMR

ICMR, OCMR---
Possible input/ output DC levels

𝑶𝑪𝑴𝑹 → 𝑽𝑫𝑫 − 𝑰𝑫𝑸 𝑹𝑫,𝒇𝒊𝒙𝒆𝒅 𝒗𝒂𝒍𝒖𝒆

I𝑪𝑴𝑹 → 𝑽𝑮𝑺𝟏 , 𝒇𝒊𝒙𝒆𝒅 𝒗𝒂𝒍𝒖𝒆

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ICMR, OCMR

Possible input/ output DC levels

𝑶𝑪𝑴𝑹 → 𝑽𝑫𝑫 − 𝑰𝑫𝑸 𝑹𝑫,𝒇𝒊𝒙𝒆𝒅 𝒗𝒂𝒍𝒖𝒆

I𝑪𝑴𝑹 → 𝑽𝑮𝑺𝟏 + 𝑽𝒐𝒗,𝒄𝒎 , -----𝑽𝑫𝑫 +𝑽𝑻𝟏 > Vdd how ??

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 ICMR, OCMR

Possible input/ output DC levels

R1=R2=10M >> ro2

𝑶𝑪𝑴𝑹 → 𝑽𝑫𝑫 − 𝑽𝑻𝟐, ,−− −|𝑽𝒐𝒗𝟏 |
R1=R2=10k, ac current through R1, R2
𝑶𝑪𝑴𝑹 → 𝑽𝑫𝑫 − 𝑽𝑻𝟐, − 𝒂𝒄 𝑽𝑹𝟐 ,−− −|𝑽𝒐𝒗𝟏 |

I𝑪𝑴𝑹 → 𝑽𝑮𝑺𝟏 , 𝒇𝒊𝒙𝒆𝒅 𝒗𝒂𝒍𝒖𝒆

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Rin, Rout

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CGA-- Rin

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CGA-- Rin

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Source Follower–
Rout

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Resistive load amplifier
Output Voltage swing

Vomax---- Vdd
Vomin---- Vov1

For Vdd=3v, Vgsp = Vgsn =0.9v, Vt=0.7v

Vomax---- 3V
Vomin---- 0.2 V
} 2.8 V

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 BITS Pilani
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Active Load amplifier

Resistive/ Active load CSA

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Active Load amplifier- Q point
load line plot

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CSA/ CGA/ CDA
Max. Gain---- maximize load, R ∞

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Non ideal current source
(active ) load

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Active Load amplifier
Output Voltage swing

Vomax---- Vdd - Vov2

Vomin---- Vov1

For Vdd=3v, Vgsp = Vgsn =0.9v, Vt=0.7v

Vomax---- 0.2v
Vomin---- 2.8v
} 2.6v

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Gain Comparison—
Active/ passive load

𝐴𝑣 = − 𝑔𝑚 𝑟𝑜𝑛 ||𝑟𝑜𝑝
𝐴𝑣 = -500
𝐴𝑣 = − 𝑔𝑚 𝑟𝑜𝑛 ||𝑅𝐷
𝐴𝑣 = -20
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Benefit of Active load
Benefit:
• Less silicon requirement, Less PVT sensitivity
• High impedance leads to high gain
• DC at output is dynamic (adjust on its own)

Drawback:
• Voltage swing reduces
• Transistor count increase
• Power dissipation increases (reference arm added)

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 BITS Pilani
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Different types of Active load

Amplifier
Different Active loads
• Diode connected load

• NMOS/ PMOS lin. enhancement load (triode load) (less R)

• NMOS/ PMOS sat. enhancement load

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 Preferred Active load

• Current mirror load

• Reason--High impedance ro

• Hence, high gain

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Impedance (in ac conditions)
calculation

2𝐼 1 1
𝑔𝑚 = = 1mA/V ||𝑟𝑜 = =1K
𝑉𝑜𝑣 𝑔𝑚 𝑔𝑚
𝑉𝑜𝑣 = 0.2V 𝑟𝑜 = 1𝑀 𝑜ℎ𝑚

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•NMOS/ PMOS sat. enhancement load
Diode connected load
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Active Load Amplifiers

Active load amp,
Gain calculations

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Active Load amplifier

pmos

Small value
Gain depends on device dim
for same I.

Also on µp if load is pmos

Gain improvement technique for
diode connected load—inc. I1

I1/4

But Vgs of M1 will increase

to carry 4I current. Swing reduces Double Gain
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Adv.- diode connected load
amp.
Here, gain depends only on device dim. ---so, linear
amplification, less distortion

For lin. Amp. ----Gain shd. be independent of bias

voltages and current

Reason---
|Av|= gm Rd changes as gm changes with the input
signal swing (though close to Q point)

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Triode load

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Active load CGA

𝒗𝒐𝒖𝒕 𝒓𝒐 𝑹𝑫
≅ 𝒈𝒎 + 𝒈𝒎𝒃
𝒗𝒊𝒏 𝒓𝒐 + 𝑹𝑫

𝒗𝒐𝒖𝒕
≅ 𝒈𝒎 + 𝒈𝒎𝒃 𝒓𝒐 ||𝑹𝑫
𝒗𝒊𝒏 Anu Gupta BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Active load
Source follower

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 BITS Pilani
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Source Follower-
DC Level shifter, impedance matching
Source follower as DC Level
shifter
How much shift?

Vout dc= Vindc-Vgs

Vgs can be adjusted for a

given Ibias by adjusting w/L

Used in push pull amplifier for

shifting dc bias

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 Ex1- DC level shifter
Pmos requires high Vg, Swing requirement
nmos requires low Vg

Vgs for both transistors Level shifter circuit

are not optimized here.

vin

vin
vin
Ex2- level shifter
Charac. of Source follower

• Rin--high
• Rout--low
• Av ≈1
• It reduces Vswing of previous stage
• Non linearity due to gmb

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Vmin at x node of successor

constraint

↓
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Amplifier Gain enhancement

Trade offs
Maximum Gain possible
(intrinsic gain)

• Av = - gm ro
• Make Rd infinite (ideal
current source)

• But this will make

VRd=Vdd, MOS goes to
cutoff

• How?---Rd replaced by
current source
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Gain in active region

Av increases with W/L, VRD, or by dec ID

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Design Parameter affecting
gain
Av increases with W/L, VRD, or by dec ID

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 Trade Offs

W/L increased keeping ID and VRD constant

---greater device capacitance at output , time constant

increases, speed of response is affected
---less overdrive voltage reqd. ( as Id constt.) so vomin
reduces
output swing range increases, bias point will shift
----gain increases

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Bias point for increased (w/L)--- ID and V RD constant

(w/L) 2 large

(w/L) 1 small

vgs 2 vgs 1
small large
 (w/L) 2 > (w/L) 1
Id =
Vdd/Rd
ID and VRD constant

Q1, Q2 vgs1

(w/L)2 large vgs2

Vov2 less

Less lower
swing
(w/L)1 small
Vov1 more
More lower swing

Vdd
vov2 vov1
VdS
less more
VRD increased keeping Id and
W/L constant

Gain increases

Vdd - VRd inc., or Vout max reduces,

output swing range decreases,
MOS shifts towards triode region,
Voltage swing is limited

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Bias point for increased VRD -----
-ID and w/L constant

vgs 1,2

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 (VRD)2 > (VRD)1
Id=
Vdd/Rd Id and W/L constant

(VRD)2 large
Q2
vgs
Q1
Less lower swing

(VRD)1small

More lower swing

vds2 vds1 Vdd

less more VdS
ID dec. keeping VRD and W/L
const.
ID reduces---to keep VRd constant Rd
must increase,
So, Rout shd. be increased
time constant increases,
So, speed of response is affected
 Vgs must dec.

Gain increases
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Bias point for decreased (ID)---
(w/L) and VRD constant

vgs 2 vgs 1
small large

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 VRD and W/L constt. (Id)2 < (Id)1
Id=
Vdd/Rd

Q1
vgs1
(Id) 2 small
vgs2
Vov2 less
Q2
Less swing
((Id)1 large
Vov1 more
More swing

Vdd
vov2 vov1
VdS
less more
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BJT amplifiers
Small-Signal Operation
BJT Hybrid-Pi Model

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When to apply resistance
reflection rule in analysis???
Tips—

• Apply resistance reflection rule when Vx source is applied at

Base terminal

• Apply resistance reflection rule when Vx source is applied at

Emitter terminal

DO NOT APPLY resistance reflection rule when Vx source is

applied at collector terminal

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Examples –1
Vx at base terminal

𝑅𝑠 → 𝛽 + 1 𝑅𝑠

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Examples –2
Vx at emitter terminal

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Examples –3 𝑣𝜋 = −𝑣𝑥
Vx at emitter terminal

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Example 3
Vx at collector terminal

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CEA/ CBA/ CCA

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Small signal model of CEA,
voltage gain

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Small signal model of CEA,
voltage gain

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Small signal model of CEA,
Current gain

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Common Base Amplifier
with dual rail/ single rail supply

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CBA– for correct DC bias
Minimum Vbias/ Maximum VE,min

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CBA–Minimum Vbias for given
input DC of 1 V

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Common Base amplifier

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Open circuit Voltage gain

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CBA
Short circuit Current gain

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CBA
Rin

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CBA
Rin

𝑅𝑖𝑛 =
𝑟𝜋 𝑅𝐶 + 𝑟𝑜
||𝑅𝑆,𝐸 ||
𝛽+1 1 + 𝑔𝑚 𝑟𝑜

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CBA
r
Rout with shunting effect of ᴨ (without Rsig)

𝑹𝒐𝒖𝒕 = 𝑹𝒄 ||𝒓𝒐 ||𝒓𝝅

Anu Gupta BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
CBA
Rout (impact of Rsig - source degeneration))

𝑹𝒐𝒖𝒕 = 𝑹𝒄 || 𝑹𝒔𝒊𝒈 ||𝒓𝝅 + 𝒓𝒐 + 𝒈𝒎 𝒓𝒐 𝑹𝒔𝒊𝒈 ||𝒓𝝅

Anu Gupta BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Emitter Follower

Anu Gupta BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Rin

𝑖𝑒 = 𝑖𝑏 𝛽 + 1

𝑣𝑖𝑛
𝑅𝑖𝑛 =
𝑖𝑖𝑛

𝑅𝑖𝑛 = 𝑟𝜋 + 𝛽 + 1 𝑅𝑠

Anu Gupta BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Rin (with Rsig)

𝑖𝑒 = 𝑖𝑏 𝛽 + 1

𝑣𝑖𝑛
𝑅𝑖𝑛 =
𝑖𝑖𝑛

𝑅𝑖𝑛 = 𝑅𝑠𝑖𝑔 + 𝑟𝜋 + 𝛽 + 1 𝑅𝑠
Anu Gupta BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
 Method-1
𝑅𝑜𝑢𝑡 = 𝑟𝑜 ||𝑟𝑜𝑐 ||𝑅𝑜𝑢𝑡 ′
𝑣𝜋 = 𝑣𝑥 ′ 𝑣𝑥
𝑅𝑜𝑢𝑡 =
𝑖𝑥

𝑣𝑥 1
𝑖𝑥 = 𝑔𝑚 𝑣𝑥 + = 𝑣𝑥 + 𝑔𝑚
𝑟𝜋 𝑟𝜋
𝑣𝑥 ′ 𝑟𝜋 1
= 𝑅𝑜𝑢𝑡 = ≅
𝑖𝑥 1 + 𝑔𝑚 𝑟𝜋 𝑔𝑚

𝟏 𝟏
𝑹𝒐𝒖𝒕 = 𝒓𝒐 ||𝒓𝒐𝒄 || ≅
𝒈𝒎 𝒈𝒎
 Method-2
𝑅𝑜𝑢𝑡 = 𝑟𝑜 ||𝑟𝑜𝑐 ||𝑅𝑜𝑢𝑡 ′
′ 𝑣𝑥
𝑅𝑜𝑢𝑡 =
𝑖𝑒 𝑖𝑥 𝑖𝑥
𝑖𝑏 = =
1+𝛽 1+𝛽
𝑖𝑥 = 𝑖𝑒 = 𝛽𝑖𝑏 + 𝑖𝑏 = 𝑖𝑏 𝛽 + 1

𝑟𝜋 𝑟𝜋 𝑟𝜋
𝑣𝑥 = 𝑖𝑏 𝑟𝜋 = 𝑖𝑒 𝑣𝑥 = 𝑖𝑥 =
1+𝛽 1 + 𝛽 1 + 𝑔𝑚 𝑟𝜋
𝑣𝑥 ′ 𝑟𝜋 1
= 𝑅𝑜𝑢𝑡 = ≅
𝑖𝑥 1 + 𝑔𝑚 𝑟𝜋 𝑔𝑚
𝟏 𝟏
𝑹𝒐𝒖𝒕 = 𝒓𝒐 ||𝒓𝒐𝒄 || ≅
𝒈𝒎 𝒈𝒎
Anu Gupta
Summary---- BJT amplifiers

Anu Gupta BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
 BITS Pilani
Pilani Campus

Voltage gain = Gm* Rout

Gm, Rout

Anu Gupta BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
CSA , Av = Gm Rout

Anu Gupta BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
CSA with Source degeneration
Remove capacitor

Anu Gupta BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Gm----Small signal model

Anu Gupta BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
 gm

• For Rs=0, Gm = gm
• For Rs ≠ 0, Gm < gm
Gm from small signal model without
ro and gmb intuitive analysis

Anu Gupta BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Gm--- Circuit trans-
conductance
−𝑔𝑚
𝐺𝑚 ≅
1 + 𝑔𝑚 + 𝑔𝑚𝑏 𝑅𝑠
−𝑔𝑚
𝐺𝑚 ≅
1 + 𝑔𝑚 𝑅𝑠
Voltage Gain

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Anu Gupta BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Gm decreases --csa/ csa-Rs
Without Rs With Rs

Gm=

Anu Gupta BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
 Trans-conductance variation-
comparison

Gm=

Without Rs With Rs

Anu Gupta, Bits, pilani

Gm decreases. why ?

Because
Input going
to amplifier
reduces

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Rout----Small signal model

Anu Gupta BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Rout’

Anu Gupta BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Voltage gain

Anu Gupta BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Why Rout increases due to Rs?
A high impedance at a node means if voltage at that
node is changed slightly, current through that node
does no change much.

Here we achieve this at Vout node through negative

feedback action in vgs.---

If Vout ↑---Id ↑ (effect comes through ro)

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Anu Gupta BITS Pilani, Pilani Campus

Voltage gain (from ac model)

If ro >> Rs, Rd
• Vout ↑---Id ↑ --- vs ↑--- Vgs ↓--- Id ↓
• (effect comes through (1+λ Vds)

• At the same time, due to Vout ↑ , a voltage vs

vs appears at source

• Vs causes reduction in Vgs, due to which Id

falls more due to square dependence on
Vgs

• Hence Id changes little in comparison to

change in vout

• So Rout increases
Benefit/ drawback

Advantage—
• Non linearity decreases as Id varies less w.r.t
vin variations, Q point is more stable

• Output impedance increases

Drawback--
• Vgs < vin, gain reduces

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Comparison—
CSA/ CSA-Rs

With Rs

Without Rs With Rs

Bits, pilani
Anu Gupta BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Nonlinearity reduction-
Q point stable

Anu Gupta BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
 BITS Pilani
Pilani Campus

Amplifiers with increased voltage/

current gain
Cascode amplifier (high gain)

Cascode Amplifier---

• Modified CSA with cascode load

• CSA-CGA Cascade

Anu Gupta BITS Pilani, Pilani Campus

Cascode amplifier--
Modified CSA

Anu Gupta BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
CASCODE amp with cascode
load

Anu Gupta BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Cacode Amp. ---
CSA-CGA Cascade

Anu Gupta BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Anu Gupta
Resistive Load

Anu Gupta BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Output Voltage swing, Rin,
Rout

Bits, pilani
Anu Gupta BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Cascode amp with current
bias

Anu Gupta BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
BJT CASCODE Amplifier-

Anu Gupta BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Small signal model
BJT--- Effect of rπ on Rout

Anu Gupta BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
BICMOS Cascode amplifier
BJT + MOSFET

Anu Gupta BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Cascode amp with current
bias--- capacitor???

Anu Gupta BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
 BITS Pilani
Pilani Campus

BJT Darlington pair

Super beta BJT
BJT amplifier-
Darlington pair– high current gain

Anu Gupta BITS Pilani, Pilani Campus

If the current gain of a transistor is β1 and β2, the overall current
gain of Darlington pair is β1β2. The current gain of this
transistor is very high compared to the normal transistor.
Therefore, this transistor is also known as “Super Beta
Anu Gupta
Transistor”.
BJT amplifier-
Darlington pair

𝛽 𝛽 + 1 𝐼𝐵 + 𝛽𝐼𝐵 ≅ 𝛽 2 𝐼𝐵

𝛽𝐼𝐵
𝐼𝐵
𝛽 𝛽 + 1 𝐼𝐵

𝛽 + 1 𝐼𝐵

𝛽 + 1 2 𝐼𝐵

Anu Gupta BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
 𝑖𝑐 𝑖𝑐 𝛽2
= 𝑔𝑚,𝑑𝑎𝑟𝑙𝑖𝑛𝑔𝑡𝑜𝑛 = ≅ = β𝑔𝑚
𝑉𝑏𝑒 𝑖𝑏 𝑟𝜋 𝑟𝜋

Increased trans-conductance

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Rout calculations of Darlington
BJT

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Ac model of Darlington pair,
BJT

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

A C model of darlington pair
BJT

2
𝑣𝑏𝑒. 2
𝛽 𝑖𝑏 = 𝛽 = 𝑔𝑚 𝑣𝑏𝑒
𝛽𝑟𝜋

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 𝑖𝑐
𝑔𝑚,𝑑𝑎𝑟𝑙𝑖𝑛𝑔𝑡𝑜𝑛 =
𝑣𝑏𝑒
𝛽2 𝑖𝑏 𝛽𝑖𝑏
= =𝛽 = 𝑔𝑚
𝑣𝑏𝑒,𝑑𝑎𝑟𝑙𝑖𝑛𝑔𝑡𝑜𝑛 𝛽𝑟𝜋 𝑖𝑏

𝑤ℎ𝑒𝑟𝑒; 𝑣𝑏𝑒,𝑑𝑎𝑟𝑙𝑖𝑛𝑔𝑡𝑜𝑛 ≅ 𝑖𝑏 𝛽𝑟𝜋

ℎ𝑒𝑛𝑐𝑒, 𝑔𝑚,𝑑𝑎𝑟𝑙𝑖𝑛𝑔𝑡𝑜𝑛 × 𝑣𝑏𝑒,𝑑𝑎𝑟𝑙𝑖𝑛𝑔𝑡𝑜𝑛 =𝛽 2 𝑖𝑏

CEA with Darlington pair

𝛽1 𝛽2 𝑅𝐶 𝛽2 𝑅𝐶
𝐴𝑉0 ≅ − =−
𝛽1 𝑟𝜋2 𝛽𝑟𝜋2
𝛽𝑅𝐶
𝐴𝑉𝑂 = = −𝑔𝑚2 𝑅𝐶
𝑟𝜋2

Anu Gupta BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
 𝑖𝑜 𝑖𝑜
= 𝐺𝑚 =
𝑉𝑖𝑛 𝑖𝑖𝑛 𝑟𝜋
𝛽
𝐺𝑚 ≅ = 𝑔𝑚,𝑑𝑎𝑟𝑙𝑖𝑛𝑔𝑡𝑜𝑛 = 𝑔𝑚
𝑟𝜋
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
CBA with Darlington pair
self practice

Anu Gupta BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
 BITS Pilani
Pilani Campus

Example—2 stage amplifier

Gain calculation Using different methods
(all should give same result)
Example circuit
(csa+cga) with diode connected load

Anu Gupta BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Method1

Anu Gupta BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Method2

Anu Gupta BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Anu Gupta
Method 3

Anu Gupta
Anu Gupta BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Anu Gupta
 BITS Pilani
Pilani Campus

Multi Stage amplifiers–

increased voltage/ current gain, beyond gmro
2 Stage amplifier-- -- active
load (ro)
• CSA, CSA--- Rin- high, Rout –high, Av– high, in phase
• CGA, CGA--- Rin- low, Rout –high, Av– high, out of phase
• CSA, CGA---Rin- high, Rout –high, Av– low, out of phase
• CGA, CSA---Rin- low, Rout –high, Av– high, out of phase
• CGA, SF--- Rin- low, Rout –low, Av– low, in phase
• CSA, SF---Rin- high, Rout –low, Av– low, out of phase
• SF, CSA-- Rin- high, Rout –high, Av– low, out of phase

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Problem

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 BITS Pilani
Pilani Campus

End