Synopsys Learning Journeys

An easy access guide to your learning

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Table of Contents
Product-based Journeys Role-based Journeys
• PrimeLib • Tweaker
• Custom Compiler • Analog Designer
• PrimePower • VC Formal
• Design Compiler NXT • RF/Transceiver Designer
• PrimeSim • ZeBu
• DSO.ai • Digital Designer
• PrimeTime
• ESP • Physical Designer
• Reference Methodology
• Formality
• RTL Architect
• Fusion Compiler
• SaberRD
• FC/ICC II Hierarchical Design Planning
• Synplify
• Fusion Platform Methodology
• StarRC
• HAPS
• TestMAX Advisor
• IC Compiler II
• TestMAX Access
• IC Validator
• TestMAX FuSa
• Library Compiler
• TestMAX Manager
• Language
• TestMAX SMS
• LynxNXT
• TestMAX XLBIST

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Custom Compiler Learning Path Analog Designer
Course 1 Course 2 Course 3 Course 4 Course 5
Custom Compiler: Custom Compiler: PrimeWave & PrimeSIM Custom Compiler:
PrimeWave Jumpstart
Foundation I Schematic Entry SPICE Analog Tutorial Reliability

Custom Compiler Overview Capturing Schematics Testbench Setup OP, DC, Tran Analysis PrimeSim ResCheck Analysis

Using Advanced Editing PrimeSim EMIR Reliability

Library Manager Parametric Analysis Loop Stability Analysis
features Analysis
In-Design EM Aware Layout
Data I/0 Generating Symbols Corner Analysis Noise Analysis
Implementation
In-Design Capacitance
Technology Schematic Entry Monte Carlo Analysis Transient Analysis
Reporting
In-Design Resistance
Design Review Assistant Advanced Schematic Editing Dynamic Device Checks Transient Noise Analysis Legend
Checking and Reporting
Unified Constraint Partial Layout Extraction
Symbol Creation S-parameter Analysis
Management (needs CC Elite license)
Self-paced
Design Hierarchy SOA Layout Dependent Effects Learning

Transient + Monte Carlo Voltage Dependent Rule

Working with Text Views
Analysis Check
Instructor-Led
Parameterized Connections Training
MOSRA

Schematic Overlays Downloadable

Lab

Using Estimated Parasitic

Cloud-based Lab

#
Duration in Days

1 1
Badge

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Custom Compiler Learning Path RF/Transceiver Designer
Course 6
Custom Compiler : ICC2
CoDesign

Data Preparation

Analog BlackBox Preparation

Digital Implementation

ICC2 Editing

Capacitance Reporting and

Checking Legend

Self-paced
Learning

Instructor-Led
Training

Downloadable
Lab

Cloud-based Lab

#
Duration in Days

1 Badge

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Design Compiler NXT Learning Path
Course 1 Course 2 Course 3 Course 4 Course 5
Design Compiler NXT: Design Compiler NXT : Design Compiler NXT : Design Compiler NXT : Design Compiler NXT:
Jumpstart RTL Synthesis Clock Gating Low Power DFT Insertion SystemVerilog for RTL
Design

Introduction Introduction to DC NXT Introduction Introduction Introduction

Design Setup for Physical

Design Setup Power Analysis Scan Testing and Flows SystemVerilog Features
Synthesis
Accessing Design and Library Implementing User Logic
Reading RTL Design Power Optimization Test Protocol
Object Intent
Constraints: Reg-to-Reg and
Loading Floorplan Data Clock Gating DFT Design Rule Checks Combinational Logic/Latches
I/O Timing

Constraining Design Advanced Schematic Editing Advanced Clock Gating DFT DRC GUI Debug Meaning of full/parallel Legend
Input Transition and Output
Synthesis Techniques Self Gating DRC Fixing Registers
Loading
DC NXT Ultra Synthesis Self-paced
Post Synthesis Outputs Multibit Top-Down Scan Insertion State Machine Learning
Techniques

Timing Analysis ICC II Link Advanced Scan Insertion Wildcard & Tri-state logic
Instructor-Led
Constraints: Multiple Clocks Pack/Unpack Array & Training
Reporting Bottom-up Scan Insertion
and Exceptions Struct/Union
SPG Flow, Congestion,
Export Interface & Package Downloadable
Layout GUI Lab
Constraints: Complex Design
On-Chip Clocking (OCC) Achieving High QoR-Coding
Considerations
Cloud-based Lab

Post-Synthesis Output Data DFTMAX #

Clk Gating/Leakage Duration in Days
Advanced Topics
Power analysis

1/2 3 3 1 Badge

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1/3

Recommended Learning Journey for a Digital Designer

Course 1 Course 2 Course 3 Course 4 Course 5
Library Compiler: Design Compiler NXT: Fusion Compiler: Design Fusion Compiler: Design Fusion Compiler: DFT
Foundation Synthesis Creation & Synthesis Implementation Insertion

Introduction Introduction to DC NXT Introduction & GUI Floorplanning Introduction

Design Setup for Physical Setting up CTS Scan Testing and Flows
Functional Modeling Reading RTL
Synthesis
Accessing Design and Library Objects, Attributes, Running CTS (CCD & Classic
Timing Modeling Test Protocol
Object Application Options Flow)
Constraints: Reg-to-Reg and Routing DFT Design Rule Checks
Low Power Modeling Compile Flows and Setup
I/O Timing

Modeling for Test Advanced Schematic Editing NDM Cell Libraries Routing DRC DFT DRC GUI Debug Legend
Input Transition and Output Via Ladder DRC Fixing
Library Creation Guidelines Loading UPF and Floorplan
Loading
DC NXT Ultra Synthesis Post-route Optimization Top-Down Scan Insertion
Self-paced
CCS Modeling Timing Setup & OCV Learning
Techniques

OCV Modeling Timing Analysis CCD Optimization Signoff Advanced Scan Insertion
Instructor-Led
Constraints: Multiple Clocks Bottom-up Scan Insertion Training
Check Library Power Optimization
and Exceptions
SPG Flow, Congestion, Additional Compile Settings Export Downloadable
Advance Node Features Layout GUI and Techniques Lab

Constraints: Complex Design On-Chip Clocking (OCC)

Library Analytics Considerations
Cloud-based Lab
Physical Library Preparation Post-Synthesis Output Data DFTMAX
& Creation #
Clock Gating/Leakage Duration in Days
Fusion Library Creation Advanced Topics
Power Analysis

2 3 3 Badge

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2/3

Recommended Learning Journey for a Digital Designer

Course 6 Course 7 Course 8 Course 9
Fusion Compiler: SOC IC Validator: User
Prime Time: Foundation StarRC: Foundation
Design Planning (DRC & LVS)

Introduction to STA in Setup ICV and Run DRC/LVS

Initial Design Planning Extraction Fundamentals​
PrimeTime Testcase
STA Concepts and Flow in
IO Planning Gate Level Extraction DRC Error Classification
PrimeTime
From Commit to Abstract Methodology: Qualifying Execute DRC Testcase with
Transistor Level Extraction
Creation Constraints Select Commands
Methodology: Generating
VA and Block Shaping Selective Netlist LVL
Reports

Macro Placement Constraining Multiple Clocks Field Solver​ Legend Text Options Legend
Additional Checks and Generate ICV formatted
PG PPNS Process Modelling​
Constraints netlist
Correlation: POCV and AWP Self-paced Generate Equivalence Self-paced
Pin Placement Metal Fills Learning
Analysis Options Learning

Signoff: Path Based Analysis

Timing and Budgeting (PBA) Debug LVS Errors
Instructor-Led Instructor-Led
Signal Integrity: Crosstalk Training Training
Integration/Assembly Delay Analysis Using Short Finder

Signal Integrity: Crosstalk Downloadable Downloadable

Noise Analysis Lab Lab
Timing Closure: ECO/What If
Analysis
Cloud-based Lab Cloud-based Lab
Large Data: DMSA and
Hyperscale Analysis # #
Duration in Days Duration in Days

3 3 Badge 2 2
Badge

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3/3

Recommended Learning Journey for a Digital Designer

Course 10 Course 11 Course 12
Reference Methodology: Fusion Platform
IC Validator: Runset
Jumpstart Methodology: Jumpstart

Overview Compare Introduction & Overview Introduction & Overview

Language Introduction Benefits of New Language Organization & Structure Organization & Structure

PXL Compare Syntax

Command API Running RM Lab Example
Strategy
Writing a Simple “Flat" Rule Anatomy of Compare
Demo Installation & Setup
Runset Functions
Running a Simple IC Complementary Compare
Validator Runset Functions
FCRM for FPM Users Legend
Advanced Programming
User-defined Functions FAQ – Common Topics
Concepts
IC Validator API Header StarRC Transistor-level Self-paced
Files Extraction Flow Learning

Runset Coding Practices

Instructor-Led
Training
Layout Device Extraction

Benefits of New Language Downloadable

Lab

Runset Structure
Cloud-based Lab
Anatomy of Device Extraction
Functions #
Duration in Days
Property Calculation

User-defined Property
Functions 3 1/2 1/2 Badge

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Custom Compiler Learning Path RF/Transceiver Designer
Course 1 Course 2 Course 3 Course 4 Course 5
Custom Compiler:
Custom Compiler: Custom Compiler: Basic Custom Compiler : Custom Compiler :
Accelerated Layout
Foundation I Layout Design Reliability Automated Layout Design
Design
Schematic Driven Layout
Custom Compiler Overview Layout Design Entry PrimeSim ResCheck Analysis Placement Assistant
(SDL) Initialization
Abutment & Align Functions SDL Placement with PrimeSim EMIR Reliability
Library Manager Pin Placer
Advanced Editing Functions Connectivity Use Analysis
SDL ECO & Cross Object In-Design EM Aware Layout
Data I/0 Hierarchical Design Creation Block Placer
Referencing Implementation

Connectivity Engine Placement Advanced In-Design Capacitance

Technology Router Introduction
Reporting

Abstract Generation In-Design Resistance

Design Review Assistant Symbolic Editor Pattern Router Legend
Checking and Reporting
Unified Constraint Visually Assisted Automation Partial Layout Extraction
Design Rule Aware Editing Interactive Router
Management (needs CC Elite license)
Self-paced
Mcell Guard Ring Template Manager Layout Dependent Effects Auto Router Learning

Advanced Node Support Voltage Dependent Rule

Shielding
Check
Instructor-Led
Multi Pattern Technology Scripting Training

User Defined Devices (UDD) Antenna Rule Support Downloadable

Lab

Physical Verification Technology Enablement

Cloud-based Lab

Parasitic Extraction
#
Duration in Days

1 1
Badge

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DSO.ai Learning Path
Course 1
DSO: Foundation

Introduction

Cold Start

Warm Start

Legend

Self-paced
Learning

Instructor-Led
Training

Downloadable
Lab

Cloud-based Lab

#
Duration in Days

1/2
Badge

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ESP Learning Path
Course 1
ESP: Jumpstart

Introduction

Symbolic Simulations

Functional Accuracy

PIV Introduction

Legend

Self-paced
Learning

Instructor-Led
Training

Downloadable
Lab

Cloud-based Lab

#
Duration in Days

1 Badge

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Formality Learning Path
Course 1 Course 2
Formality: Jumpstart Formality: Foundation

Introduction to Equivalency
Overview
checking

SVF Guidance Concept & Step

Simple Logic Cones & Failing

Design Read
Points
Multi-Stage Verification &
Setup for Verification
SVF

Match and Verify Multi-Voltage Designs & UPF Legend

Debugging Hard Verifications & SVP

Self-paced
Formality Lab Efficient Debugging Learning

RTL & Netlist Interpretation

Instructor-Led
Sequential Design Training
Transforms & SVF
Other Design Transforms & Downloadable
SVF Lab

Conclusion
Cloud-based Lab

#
Duration in Days

1 2 Badge

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Fusion Compiler Learning Path
Course 1 Course 2 Course 3 Course 4 Course 5
Fusion Compiler: Design Fusion Compiler: Design Fusion Compiler: DFT
Fusion Compiler: Jumpstart Fusion Compiler: UPF
Creation & Synthesis Implementation Synthesis

Introduction Introduction & GUI Floorplanning Introduction Introduction to UPF

Design Setup and Reading

Reading RTL Setting up CTS Scan Testing and Flows Power Domains
RTL Design
Objects, Attributes, Running CTS (CCD+classic
NDMs/CLIBS flow) Test Protocol Power Strategies
Application Options

Floorplan and UPF data Compile Flows and Setup Routing DFT Design Rule Checks Supply Network

Compile Flow NDM Cell Libraries Routing DRC DFT DRC GUI Debug Power States Legend

Timing Setup and CCD Loading UPF and Floorplan Via Ladder DRC Fixing Fusion Compiler and UPF

Self-paced
Power Optimization Timing Setup & OCV Post-route Optimization Top-Down Scan Insertion Fusion Compiler Reporting Learning

Top Level Synthesis CCD Optimization Signoff Advanced Scan Insertion

Instructor-Led
Power Optimization Training
Design Implementation Bottom-up Scan Insertion

Additional Compile Settings Downloadable

Export
and Techniques Lab

Hierarchical Synthesis​ On-Chip Clocking (OCC)

Cloud-based Lab

DFTMAX #
Duration in Days
Advanced Topics

1/2 3 Badge

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FC/ICC II Hierarchical Design Planning Learning Path
Course 1
Fusion Compiler: SOC
Design Planning

Initial Design Planning

IO Planning

From Commit to Abstract

Creation

VA and Block Shaping

Macro Placement Legend

PG PPNS

Self-paced
Pin Placement Learning

Timing and Budgeting

Instructor-Led
Training
Integration/Assembly

Downloadable
Lab

Cloud-based Lab

#
Duration in Days

3
Badge

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Fusion Platform Methodology Learning Path
Course 1
Fusion Platform
Methodology: Jumpstart

Introduction & Overview

Organization & Structure

Lab Example

Installation & Setup

FCRM for FPM Users Legend

FAQ – Common Topics

Self-paced
1/2 Learning

Instructor-Led
Training

Downloadable
Lab

Cloud-based Lab

#
Duration in Days

Badge

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HAPS® Hardware Learning Path
Course 1 Course 2
HAPS-80: Hardware and HAPS-100: Hardware and
ProtoCompiler ProtoCompiler

Hardware Overview Hardware Overview

System Clocks System Clocks

HapsTrak3 Connectors HapsTrak3 Connectors

Daughter Board and Cables UMRBus 3.0 Overview

Rack Mounting Solution Daughter Boards and Cables Legend

Confpro HAPS ProtoCompiler Flow

Self-paced
HAPS ProtoCompiler Flow Database Concepts Learning

HAPS ProtoCompiler Flow

Database Concepts
Overview
Instructor-Led
HAPS ProtoCompiler Flow Training
Graphical User Interface
Overview

Graphical User Interface Introduction to Debug Downloadable

Lab

Introduction to Debug
Cloud-based Lab

#
Duration in Days

1/2 1/2
Badge

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IC Compiler II Learning Path
Course 1 Course 2
IC Compiler II: Jumpstart IC Compiler II: Block Level Implementation

Introduction GUI Usage (lab) Signoff

Objects, Attributes,
Design/Timing Setup
Application Options

NDMs/CLIBS Floorplanning

Floorplan Placement

Placement & Optimization NDM Cell Libraries Legend

Clock Tree Synthesis Design Setup

Self-paced
Routing Timing Setup Learning

Top Level Synthesis Setting up CTS

Instructor-Led
Running CTS (CCD+classic Training
Design Implementation
flow)

Routing Downloadable
Lab

Routing DRC
Cloud-based Lab

Via Ladder
#
Duration in Days
Post-route Optimization

1/2
Top Level Implementation 3
Badge

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IC Validator Learning Path
Course 1 Course 2 Course 3
IC Validator: User IC Validator: Runset
IC Validatro: DRC Runset
(DRC & LVS)

Setup ICV and run DRC/LVS Writing a basic "single file"

Overview Compare
testcase runset

DRC Error Classification Language introduction Benefits of new language Writing debug output to
OASIS/GDS Using Layer
Execute DRC testcase with Debugger
Command API PXL compare syntax strategy
select commands Understanding Error
Writing a simple "flat" rule Anatomy of compare Messages & Using
LVL
runset functions Diagnostic Functions
Running a simple IC Validator Complementary compare
Edtext options Options Functions Legend
runset functions
Generate ICV formatted Advanced programming
User-defined functions
netlist concepts
Generate equivalence StarRC transistor-level Self-paced
IC Validator API header files Learning
options extraction flow

Debug LVS errors Runset coding practices

Instructor-Led
Training
Using Short finder Layout device extraction

Using VUE & ICVWB with Downloadable

Benefits of new language
ICV Lab

Runset structure
Cloud-based Lab
Anatomy of device extraction
functions #
Duration in Days
Property calculation

User-defined property
2 functions 3 1
Badge

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Library Compiler Learning Path
Course 1
Library Compiler: Foundation

Introduction Fusion Library Creation​

Functional Modeling

Methodology: Qualifying
Constraints

Timing Modeling​

Modeling for Test​

Library Creation Guidelines

CCS Modeling​

OCV Modeling​

check_library

Electromigration

10 nm Feature

Library Analytics​

Physical Library Preparation​

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1/2

Language Learning Path

Course 1 Course 2 Course 3 Course 4
Language: SVA Formal Language: System Verilog Language: System Verilog
Language: System Verilog for RTL Design
Verification Assertion Testbench

Basic System Verilog Achieving High QoR Through

Introduction to SVA Introduction The Device Under Test
Features Coding
Implementing User Logic System Verilog Verification
Formal Testbench Types of Assertions
Intent (combinatorial logic & Environment
Coding Recommendation – latch) System Verilog Testbench
Action Blocks
Do’s and Don’ts Language Basics - 1
Implementing User Logic
Disabling/Combining/Embedd Intent (meaning of full and System Verilog Testbench
Resources
ing Assertions parallel) Language Basics - 2
Managing Concurrency in
Controlling Assertions Implementing User Logic Legend
System Verilog
Intent (implementing
Sequences and Sequence registers) Object-Oriented
Repetition Programming: Encapsulation
Implementing User Logic Object-Oriented Self-paced
Sequences Operators Intent (implementing state Learning
Programming: Randomization
machines)
Synthesis Assertion Voltage Dependent Rule
Coverage Implementing User Logic Check
Instructor-Led
Intent (wildcard and tri-state Object-Oriented Training
Assertion Libraries logic) Programming: Inheritance
Advanced System Verilog Inter-Thread Communications Downloadable
Features (packed or Lab
unpacked array and struct)
Functional Coverage
Advanced System Verilog Cloud-based Lab
Features (System Verilog System Verilog UVM preview
interface) #
Duration in Days
Advanced System Verilog
Features (System Verilog
package)
1 1 1 3 Badge

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2/2

Language Learning Path

Course 5
Language: System Verilog
Verification using UVM

System Verilog OOP

Inheritance Review

UVM Structural Overview

Modeling Stimulus (UVM

Transactions)
Creating Stimulus Sequences
(UVM Sequence)
Component Configuration
Legend
and Factory

TLM Communications

Self-paced
Scoreboard & Coverage Learning

UVM Callback
Instructor-Led
Advance Training
Sequence/Sequencer
Downloadable
Phasing and Objections Lab

Register Layer Abstraction

(RAL) Cloud-based Lab

Summary #
Duration in Days

3
Badge

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LynxNXT Learning Path
Course 1
LynxNXT:
Foundation

Introduction

Variable Editor

Flow Editor

Execution Monitor

Failure Debug Legend

Exploration

Self-paced
Command Line Interface Learning

Working with FPM

Instructor-Led
Training

Downloadable
Lab

Cloud-based Lab

#
Duration in Days

1 Badge

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PrimeLib Learning Path
Course 1
PrimeLib: Foundation

Tool Introduction

Global Setting to start

characterization
Cell Level Setting to
Configure Arcs
Different Characterization
flow
Creating multiple Connect
Database Legend
Debugging and
Troubleshooting
Complex Cell Self-paced
Characterization Learning

Timing Characterization
Instructor-Led
Constraint Timing Training
Characterization

Power Characterization Downloadable

Lab

Cloud-based Lab

#
Duration in Days

1
Badge

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PrimePower Learning Path
Course 1 Course 2
PrimePower: Jumpstart PrimePower: Foundation

PrimePower – Session Based

Power Analysis Input Introduction
Flow

Power Components Power Analysis Check & Report Power

Leakage Power Power Components Report Switching Activity

Internal Power Leakage Power Summary

Switching Power Internal Power Legend

Inputs & Outputs of Power Switching Power
Analysis
Leakage & Internal Power Self-paced
Simulation Activity Files Data Learning

Input & Outputs of Power

Flow & Report
Analysis
Instructor-Led
PrimePower Analysis Modes Training

Simulation Activity Files Downloadable

Lab

RTL Activity Flow

Cloud-based Lab
Gate-Level Activity Flow
#
PrimePower Analysis Duration in Days
Accuracy
PrimePower Standalone –
1/2 ASCII Flow 1 Badge

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PrimeSim Learning Path
Course 1 Course 2 Course 3 Course 4
PrimeSim: Jumpstart PrimeSim: Foundation PrimeSim: Advance PrimeSim: Advance

PrimeSim Static CCK CCK Advanced ERC and

PrimeSim XA Introduction Interactive Mode
Introduction ESD Checks
PrimeSim CCK Built-In PrimeSim XA Netlist format CCK Propagation Engine –
Distributed Processing
Checks Support XPL and Analog Propagation
PrimeSim CCK Interactive PrimeSim XA Analyses CCK Custom Programmable
Monte-Carlo (MC)
Debugging Commands support Checks
PrimeSim CCK False Error Command/Option Usage &
Custom Check Assertion MOSRA
Pruning Precedence Rules
Custom Compiler – PrimeSim PrimeSim XA Post-Layout GUI : Cross-Probe, Filtering,
Aging and Self-Heating Legend
CCK : Setup and run Simulation Waiver, Grouping, export
PrimeSim XA Command Line
Usage
Self-paced
PrimeSim XA Log File Details Learning

Accuracy and Speed Trade-

off
Instructor-Led
Training
Back-Annotation & XBA

Probing in PrimeSim XA Downloadable

Lab

PrimeSim XA .ALTER Usage

Cloud-based Lab

PrimeSim XA .DATA Usage #

Duration in Days

1/2 2 1 1
Badge

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PrimeTime Learning Path
Course 1 Course 2 Course 3 Course 4
PrimeTime: Jumpstart PrimeTime: Foundation PrimeTime: HyperScale PrimeTime: Scalable STA

Introduction to STA in
Overview Introduction HyperScale Hierarchical Methodologies
PrimeTime
PrimeTime Implementation STA Concepts and Flow in
Flat Context Flow HyperScale
Flow PrimeTime
Methodology: Qualifying
PrimeTime Inputs & Outputs Bottom Up Flow HyperScale Hybrid Flow
Constraints
Methodology: Generating Generating HyperScale Block Distributed & Scenario
Timing Analysis Flow
Reports Models Analysis

Load Design & Check Constraining Multiple Clocks Constraint Consistency HyperGrid Legend
Additional Checks and
Load Library & Check Clock Mapping DMSA
Constraints
Correlation: POCV and AWP Self-paced
Read Parasitic & Check HyperScale Top-Down Flow DVFA/SMVA
Analysis Learning

Signoff: Path Based Analysis

Source Constraints & Check HyperScale-Driven ECO PBA Technologies
(PBA)
Instructor-Led
Signal Integrity: Crosstalk
Constraints Completeness Summary Best Practices Training
Delay Analysis
Signal Integrity: Crosstalk
Coverage Analysis Downloadable
Noise Analysis Lab

Report Timing Closure: ECO/What If

Analysis
Cloud-based Lab
Saving & Exit Large Data: DMSA and
Hyperscale Analysis #
Duration in Days

1/2 3 1 1
Badge

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1/2

Recommend Learning Journey: Physical Designer

Course 1 Course 2 Course 3 Course 4 Course 5
Fusion Compiler: Design Fusion Compiler: Design Fusion Compiler: DFT Fusion Compiler: SOC
Fusion Compiler: Jumpstart
Creation & Synthesis Implementation Synthesis Design Planning

Introduction Introduction & GUI Floorplanning Introduction Initial Design Planning

Design Setup and Reading

Reading RTL Setting up CTS Scan Testing and Flows IO Planning
RTL Design
Objects, Attributes, Running CTS (CCD+classic From Commit to Abstract
NDMs/CLIBS flow) Test Protocol
Application Options Creation

Floorplan and UPF data Compile Flows and Setup Routing DFT Design Rule Checks VA and Block Shaping

Compile Flow NDM Cell Libraries Routing DRC DFT DRC GUI Debug Macro Placement Legend

Timing Setup and CCD Loading UPF and Floorplan Via Ladder DRC Fixing PG PPNS

Self-paced
Power Optimization Timing Setup & OCV Post-route Optimization Top-Down Scan Insertion Pin Placement Learning

Top Level Synthesis CCD Optimization Signoff Advanced Scan Insertion Timing and Budgeting
Instructor-Led
Power Optimization Training
Design Implementation Bottom-up Scan Insertion Integration/Assembly

Additional Compile Settings Downloadable

Export
and Techniques Lab

Hierarchical Synthesis​ On-Chip Clocking (OCC)

Cloud-based Lab

DFTMAX #
Duration in Days
Advanced Topics

1/2 3 3 Badge

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2/2

Recommend Learning Journey: Physical Designer

Course 6 Course 7
Fusion Compiler: UPF Reference Methodology:
Fundamental Jumpstart

Introduction UPF Introduction & Overview

Power Domains Organization & Structure

Power Strategies Running RM

Supply Network Demo

Power States Legend

Fusion Compiler and UPF

Self-paced
Learning

Instructor-Led
Training

Downloadable
Lab

Cloud-based Lab

#
Duration in Days

1/2
Badge

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Reference Methodology Learning Path
Course 1
Reference Methodology:
Jumpstart

Introduction & Overview

Organization & Structure

Running RM

Demo

Legend

Self-paced
Learning

Instructor-Led
Training

Downloadable
Lab

Cloud-based Lab

#
Duration in Days

1/2
Badge

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 RTL Architect Learning Path
Course 1 Course 2
RTL Architect: Using RTL
RTL Architect: Jumpstart
Restructuring

Introduction & Overview RTL Restructuring

RTL Architect Key Features Group

Predictive Engine Ungroup

Unified GUI Reparent

Restructured RTL, SDC,

Physical Floorplaning Legend
UPF, SAIF Generation

Power Analysis Reparenting and Writing RTL

Self-paced
Logic Restructuring Demo Learning

Constraint Management
Instructor-Led
Flows Training

rtl_opt Mega Command Downloadable

Lab

Block-Level Flow/Breakpoints
Cloud-based Lab
Hierarchical Flow/Breakpoints
#
Duration in Days

1 1 Badge

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StarRC Learning Path
Course 1 Course 2
StarRC: Jumpstart StarRC: Foundation

Interconnect Extraction Fundamentals​

Coupling Capacitance Gate level Extraction

Classes of Extractors Transistor Level Extraction

Input for Parasitic Extraction Selective Netlist

StarRC Flow Field Solver​ Legend

SMC Flow Process Modelling​

Self-paced
ITF File Metal Fills
Learning

Instructor-Led
Training

Downloadable
Lab

Cloud-based Lab

#
Duration in Days

1/2 2
Badge

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SaberRD Learning Path
Course 1
SanerRD: Foundation
Training Series

Timing Domain Analysis

Schematic Capture & Parts

Library
Operating Points & Small
Signal Frequency Analysis

Test Automation

Design Optimization Legend

Introduction to Modeling

Self-paced
Import SPICE Models Learning

Modeling with Table Look-Up

Instructor-Led
Modeling with StateAMS Training

Robust Design & Sensitivity Downloadable

Analysis Lab

Monte Carlo & Pareto

Cloud-based Lab

Worst-Case Analysis #
Duration in Days
Fault Analysis

Stress Analysis 3
Badge

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Synplify: Learning Path
Course 1
Synplify: Foundation

Introduction to Synplify Elite

Flow
Creating and Running
Synplify Project

View Log File

HDL Analyst

Handling High Reliability

Designs Legend
Implementing Fault Tolerant
FSMs
Self-paced
ECC RAM Inferring Learning

Importing Quartus IP in
Synplify Projects
Instructor-Led
Training
Debugging with SpyGlass

Debugging with VCS Downloadable

Lab

Identify Instrumentor and

Debugger
Cloud-based Lab

#
Duration in Days

2 Badge

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TestMAX Advisor Learning Path
Course 1
TestMAX: Jumpstart

Early Testability Goals and

Reports

Debug using the GUI

Transition Delay Checks

Random Resistant Fault

Analysis and Test Points

Post stitch DRC Checks Legend

Connectivity Checks

Self-paced
Flow With TestMAX Manager Learning

Instructor-Led
Training

Downloadable
Lab

Cloud-based Lab

#
Duration in Days

1/2
Badge

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TestMAX Access Learning Path
Course 1 Course 2
TestMAX: Jumpstart TestMAX: ATPG

Manufacturing Test and

TestMAX Access structure
ATPG

IEEE 1687 interface to drive Building ATPG Models

internal instruments through
TDR
Running DRC

SIBs Fault Models and Managing

Faults
Define Ring configuration Controlling ATPG Legend
Definition of Server and
Subserver Post ATPG Analysis

AIT Self-paced
Pattern Validation Learning

PDL Pattern Porting At-Speed Testing and

Constraints
Instructor-Led
PDL data packetization Transition Delay Testing
Training

Validation of AIT On-Chip Clocking and Downloadable

Compression Lab

Path Delay Testing

Cloud-based Lab

Power Aware ATPT #

Duration in Days
Conclusion

1 3
Badge

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TestMAX FuSa Learning Path
Course 1
TestMAX FuSa: Jumpstart

Functional Safety for

Automotive Designs

TestMAX FuSa: Introduction

TestMAX FuSa: Static FuSa

Analysis
Running TestMAX FuSa:
Requirement & Constraints
Functional Safety reporting in
TestMAX FuSa Legend

Self-paced
Learning

Instructor-Led
Training

Downloadable
Lab

Cloud-based Lab

#
Duration in Days

1/2
Badge

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TestMAX Manager Learning Path
Course 1
TestMAX Manager:
Jumpstart

Launching and Configuring

tool
Objects, Attributes,
Application Options

NDM Cell Libraries

Timing Setup

Legend

Self-paced
Learning

Instructor-Led
Training

Downloadable
Lab

Cloud-based Lab

#
Duration in Days

1/2
Badge

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 TestMAX SMS Learning Path
Course 1
TestMAX-SMS: Architecture

Introduction

SMS Wrapper

SMS Processor

MMB Processor

SMS Server Legend

Conclusion

Self-paced
Learning

Instructor-Led
Training

Downloadable
Lab

Cloud-based Lab

#
Duration in Days

1 Badge

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TestMAX XLBIST Learning Path
Course 1
TestMAX XLBIST: Jumpstart

Troubleshooting and Debug

LogicBIST basics
hints

XLBIST architecture Intro to AIT

XLBIST and SEQ modes of

operation
IEEE 1500 I/F and internal
resources
XLBIST patterns and interval
definition Legend
Random Resistant Fault
analysis and Test Point
insertion
X propagation analysis and Self-paced
Learning
fixing

OCC and Clock Weights

Instructor-Led
Reset Controller and Reset Training
Weights
Programmable SE Timing Downloadable
Margin Lab

Remap XLBIST Patterns for

Debug and Diagnosis Cloud-based Lab

Validation of XLBIST patterns #

Duration in Days
Porting of XLBIST patterns

Simulation steps for

2
validation Badge

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Tweaker Learning Path
Course 1
Tweaker: ECO

ECO Flow and

Interoperability

Basic ECO Flow

Timing ECO

Useful Skew Clock ECO

Power ECO Legend

Area Recovery

Self-paced
Reliability Recovery Learning

Advanced ECO Features

Instructor-Led
Training
Hierarchy Design Flow

Downloadable
Lab

Cloud-based Lab

#
Duration in Days

3
Badge

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VC Formal Learning Path
Course 1
VC Formal: Foundation

Introduction

Formal Verification
Methodology

SVA for Formal Verification

VC Formal Basic

VC Formal Navigator Legend

Self-paced
Learning

Instructor-Led
Training

Downloadable
Lab

Cloud-based Lab

#
Duration in Days

1
Badge

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Zebu Learning Path
Course 1 Course 2
Zebu: Foundation Zebu: Advanced

Introduction to Emulation Transactors – Guide to

integration + List

ZeBu overview (HW and SW) Low Power emulation

ZeBu Ecosystem Virtual Host and Devices

ZeBu Compile ZeBu Debug

ZeBu Runtime Hybrid Emulation Legend

Tuning ZeBu for High ZeBu Empower – SW based
Performance / TAT / Capacity power analysis
Real world interfaces with Self-paced
Gate Level emulation Learning
speed adaptors

Instructor-Led
Training

Downloadable
Lab

Cloud-based Lab

#
Duration in Days

1 1
Badge

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