Sequential Logic

• Digital state: the D-Register

• Timing constraints for D-Registers
• Specifying registers in Verilog
• Blocking and nonblocking assignments
• Examples

Reminder: Lab #2 due Thursday

6.111 Fall 2017 Lecture 4 1
 Lpset 2 Q1 - Datasheet Specs
• Parts are only guaranteed to meet min/max specs – not typical.
– Lpset 2a: “As a design engineer using good engineering practice,
what would you specify as the maximum data transfer rate to be
published in a “labkit datasheet”? Ans: 150kps

• Typical values acceptable for prototyping, testing

– Lpset 2b: 250kps

6.111 Fall 2008 Lecture 1 2

 Lpset 2 Q1 - Datasheet Specs
• Understand voltage margins between families
– Vcc max32222: 3.3 or 5v; CH340g: 3.3 or 5v

CH340g
• Input/out voltages

max3222

6.111 Fall 2008 Lecture 1 3

 Module Instantiation
Use Explicit Port Declarations

module mux32two
(input [31:0] i0,i1,
input sel,
output [31:0] out);

assign out = sel ? i1 : i0;

endmodule

mux32two adder_mux(.i0(b), .i1(32'd1),

.sel(f[0]), .out(addmux_out));

mux32two adder_mux(b, 32'd1, f[0], addmux_out);

Order of the ports matters!

6.111 Fall 2015

 Top-Level ALU Declaration
• Given submodules: A[31:0] B[31:0]
module mux32two(i0,i1,sel,out); alu
module mux32three(i0,i1,i2,sel,out);
32’d1
module add32(i0,i1,sum); F[0]
0 1
module sub32(i0,i1,diff);
module mul16(i0,i1,prod); F[2:0]
+ - *
• Declaration of the ALU Module:
module alu
00 01 10
(input [31:0] a, b, F[2:1]
input [2:0] f,
output [31:0] r); R[31:0]
wire [31:0] submux_out;
wire [31:0] add_out, sub_out, mul_out; intermediate output nodes

mux32two sub_mux(b, 32'd1, f[0], submux_out);

add32 our_adder(a, addmux_out, add_out);
sub32 our_subtracter(a, submux_out, sub_out);
mul16 our_multiplier(a[15:0], b[15:0], mul_out);
mux32three output_mux(add_out, sub_out, mul_out, f[2:1], r);

endmodule module (unique) corresponding

names instance wires/regs in
names module alu
6.111 Fall 2017 Lecture 3 5
 Verilog Summary
• Verilog – Hardware description language – not software program.

• A convention: lowercase for variables, UPPERCASE for

parameters
module blob
#(parameter WIDTH = 64, // default width: 64 pixels
HEIGHT = 64, // default height: 64 pixels
COLOR = 3'b111) // default color: white
(input [10:0] x,hcount, input [9:0] y,vcount, output reg [2:0] pixel);
endmodule

wire a,b,z; // three 1-bit wires

• wires wire [31:0] memdata; // a 32-bit bus
wire [7:0] b1,b2,b3,b4; // four 8-bit buses
wire [WIDTH-1:0] input; // parameterized bus

6.111 Fall 2017 Lecture 4 6

 Examples

parameter MSB = 7; // defines msb as a constant value 7

parameter E = 25, F = 9; // defines two constant numbers

parameter BYTE_SIZE = 8,
BYTE_MASK = BYTE_SIZE - 1;

parameter [31:0] DEC_CONST = 1’b1; // value converted to 32 bits

parameter NEWCONST = 3’h4; // implied range of [2:0]

parameter NEWCONS = 4; // implied range of at least [31:0]

6.111 Fall 2017 Lecture 4 7

 Something We Can’t Build (Yet)

What if you were given the following design specification:

When the button is pushed:

1) Turn on the light if
it is off
button 2) Turn off the light if light
it is on

The light should change

state within a second
of the button press

What makes this circuit so different

from those we’ve discussed before?

1. “State” – i.e. the circuit has memory

2. The output was changed by a input
“event” (pushing a button) rather
than an input “value”
6.111 Fall 2017 Lecture 4 8
 Digital State
One model of what we’d like to build

Next
State
Memory
Device Current
State Combinational
LOAD
Logic

Input Output

Plan: Build a Sequential Circuit with stored digital STATE –

• Memory stores CURRENT state, produced at output
• Combinational Logic computes
• NEXT state (from input, current state) When Output depends on input
and current state, circuit is
• OUTPUT bit (from input, current state) called a Mealy machine. If
Output depends only on the
• State changes on LOAD control input current state, circuit is called
a Moore machine.
6.111 Fall 2017 Lecture 4 9
 Our next building block: the D register

The edge-triggered D register: on

the rising edge of CLK, the value of
D is saved in the register and then
shortly afterwards appears on Q.

D
CLK

6.111 Fall 2017 Lecture 4 10

 D-Register Timing - I
≤tPD

≥tCD

CLK

D
≥tSETUP ≥tHOLD
tPD: maximum propagation delay, CLK →Q
tCD: minimum contamination delay, CLK →Q
tSETUP: setup time
How long D must be stable before the rising edge of CLK

tHOLD: hold time

How long D must be stable after the rising edge of CLK

6.111 Fall 2017 Lecture 4 11

 D-Register Internals – 74LS74
≤tPD

≥tCD

CLK

D
≥tSETUP ≥tHOLD

CLK
tSETUP = 20ns tPD-HL = 40ns

tHOLD = 5ns tPD-LH = 25ns

6.111 Fall 2017 Lecture 4 12

 D-Register Timing - II
D Q logic D Q
reg1 reg2

CLK
tCLK

tPD,reg1
CLK
tPD,logic

tCD,reg1

tCD,logic ≥ tSETUP,reg2 The good news: you can

choose tCLK so that this
constraint is satisfied!
tPD,reg1 + tPD,logic + tSETUP,reg2 ≤ tCLK
The bad news: you have to change
tCD,reg1 + tCD,logic ≥ tHOLD,reg2 your design if this constraint isn’t
met.
6.111 Fall 2017 Lecture 4 13
 Single-clock Synchronous Circuits

We’ll use Registers in a highly constrained way to build digital

systems:
Does that
symbol
register?
Single-clock Synchronous Discipline
• No combinational cycles
• Single clock signal shared among
all clocked devices (one clock
domain)
• Only care about value of
combinational circuits just before
rising edge of clock

• Clock period greater than every

combinational delay
• Change saved state after noise-
inducing logic transitions have
stopped!
6.111 Fall 2017 Lecture 4 14
 Clocks are Not Perfect: Clock Skew
CLout

In
D Q Combinational D Q
Logic

Wire  delay   clk2

clk1  
clk1  

clk2  

δ>0  

tskew    =   tclk2  –  tclk1  

6.111 Fall 2017 Lecture 4 15

 Positive and Negative Skew
TCLK +
R1 R2 R3
In Combinational Combinational TCLK
D Q D Q D Q • • • CLK1 1 3
Logic Logic

CLK tCLK1 tCLK2 tCLK3

CLK2 2 4
delay delay
R1 R2 R3 + th
In Combinational
(a) Positive skew Combinational
D Q D Q D Q •••
Logic Logic
R1 t R2 R3
In CLK Launching edge arrives
D Q
t
CLK1Combinational
D Q
Logic
before
Combinational
Logic
the
D receiving
Q
tCLK2
edge CLK3
•••
delay delay
tCLK1 tCLK2
(a) Positive skew tCLK3

delay delay CLK

R1 R2 R3
In (b) Negative skew
Combinational Combinational TCLK +
D Q D Q D Q •••
Logic Logic 1
TCLK
3
CLK1
tCLK1 tCLK2 tCLK3

delay delay CLK CLK2 2 4

(b) Negative skew

Receiving edge arrives before the launching edge

ØAdapted from J. Rabaey, A. Chandrakasan, B. Nikolic,

“Digital Integrated Circuits: A Design Perspective” Copyright 2003 Prentice Hall/Pearson.

6.111 Fall 2017 Lecture 4 16

 D-Register Timing With Skew
In the real world the clock signal arrives
at different registers at different times.
D Q logic D Q
reg1 reg2
The difference in arrival times (pos or
neg) is called the clock skew tskew.
tskew = tRn,clk2 – tRn,clk1
CLK ±skew
We can update our two timing constraints
to reflect the worst-case skew
CLKreg1
tPD,reg1+ tPD,logic Setup time: tRn,clk = tRn+1,clk
tRn,clk1+tPD,reg1+tPD,logic +tSETUP,reg2 ≤ tRn+1,clk2
tPD,reg1+tPD,logic+ tSETUP,reg2 ≤ tCLK + tskew
tCD,reg1+tCD,logic
Hold time:
≥ tSETUP,reg2 tRn,clk1+tCD,reg1+tCD,logic ≥ tRn,clk2+tHOLD,reg2
tCD,reg1+tCD,logic ≥ tHOLD,reg2+ tskew
CLKreg2
Thus clock skew increases the minimum
≥ tHOLD,reg2 cycle time of our design and makes it
harder to meet register hold times.
CLKreg2 rising edge might fall
anywhere in this region. Which skew is tougher to deal with (pos or neg)?
6.111 Fall 2017 Lecture 4 17
 Delay Estimation : Simple RC Networks
VDD

Vin Vout

CL

V DD V DD

Ron (a) Low-to-high (b) High-to-low

review R
vout

V out V out
vin C
CL
CL
Ron

tp = ln (2) τ = 0.69 RC
6.111 Fall 2017 Lecture 4 18
 RC Equation

Vs = 5 V
Vs = 5 V
Switch is closed t<0
R
Switch opens t>0
Vs = VR + VC
+
Vc Vs = iR R+ Vc iR = C dVc
- dt
dV
Vs = RC c + Vc
dt
t
⎛ − ⎞
t
Vc = Vs ⎜⎜1 − e ⎟⎟
RC
⎛ − ⎞ ⎝ ⎠
Vc = 5⎜⎜1 − e ⎟⎟
RC

⎝ ⎠

6.111 Fall 2017 Lecture 4 19

 Clocks are Not Perfect: Clock Jitter

tpd, tsu, thold

Typical crystal oscillator

tclk – 2tjitter > tpd + tsu + tlogic 100mhz (10ns)
Jitter: 1ps

6.111 Fall 2017 Lecture 4 20

 Sequential Circuit Timing

New
tCD,R = 1ns State
tPD,R = 3ns
tS,R = 2ns Current
tH,R = 2ns Combinational
State
Logic
Clock tCD,L = ?
tPD,L = 5ns
Input Output

Questions:
• Constraints on tCD for the logic? > 1 ns

• Minimum clock period? > 10 ns (tPD,R+tPD,L+ tSETUP,R)

• Setup, Hold times for Inputs? tSETUP,Input = tPD,L +tSETUP,R
tHOLD,Input = tHOLD,R -tCD,L

This is a simple Finite State Machine … more on next time!

6.111 Fall 2017 Lecture 4 21
 The Sequential always Block
Edge-triggered circuits are described using a sequential always
block

Combinational Sequential

module comb(input a, b, sel, module seq(input a, b, sel, clk,

output reg out); output reg out);
always @(*) begin always @(posedge clk) begin
if (sel) out = b; if (sel) out <= b;
else out = a; else out <= a;
end end
endmodule endmodule

6.111 Fall 2017 Lecture 4 22

 Importance of the Sensitivity List
• The use of posedge and negedge makes an always block
sequential (edge-triggered)
• Unlike a combinational always block, the sensitivity list does
determine behavior for synthesis!
D-Register with synchronous clear D-Register with asynchronous clear
module dff_sync_clear( module dff_sync_clear(
input d, clearb, clock, input d, clearb, clock,
output reg q output reg q
); );
always @(posedge clock) always @(negedge clearb or posedge clock)
begin begin
if (!clearb) q <= 1'b0; if (!clearb) q <= 1'b0;
else q <= d; else q <= d;
end end
endmodule endmodule

always block entered immediately when

always block entered only at
each positive clock edge (active-low) clearb is asserted

Note: The following is incorrect syntax: always @(clear or negedge clock)

If one signal in the sensitivity list uses posedge/negedge, then all signals must.

§ Assign any signal or variable from only one always block. Be wary of
race conditions: always blocks with same trigger execute concurrently…
6.111 Fall 2017 Lecture 4 23
 Blocking vs. Nonblocking Assignments
• Verilog supports two types of assignments within always blocks,
with subtly different behaviors.
• Blocking assignment (=): evaluation and assignment are immediate
always @(*) begin
x = a | b; // 1. evaluate a|b, assign result to x
y = a ^ b ^ c; // 2. evaluate a^b^c, assign result to y
z = b & ~c; // 3. evaluate b&(~c), assign result to z
end

Nonblocking assignment (<=): all assignments deferred to end of

simulation time step after all right-hand sides have been
evaluated (even those in other active always blocks)
always @(*) begin
x <= a | b; // 1. evaluate a|b, but defer assignment to x
y <= a ^ b ^ c; // 2. evaluate a^b^c, but defer assignment to y
z <= b & ~c; // 3. evaluate b&(~c), but defer assignment to z
// 4. end of time step: assign new values to x, y and z
end

Sometimes, as above, both produce the same result. Sometimes, not!

6.111 Fall 2017 Lecture 4 24
 Blocking vs. Nonblocking Assignments
• Guaranteed question on job interviews with Verilog questions.

• Blocking assignment (=): evaluation and assignment are immediate;

subsequent statements affected.

• Nonblocking assignment (<=): all assignments deferred to end of

simulation time step after all right-hand sides have been
evaluated (even those in other active always blocks)

Sometimes, as above, both produce the same result. Sometimes,

not!

6.111 Fall 2017 Lecture 4 25

 Assignment Styles for Sequential Logic

What we want:
Register Based
Digital Delay Line

Will nonblocking and blocking assignments both produce the

desired result? (“old” means value before clock edge, “new” means
the value after most recent assignment)

module nonblocking( module blocking(

input in, clk, input in, clk,
output reg out output reg out
); );
reg q1, q2; reg q1, q2;
always @(posedge clk) begin always @(posedge clk) begin
q1 <= in; q1 = in;
q2 <= q1; // uses old q1 q2 = q1; // uses new q1
out <= q2; // uses old q2 out = q2; // uses new q2
end end

endmodule endmodule
6.111 Fall 2017 Lecture 4 26
 Use Nonblocking for Sequential Logic
always @(posedge clk) begin always @(posedge clk) begin
q1 <= in; q1 = in;
q2 <= q1; // uses old q1 q2 = q1; // uses new q1
out <= q2; // uses old q2 out = q2; // uses new q2
end end

“At each rising clock edge, q1, q2, “At each rising clock edge, q1 = in.
and out simultaneously receive the After that, q2 = q1.
old values of in, q1, and q2.” After that, out = q2.
Therefore out = in.”

• Blocking assignments do not reflect the intrinsic behavior of multi-

stage sequential logic
• Guideline: use nonblocking assignments for sequential always blocks

6.111 Fall 2017 Lecture 4 27

 always block
• Sequential always block: always @(posedge clock) use <=
• Combinatorial always block: always @ * use =
• Results of operators (LHS) inside always block (sequential and
combinatorial) must be declared as “reg”

• Equivalent Verilog

reg z ç same as è
always @ * example of assign z = x && y
z = x && y combinatorial // z not a “reg”
always block

• case statements must be used within an always block; include

default case

6.111 Fall 2017 Lecture 4 28

 Sequential always block style
// There are two styles for creating this sample divider. The
// first uses sequential always block for state assignment and
// a combinational always block for next-state. This style tends
// to result in fewer errors.
//
// An alternate approach is to use a single always block. An example
// of a divide by 5 counter will illustrate the differences

////////////////////////////////// /////////////////////////////////
// Sequential always block with a // Single always block
// combinational always block //

reg [3:0] count1, next_count1; reg [3:0] count2;

always @(posedge clk) always @(posedge clk) begin

count1 <= next_count1; if (reset) count2 <= 0;
else count2 <=
always @* begin (count2 == 4) ? 0 : count2 + 1;
if (reset) next_count1 = 0; end
else next_count1 =
(count1 == 4) ? 0 : count1 + 1; assign enable2 = (count2 == 4);
end

assign enable1 = (count1 == 4);

////////////////////////////////// //////////////////////////////////

6.111 Fall 2017 Lecture 4 29

 Coding Guidelines
The following helpful guidelines are from the Cummings paper. If
followed, they ensure your simulation results will match what they
synthesized hardware will do:

1. When modeling sequential logic, use nonblocking assignments.

2. When modeling latches, use nonblocking assignments.
3. When modeling combinational logic with an always block, use blocking
assignments.
4. When modeling both sequential and “combinational” logic within the
same always block, use nonblocking assignments.
5. Do not mix blocking and nonblocking assignments in the same always
block.
6. Do not make assignments to the same variable from more than one
always block.
7. Use $strobe to display values that have been assigned using
nonblocking assignments.
8. Do not make assignments using #0 delays.
For more info see: http://www.sunburst-design.com/papers/CummingsSNUG2002Boston_NBAwithDelays.pdf

#1 thing we will be checking in your Verilog submissions!

6.111 Fall 2017 Lecture 4 30
 Guideline 4: Sequential and “combinatorial” logic
in the same always block

module nbex1 module nbex2

(output reg q, (output q,
input clk, rst_n, input clk, rst_n,
input a, b); input a, b);
reg y; reg q;
always @(a or b) always @(posedge clk or
Combinatorial
y = a ^ b; negedge rst_n)
logic
if (!rst_n) q <= 1'b0;
always @(posedge clk or else q <= a ^ b;
negedge rst_n)
if (!rst_n) q <= 1'b0; endmodule
else q <= y;
Combinatorial logic
endmodule

6.111 Fall 2008 Lecture 4 31

 = vs. <= inside always

always @(posedge clk) begin

A a = b; // blocking assignment
module main; b = a; // execute sequentially
reg a,b,clk; end

always @(posedge clk) begin

B a <= b; // non-blocking assignment
b <= a; // eval all RHSs first
end

always @(posedge clk) a = b;

C always @(posedge clk) b = a;

initial begin
clk = 0; a = 0; b = 1; always @(posedge clk) a <= b;
D always @(posedge clk) b <= a;
#10 clk = 1;
#10 $display("a=%d b=%d\n",a,b);
$finish; always @(posedge clk) begin
end E a <= b;
endmodule b = a; // urk! Be consistent!
end

Rule: always change state using <= (e.g., inside always @(posedge clk)…)
6.111 Fall 2017 Lecture 4 32
 Implementation for on/off button
button

light

module onoff(input button, output reg light);

always @(posedge button) light <= ~light;
endmodule

6.111 Fall 2017 Lecture 4 33

 Synchronous on/off button
When designing a system that accepts many inputs it would be hard
to have input changes serve as the system clock (which input would
we use?). So we’ll use a single clock of some fixed frequency and
have the inputs control what state changes happen on rising clock
edges.

For most of our lab designs we’ll use a 27MHz system clock (37ns
clock period).

module onoff_sync(input clk, button,

output reg light);
always @ (posedge clk) begin
if (button) light <= ~light;
end
endmodule

6.111 Fall 2017 Lecture 4 34

 Resetting to a known state
Usually one can’t rely on registers powering-on to a particular initial
state*. So most designs have a RESET signal that when asserted
initializes all the state to known, mutually consistent initial values.

module onoff_sync(input clk, reset, button,

output reg light);
always @ (posedge clk) begin
if (reset) light <= 0;
else if (button) light <= ~light;
end
endmodule

* Actually, our FPGAs will reset all registers to 0 when the device is
programmed. But it’s nice to be able to press a reset button to return to a
known state rather than starting from scratch by reprogramming the
device.

6.111 Fall 2017 Lecture 4 35

 Clocks are fast, we’re slow!
The circuit on the last slide toggles the light on every rising clock
edge for which button is 1. But clocks are fast (27MHz!) and our
fingers are slow, so how do we press the button for just one clock
edge? Answer: we can’t, but we can add some state that remembers
what button was last clock cycle and then detect the clock cycles
when button changes from 0 to 1.

module onoff_sync(input clk, reset, button,

output reg light);
reg old_button; // state of button last clk
always @ (posedge clk) begin
if (reset)
begin light <= 0; old_button <= 0; end
else if (old_button==0 && button==1)
// button changed from 0 to 1
light <= ~light;
old_button <= button;
end
endmodule
6.111 Fall 2017 Lecture 4 36
 Asynchronous Inputs in Sequential Systems
What about external signals?
Can’t guarantee
Sequential System setup and hold
times will be met!
Clock

When an asynchronous signal causes a setup/hold

violation...
I II III
Q ?

D
Clock
Transition is missed Transition is caught Output is metastable
on first clock cycle, on first clock cycle. for an indeterminate
but caught on next amount of time.
clock cycle.
Q: Which cases are problematic?
6.111 Fall 2017 Lecture 4 37
 Asynchronous Inputs in Sequential Systems

All of them can be, if more than one happens simultaneously

within the same circuit.
Guideline: ensure that external signals directly feed
exactly one flip-flop
Clocked
Synchronous
System
Async Q0
D Q
Sequential System Input

D Q Clock

Q1
D Q

Clock Clock

This prevents the possibility of I and II occurring in different places in

the circuit, but what about metastability?

6.111 Fall 2017 Lecture 4 38

 Handling Metastability
• Preventing metastability turns out to be an impossible problem
• High gain of digital devices makes it likely that metastable conditions will
resolve themselves quickly
• Solution to metastability: allow time for signals to stabilize

Can be Very unlikely to Extremely unlikely

metastable be metastable for to be metastable for
right after >1 clock cycle >2 clock cycles
sampling

Complicated
D Q D Q D Q Sequential Logic
System

Clock

How many registers are necessary?

• Depends on many design parameters (clock speed, device speeds, …)
• In 6.111, a pair of synchronization registers is sufficient

6.111 Fall 2017 Lecture 4 39

 One last little problem…
Mechanical buttons exhibit contact // Switch Debounce Module
// use your system clock for the clock input
“bounce” when they change position, // to produce a synchronous, debounced output
leading to multiple output transitions // DELAY = .01 sec with a 27Mhz clock
module debounce #(parameter DELAY=270000-1)
before finally stabilizing in the new (input reset, clock, bouncey,
position: output reg steady);

reg [18:0] count;

We need a reg old;
debouncing always @(posedge clock)
circuit!

endmodule

6.111 Fall 2017 Lecture 4 40

 One last little problem…
Mechanical buttons exhibit contact // Switch Debounce Module
// use your system clock for the clock input
“bounce” when they change position, // to produce a synchronous, debounced output
leading to multiple output transitions // DELAY = .01 sec with a 27Mhz clock
module debounce #(parameter DELAY=270000-1)
before finally stabilizing in the new (input reset, clock, bouncey,
position: output reg steady);

reg [18:0] count;

We need a reg old;
debouncing always @(posedge clock)
circuit! if (reset) // return to known state
begin
count <= 0;
old <= bouncey;
steady <= bouncey;
end
else if (bouncey != old) // input changed
begin
old <= bouncey;
count <= 0;
end
else if (count == DELAY) // stable!
steady <= old;
else // waiting…
count <= count+1;

endmodule

6.111 Fall 2017 Lecture 4 41

 On/off button: final answer
module onoff_sync(input clk, reset, button_in,
output reg light);
// synchronizer
reg button,btemp;
always @(posedge clk)
{button,btemp} <= {btemp,button_in};

// debounce push button

wire bpressed;
debounce db1(.clock(clk),.reset(reset),
.bouncey(button),.steady(bpressed));

reg old_bpressed; // state last clk cycle

always @ (posedge clk) begin
if (reset)
begin light <= 0; old_bpressed <= 0; end
else if (old_bpressed==0 && bpressed==1)
// button changed from 0 to 1
light <= ~light;
old_bpressed <= bpressed;
end
endmodule

6.111 Fall 2017 Lecture 4 42

 Example: A Simple Counter
Isn’ t this a lot like
Exercise 1 in Lab 2?
0 1 4 4
+1 1 count
0
0

clr
enb clk

// 4-bit counter with enable and synchronous clear

module counter(input clk,enb,clr,
output reg [3:0] count);
always @(posedge clk) begin
count <= clr ? 4’b0 : (enb ? count+1 : count);
end
endmodule

6.111 Fall 2017 Lecture 4 43