Minor Project 1 – Washing Machine Controller FSM Design
Hardware Description Language Lab
Date of Assignment: 27/03/2023 Submission Deadline: 07/04/2023
Suppose you are a design engineer in “Smart Home” design company which design
all sorts of electronic appliances for modern smart homes. One such important day-
to-day use appliance is a washing machine. You have to design a washing machine
controller for a new customer. The functionality that the customer want is described
in spoken language in words is as follows:
The machine shall start when the user deposits a coin. The machine then goes
through following four wash cycles: soak, wash, rinse, and spin. Further there is an
“Additional wash” optional switch which if pressed, the machine shall go through a
second ‘wash’ and ‘rinse’ cycle. To control the time of each cycle there shall be a
timer. It can be assumed that every wash cycle takes equal amount of time. The timer
start counting when the coin is deposited. And it counts up to time ‘T’ which is equal
to the time period of a wash cycle. After time ‘T’ it resets itself and starts again. The
timer is used to cycle the machine through different wash cycles. Further, if the lid of
the machine is raised during the spin cycle the timer suspends itself and remain
paused until the lid is closed. During this time the machine stops spinning. Once the
lid is closed the timer again starts and make the machine spin again. You have to do
the following things:
1. Identify your I/Ps and O/Ps clearly. List all of your reasonable assumptions
give brief description of each. Draw the Block diagram.
2. Choose the last three digits of your roll number as number of seconds required
by the machine to execute all the four wash cycles. Further, assume that the
machine controller has to operate at a frequency of 1GHz.
3. Draw the state diagram and make the truth table.
4. Use any of the state minimization algorithms to minimizes the states.
5. Use an appropriate state encoding scheme.
6. Finally derive the expressions for state transition and output functions.
Instructions for report submission:
1. You can discuss the solution with your classmates but you should use your
own solution. Do not copy the assignment report. Plagiarism of any kind will
result in ‘Fail’ grade. There will be a viva based on your report as an
evaluation component of the project.
2. You have to make the report on plain A4 sheets. The deadline for submission
of the project report is April, 7th 2023 (submit to the TA during the lab
session). No extension will be allowed.
3. Zip all the VHDL/Verilog design files in a single zip file and name it as your-
roll-number_MinorProject_1 and send it to the TA Mr. Gaurav Kumar on his
mail ID (
[email protected]).
4. In case you ha ve a ny do ub t please reach out to me or the TA over E-
mail or phone.
