THE CPU
Stores Intermediate e data during execution of
instruction
Performs the required micro-operations for executing
the instructions
Supervises the transfer of info among the registers and
instructs the ALU as to which operation to perform
CPU FUNCTIONS
CPU functions depend on computers instruction set.
Computer Architecture = Computer Structure and
Behavior as seen by the low level programmer
o Instruction formats
o Addressing modes
o The instruction set
o The general organization of CPU
The instruction set provides the specifications for the CPU design and this know how is essential
to be able to program efficiently.
Components
Arithmetic logic unit (ALU) Performs mathematical and logical operations
Control unit Decodes the program instruction in the IR, selecting machine
(CU) resources, such as a data source register and a particular arithmetic
operation, and coordinates activation of those resources.
Control and Status Registers
Program Counter An incrementing counter that keeps track of the memory address of
(PC) the instruction that is to be executed next or in other words, holds the
address of the instruction to be executed next.
Instruction Register A temporary holding ground for the instruction that has just been
(IR) fetched from memory.
Memory Address holds the address of a memory location that is to be read or write
Register (MAR)
Memory Buffer Register A two-way register that holds data fetched from memory (and ready
(MBR) for the CPU to process) or data waiting to be stored in memory.
Program Status Word Condition Code Flags + other bits defining the status of the CPU
(PSW) (interrupt enabled/disabled, supervisor, etc.)
User Visible Registers
General-Purpose Some architecture provides a set of registers which can be used
Registers without restrictions as operands for any opcode and as address
registers
CPU ORGANIZATIONS
Operations are performed on data stored in memory or processor registers.
The operands are thus specified by their memory addresses or register address.
The number of address fields in the instruction format depends on the internal organization of
CPU
In general, most processors are organized in one of 3 ways
o Single Register (Accumulator) Organization
o General register organization
o Stack organization
Single Register (Accumulator) Organization
Accumulator is the only general purpose register
Instructions use Zero or One address field.
Advantages
Accumulator content is meant to be an operand. No requirement for the operand address for
one operand. This results in Short instructions and less memory space.
Instruction cycle takes less time as it saves time in instruction fetching due to absence of
operand fetch.
Disadvantages
Program size increases due to usage of many instructions in complex expressions. Total memory
size increases.
Program execution time increases due to increase in no. of instructions per Program.
General register organization
Used by most modern computer processors
Any of the registers can be used as the source or destination for computer operations
Instructions use 2 or 3 addresses.
Advantages
Shorter programs than Accumulator Based CPUs
In Accumulator based CPU, a memory location is required for storing partial results. This
additional memory access is avoided here.
Increase in no. of registers increases CPU efficiency
Disadvantages
Cost of hardware increases with no. of GPRs.
Stack organization
All operations are done using the hardware stack
PUSH and POP instructions which require an address field.
Other instructions don’t need address fields as the operands are implied to be in the stack.
For example, an OR instruction will pop the two top elements from the stack, do a logical OR on
them, and push the result on the stack
Advantages
Easy programming
High compiler efficiency
Highly suited for block structured languages
Instructions don’t have address field – short instructions.
Disadvantages
Additional h/w circuitry needed for stack implementation.
Increased program size.
SOME TRADE OFFS
A large number of general purpose registers means large number of bits for encoding register
operands; specialization of registers reduces this need.
Too small number of registers creates problems to the programmer and leads to an increased
memory traffic.
The number of general-purpose or data registers is often between 8 - 32.
RISC processors often have a very large number of registers (~ 100).
EXAMPLE
(A+B)-(C+D)
Accumulator Based CPU Register Based CPU Stack Based CPU
LOAD A LOAD R1, A PUSH A
ADD B ADD R1, B PUSH B
STORE T LOAD R2, C ADD
LOAD C ADD R2, D PUSH C
ADD D SUB R1, R2 PUSH D
STORE U STORE X,R1 ADD
LOAD T SUB
SUB U POP X
STORE X
INSTRUCTION FORMAT
Instruction Fields
o OP-code field : Specifies the operation to be performed Group of bits
that define various processor operations.
o Address field : designates memory address(es) or a processor
register(s)
o Mode field : Determines how the address field is to be interpreted
(to get effective address or the operand)
Instruction Cycle
An instruction cycle (sometimes called a fetch–decode–execute cycle) is the basic operational process of
a computer. It is the process by which a computer retrieves a program instruction from its memory,
determines what actions the instruction dictates, and carries out those actions. This cycle is repeated
continuously by a computer's central processing unit (CPU), from boot-up to when the computer is shut
down. Instruction Cycle has mainly 4 phases that are Fetch Phase, Decode Phase, Decision Phase and
Execution Phase.
Initiating the cycle
The cycle begins as soon as power is applied to the system, with an initial PC value that is predefined by
the system's architecture (for instance, in Intel IA-32 CPUs, the predefined PC value is 0xfffffff0).
Typically this address points to a set of instructions in read-only memory (ROM), which begins the
process of loading (or booting) the operating system.
Flowchart of Instruction Cycle
Fetching the instruction
Step 1 of the Instruction Cycle is called the Fetch Cycle. This step is the same for each instruction:
The CPU sends PC to the MAR and sends a READ command on the control bus
In response to the read command (with address equal to PC), the memory returns the data
stored at the memory location indicated by PC on the databus
The CPU copies the data from the data bus into its MDR (also known as MBR, see section
Components above)
A fraction of a second later, the CPU copies the data from the MDR to the Instruction Register
(IR)
The PC is incremented so that it points to the following instruction in memory. This step
prepares the CPU for the next cycle.
The Control Unit fetches the instruction's address from the Memory Unit.
Decoding the instruction
Step 2 of the instruction Cycle is called the Decode Cycle. The decoding process allows the CPU to
determine what instruction is to be performed, so that the CPU can tell how many operands it needs to
fetch in order to perform the instruction. The opcode fetched from the memory is decoded for the next
steps and moved to the appropriate registers. The decoding is done by the CPU's Control Unit.
Reading the effective address
Step 3 is evaluating which operation it is. If this is a Memory operation - in this step the computer checks
if it's a direct or indirect memory operation:
Direct memory instruction - Nothing is being done.
Indirect memory instruction - The effective address is being read from the memory.
If this is an I/O or Register instruction - the computer checks its kind and executes the instruction.
Executing the instruction
Step 4 of the Instruction Cycle is the Execute Cycle. Here, the function of the instruction is performed. If
the instruction involves arithmetic or logic, the Arithmetic Logic Unit is utilized. This is the only stage of
the instruction cycle that is useful from the perspective of the end user. Everything else is overhead
required to make the execute phase happen.
Three-Address Instructions (Opcode, Destination and Source)
Program to evaluate X = (A + B) * (C + D)
ADD R1, A, B (R1 M[A] + M[B] )
ADD R2, C, D (R2 M[C] + M[D] )
MUL X, R1, R2 (M[X] R1 * R2 )
Results in short programs
Instruction becomes long (many bits)
Two-Address Instructions
Program to evaluate X = (A + B) * (C + D)
MOV R1, A (R1 M[A])
ADD R1, B (R1 R1 + M[B])
MOV R2, C (R2 M[C])
ADD R2, D (R2 R2 + M[D])
MUL R1, R2 (R1 R1 * R2)
MOV X, R1 (M[X] R1)
One-Address Instructions
Use an implied AC register for all data manipulation
Program to evaluate X = (A + B) * (C + D)
LOAD A (AC M[A])
ADD B (AC AC + M[B])
STORE T (M[T] AC)
LOAD C (AC M[C])
ADD D (AC AC + M[D])
MUL T (AC AC * M[T])
STORE X (M[X] AC)
Zero-Address Instructions
Can be found in a stack-organized computer
Program to evaluate X = (A + B) * (C + D)
PUSH A ( TOS A)
PUSH B ( TOS B)
ADD (TOS (A + B))
PUSH C ( TOS C)
PUSH D (TOS D)
ADD (TOS (C + D))
MUL (TOS (C + D) * (A + B))
POP X (M[X] TOS)
REVERSE POLISH NOTATION
• Arithmetic Expressions: A + B
A+B Infix notation
+AB Prefix or Polish notation
AB+ Postfix or reverse Polish notation
The reverse Polish notation is very suitable for stack manipulation
e.g. A * B + C * D = AB * CD * +
Evaluation of Arithmetic Expressions
Any arithmetic expression can be expressed in parenthesis-free Polish notation, including
reverse Polish notation
(3 * 4) + (5 * 6) = 3 4 * 5 6 * + = 42
6
4 5 5 30
3 3 12 12 12 12 42
3 4 * 5 6 * +
Problems
Give Zero, one, two and three address programs for given equations:
1. A*B+C*D+E*F
2. A*B+A*(B*D+C*E)
3. [A*[B+C*(D+E)]]/[F*(G+H)]
4. (A+B*C)/(D–E*F+G*H)
5. A+B*[C*D+E*(F+G)]
6. (A+B–C)/(D*(5*F–G))
7. (A–B+C*(D*E–F))/(G+H*K)
