Digital Electronics (EE2402)

Lecture#14: Shift Registers

Dr. Manas Kumar Bera
Associate Professor
Dept. of EE, NIT Rourkela
Email: beramk@[Link] Room No. EE-235
Mobile No. 9775693776

1
 Objectives

• After completing this section, you should be able to

 Describe the operation of four types of shift registers
 Explain how data bits are entered into a shift register
 Describe how data bits are shifted through a register
 Explain how data bits are taken out of a shift register
 Explain the operation of a Johnson counter and ring counter

2
 Shift Register Operations
 Shift registers consist of arrangements of flip-flops and are important in applications
involving the storage and transfer of data in a digital system.
 A register has no specified sequence of states, except in certain very specialized
applications.
 A register, in general, is used solely for storing and shifting data (1s and 0s) entered
into it from an external source and typically possesses no characteristic internal
sequence of states.
 A register is a digital circuit with two basic functions: data storage and data
movement.
 The storage capability of a register makes it an important type of memory device.
Figure illustrates the concept of storing a 1 or a 0 in a D flip-flop. A 1 is applied to
the data input as shown, and a clock pulse is applied that stores the 1 by setting the
flip-flop. When the 1 on the input is removed, the flip-flop remains in the SET state,
thereby storing the 1.
 A similar procedure applies to the storage of a 0 by resetting the flip-flop, as also
illustrated in Figure.

3
 The flip-flop as a storage element

• The storage capacity of a register is the total number of bits (1s and 0s) of digital data it
can retain.
• Each stage (flip-flop) in a shift register represents one bit of storage capacity; therefore,
the number of stages in a register determines its storage capacity.

4
 Shift capability
• The shift capability of a register permits the movement of data from stage to stage within the
register or into or out of the register upon application of clock pulses.

Fig. Basic data movement in shift registers. (Four bits are used for illustration. The bits move
in the direction of the arrows.)

5
 Serial In/Serial Out Shift Registers
The serial in/serial out shift register accepts data serially—that is, one bit at a time on
a single line. It produces the stored information on its output also in serial form.

6
 Serial In/Parallel Out Shift Registers
Data bits are entered serially (least-significant bit first) into a serial in/parallel out shift register in
the same manner as in serial in/serial out registers.

Fig. A serial in/parallel out shift register

7
 Parallel In/Serial Out Shift Registers
• Figure illustrates a 4-bit parallel in/serial out shift register and a typical logic symbol.
• There are four data-input lines, D0, D1, D2, and D3, and a 𝑆𝐻𝐼𝐹𝑇/𝐿𝑂𝐴𝐷 input, which
allows four bits of data to load in parallel into the register.
• When SHIFT/LOAD is LOW, gates G1 through G4 are enabled, allowing each data bit to be
applied to the D input of its respective flip-flop.
• When a clock pulse is applied, the flip-flops with D = 1 will set and those with D = 0 will reset,
thereby storing all four bits simultaneously.
• When SHIFT/LOAD is HIGH, gates G1 through G4 are disabled and gates G5 through G7
are enabled, allowing the data bits to shift right from one stage to the next.
• The OR gates allow either the normal shifting operation or the parallel data-entry operation,
depending on which AND gates are enabled by the level on the SHIFT/LOAD input.
• Notice that FF0 has a single AND to disable the parallel input, D0. It does not require an
AND/OR arrangement because there is no serial data in.

8
 Parallel In/Serial Out Shift Registers

Fig. A 4-bit parallel in/serial out shift register.

9
 Parallel In/Parallel Out Shift Registers
 Parallel entry and parallel output of data have been discussed. The parallel
in/parallel out register employs both methods. Immediately following the
simultaneous entry of all data bits, the bits appear on the parallel outputs.
 Figure shows a parallel in/parallel out shift register.

10
 Bidirectional Shift Registers
• A 4-bit bidirectional shift register is shown in Figure 8–17. A HIGH on the 𝑅𝐼𝐺𝐻𝑇/𝐿𝐸𝐹𝑇
control input allows data bits inside the register to be shifted to the right, and a LOW enables
data bits inside the register to be shifted to the left.
• An examination of the gating logic will make the operation apparent. When the RIGHT/LEFT
control input is HIGH, gates G1 through G4 are enabled, and the state of the Q output of
each flip-flop is passed through to the D input of the following flip-flop.
• When a clock pulse occurs, the data bits are shifted one place to the right.
• When the RIGHT/LEFT control input is LOW, gates G5 through G8 are enabled, and the Q
output of each flip-flop is passed through to the D input of the preceding flip-flop.
• When a clock pulse occurs, the data bits are then shifted one place to the left.

11
 Shift Register Counters
• A shift register counter is basically a shift register with the serial output connected
back to the serial input to produce special sequences.
• These devices are often classified as counters because they exhibit a specified
sequence of states.
• Two of the most common types of shift register counters, the Johnson counter and
the ring counter, are introduced in this section.

12
 The Johnson Counter
• In a Johnson counter the complement of the output of the last flip-flop is connected
back to the D input of the first flip-flop (it can be implemented with other types of
flip-flops as well).
• If the counter starts at 0, this feedback arrangement produces a characteristic
sequence of states, as shown in Table for a 4-bit device and a 5-bit device.
• Notice that the 4-bit sequence has a total of eight states, or bit patterns, and that
the 5-bit sequence has a total of ten states.
• In general, a Johnson counter will produce a modulus of 2n, where n is the number
of stages in the counter.

13
The Johnson Counter

14
 The Ring Counter
• A ring counter utilizes one flip-flop for each state in its sequence.
• It has the advantage that decoding gates are not required. In the case of a 10-bit
ring counter, there is a unique output for each decimal digit.
• A logic diagram for a 10-bit ring counter is shown in Figure.
• The sequence for this ring counter is given in Table. Initially, a 1 is preset into the
first flip-flop, and the rest of the flip-flops are cleared. Notice that the interstage
connections are the same as those for a Johnson counter, except that Q rather than
𝑄ത is fed back from the last stage.

15
The Ring Counter

16