Unit 3.

Combinational Functions

Prepared by, Dr S C Tamane

UNIT III
 Combinational Functions:
 Introduction,
 Multiplexers and their use in Combinational Logic Design,
 Demultiplexers/Decoders and their use in Combinational Logic
Design,
 Adders and their use as Subtractors,
 Code Converters
Books

 Text Books:
1. R.P. Jain, “Modern Digital Electronics”, Tata McGraw Hill Publication, 4th Edition, 2010.
2. M. M. Mano, “Digital Logic and Computer Design”, Prentice Hall of India Publication, 4 th
Edition, 2006.

 Reference Books:
1. D. P. Leach, A. P. Malvino, G. Saha, “Digital Principles and Applications”,Tata McGraw Hill
Publication, 8th Edition, 1993.
2. Comer, “Digital Logic & State Machine Design”, Oxford Universities Press, 3rd Edition,
2014

 E-Sources:
 NPTEL videos
 Introduction
• The traditional methods of combinational circuit designs discussed
involve simplification and realization using gates.
• Using these methods, complex functions have been integrated (MSI)
and are easily available in IC form.
• This chapter presents these complex ICs and their applications in
combinational system design.
• Examples of these devices are:
– Multiplexers, Demultiplexers
– Adders
– Parity generators/checkers
– Priority encoders, decoders
– Comparators etc.
• These devices significantly reduce IC package count thereby reducing
the system cost.
 Multiplexers and their use in
Combinational Logic Design

• The Multiplexer (data selector) is a logic circuit that allows one of the n
data inputs at the output. Fig shows a 4:1 multiplexer. It has
– 4 data input lines (I0 to I3)
– 2 select lines (S1, S0)
– 1 data output line Y
• One of the four data inputs will appear at the output depending on the
value of S1, S0.
 Multiplexers and their use in
Combinational Logic Design
• Its truth table and realization
is given as follows:

Select Inputs Output

S1 S0 Y
0 0 I0
0 1 I1
1 0 I2
1 1 I3
 Multiplexers and their use in
Combinational Logic Design
• Multiplexers are one of the widely used standard
logic circuits in digital design.
• So, commercially available in various sizes, such as
2:1, 4:1, 8:1 and 16:1 multiplexers.
• Its output Y is given by:
 Multiplexers and their use in
Combinational Logic Design
• As it is available in various sizes, the input selected is controlled by
a set of select inputs.
 Multiplexers and their use in
Combinational Logic Design
• Following table gives the truth table of a 4:1
multiplexer with active low enable input (G).
Enable Input Select Inputs Output
G S1 S0 Y
0 0 0 I0
0 0 1 I1
0 1 0 I2
0 1 1 I3
1 X X 0

• Its output Y will be:

Multiplexers and their use in
Combinational Logic Design
Combinational Logic Design Using Multiplexers

• Available Multiplexer ICs

Combinational Logic Design Using Multiplexers

• Use of Multiplexers offers the following

advantages:
– Simplification of logic expression is not required
– It minimizes the IC package count
– Logic design is simplified
Combinational Logic Design Using Multiplexers

• For using the multiplexer as a logic element,

either the truth table or one of the canonical
forms of logic expression must be available.
• The design procedure is given below:
– Identify the decimal number corresponding to each
minterm in the expression.
– The input line corresponding to these numbers are
to be connected to logic 1 level.
– All other input lines are to be connected to logic 0
level
– The inputs are to be applied to select inputs
• Since there are
4 variables,
therefore, a
multiplexer
with four
select inputs is
required.
 Solution
• First Method:
– This can be realized using the method used in
above problem
– The input lines 2, 4, 6, 7, 9, 10, 11, 12 and 15 are
to be connected to logic 1 and the input lines 0, 1,
3, 5, 8, 13 and 14 are to be connected to logic 0.
 Solution
• Second Method:
– A four variable truth table or logic expression can
be realized by using 8:1 multiplexer instead of a
16:1 multiplexer.
– For this partition the truth table is shown by
dotted lines.
Solution
 Multiplexer Tree
• Since 16 to 1 multiplexers are the largest
available ICs, therefore to meet the larger
input needs there should be a provision for
expansion.
• This is achieved with the help of
enable/strobe inputs and multiplexers stacks
or trees are designed.
• Two commonly used methods for this
purpose are illustrated in figures (next slide).
Multiplexer Tree
• This uses two 16:1
multiplexers (M1 and
M2) for the realization of
32:1 multiplexer.
• The lower order 16 data
input lines (I0—I15) are
applied at the data
input terminals of the
multiplexer M1.
• The higher order 16 data
input lines (I16—I31) are
applied at the data
input terminals of the
multiplexer M2.
Multiplexer Tree
• For a 32:1 multiplexer, the
number of select input
lines is required to be 5.
• The 5 bit select inputs are
ABCDE.
• The most significant select
input bit A is applied at G1
and is applied at G2.
• B, C, D, E are connected to
S3, S2, S1, S0 inputs of both
the multiplexers.
• The output F of the
multiplexer is obtained by
using an OR gate, where
F=Y1+Y2.
Multiplexer Tree
• When A=0, the
multiplexer M1 is enabled
and M2 is disabled.
• Thereby allowing one of
the lower order 15 bits to
Y1, depending upon the
value of BCDE.
• Y2=0 , therefore, F=Y1.
• When A=1, the
multiplexer M2 is enabled
and M1 is disabled.
• F=Y2.
Multiplexer Tree
• The circuit of figure
uses 2:1 multiplexer
instead of an OR
gate.
• When A=0, F=Y1 and
When A=1, F=Y2
• Both circuits perform
similar operations.
 Demultiplexers/Decoders and their use in
Combinational Logic Design
• The Demultiplexers
performs the reverse
operation of a
multiplexer.
• It accepts a single
input and distributes it
over several outputs.
• Following fig. gives the
block diagram of a
demultiplexer.
• The select input code
determines to which
output the data input
will be transmitted.
 Demultiplexers/Decoders and their use in
Combinational Logic Design
• output lines =n
• Select lines=m, where n=2 m
• The data input Di will appear on the
output line selected by the select
input.
• If the decimal equivalent of select
input is 4, then the data will appear
on D4 output line.
• This circuit can also be used as
binary to decimal decoder with
binary inputs applied at the select
input lines and the output will be
obtained on the corresponding line.
• The data input line will be
connected to logic 1 level.
• This device is very useful if multiple
output combinational circuit is to
be designed, because this needs
minimum package count.
Demultiplexers/Decoders and their use in
Combinational Logic Design
 Demultiplexers/Decoders and their use in
Combinational Logic Design
• Unlike the multiplexer, the decoder does
require some gates in order to realize Boolean
expression in canonical SOP form.
Realization
of logic
circuit:
 Demultiplexer Tree
• Since 4 line to 16 line decoders are the largest
available circuits in ICs, to meet the larger inputs
need there should be a provision for expansion.
• This is made possible by using enable input
terminal.
• Following figures shows a 5 line to 32 line
decoder and 8 line to 256 line decoder using 4
line to 16 line decoders.
• In a similar way any m line to n line decoder can
be implemented.
6.1 Realize the logic function of the given table using:
a) A 16:1 multiplexer IC 74150
b) An 8:1 multiplexer IC 74152
6.1 Realize the logic function of the given table using:
a) A 16:1 multiplexer IC 74150
b) An 8:1 multiplexer IC 74152

• The data output is inverted

input, i.e. complement of the
data input line selected.
• Since the data output is 1
when the input variables
correspond to decimal
numbers 2, 4, 6, 7, 9, 10, 11,
12 and 15, therefore the data
input lines corresponding to
these decimal numbers are to
be connected to logic 0 and
the data input lines 0, 1, 3, 5,
8, 13, and 14 are to be
connected to logic 1.
b) An 8:1 multiplexer IC 74152
6.8 Realize the following functions of four variables using
a) 8:1 multiplexer
b) 16:1 multiplexer
c) 4 to 16 line decoder with active low outputs.
D C B A f1 f2 f3
0 0 0 0 1 1 0
0 0 0 1 0 1 0
Solution: a) The truth table is
0 0 1 0 0 1 1 reduced to following table for
0 0 1 1 1 1 0 realization using 8:1
0 1 0 0 0 0 1 multiplexers.
0 1 0 1 1 0 1
0 1 1 0 1 0 1
0 1 1 1 0 0 0
1 0 0 0 0 0 1
1 0 0 1 1 0 0
1 0 1 0 1 0 0
1 0 1 1 0 1 0
1 1 0 0 1 1 1
The circuits can now be
1 1 0 1 0 0 0
designed separately for f1, f2,
1 1 1 0 0 1 0 f3 outputs using multiplexers
1 1 1 1 1 1 0 and inverters.
6.8 Realize the following functions of four variables using
a) 8:1 multiplexer
b) 16:1 multiplexer
c) 4 to 16 line decoder with active low outputs.
D C B A f1 f2 f3
0 0 0 0 1 1 0
0 0 0 1 0 1 0 Solution: b)
0 0 1 0 0 1 1 Output 1 values will be
0 0 1 1 1 1 0 connected to logic 1
0 1 0 0 0 0 1 And Output 0 values will be
0 1 0 1 1 0 1 connected to logic 0 for f1, f2
0 1 1 0 1 0 1
and f3 separately.
0 1 1 1 0 0 0
1 0 0 0 0 0 1
Solution: c) The circuit can be
1 0 0 1 1 0 0
1 0 1 0 1 0 0
designed using one
1 0 1 1 0 1 0
demultiplexer and two 8 input
1 1 0 0 1 1 1 and one 6 input NAND gates.
1 1 0 1 0 0 0
1 1 1 0 0 1 0
1 1 1 1 1 1 0
6.9 Design a 40:1 multiplexer using 8:1 multiplexers.
 Design Examples
• Arithmetic Circuits:
• Half Adder: A logic circuit for the addition of two one bit numbers is
referred to as an half adder.
• Inputs: A and B The logical expression for S and C
• Outputs: S sum, C Carry outputs is as follows:
• Truth Table for Half Adder: S=
C = AB
Inputs Outputs
A B S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
 Design Examples
• Arithmetic Circuits:
• Full Adder: An half adder has only 2 inputs and there is no provision to
add a carry.
• The third input terminal is added to add An, Bn, Cn-1 where, An and Bn are
the nth order bits of the numbers A and B resp. and Cn-1 is the carry
generated from the addition of (n-1)th order bits.
• This circuit is referred as Full Adder
• Truth Table for Full Adder:
Inputs Outputs
A B C S C
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
 Design Examples
• Arithmetic Circuits:
• Half Subtractor: A logic circuit for the subtraction of B (subtrahend) from A
(minuend) where A and B are 1-bit numbers is referred to as a half subtractor.
• Inputs: A and B
• Outputs: D Difference, C Borrow The logical expression for D and C
• Truth Table for Half Subtractor: outputs is as follows:

Inputs Outputs
A B D C
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
 Design Examples
• Arithmetic Circuits:
• Full Subtractor: This needs full subtractor circuit for performing
multibit subtraction wherein a borrow from the previous bit position
may also be there.
• Inputs: An, Bn, Cn-1. Outputs: Dn, Cn
• TT for Full Subtractor:
Inputs Outputs
A B C S C
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
Adders and their use as Subtractors
• Using half and full adders and subtractors one
can design adders and subtractors for n bit
numbers.
• Addition and subtraction can be performed using
only adders (we can perform subtraction using
adders and 2’sc).
• An adder circuit for addition of two n-bit binary
numbers consists of n full adder circuits.
• It accepts two n-bit binary numbers as inputs and
produces an (n+1)-bit binary number as the sum.
Adders and their use as Subtractors
• A and B are the two n-bit inputs to be added and
Cn-1Sn-1Sn-2…..S2S1S0 is their sum.
• A half adder may be used to add the LSBs A0 and B0.
• For cascading these adders to increase the number
of bits to be added, the CARRY input terminal is
required for the adder to add the LSBs.
• All the adders used are full adders.
• Using this scheme, the carry has to ripple down the
line of cascaded adders from the LSB to MSB
position which decreases the operating speed of
the adder.
Digital Comparators
• Comparators can be
designed for comparing
multibit numbers.
• Figure shows the block
diagram of an n-bit
comparator.
• Inputs: two n-bit numbers A
and B
• Output:
– high: A>B, A=B and A<B
 Digital Comparators

• 1 bit Comparator
• Inputs: two 1-bit numbers A and B
• Output: high: A>B, A=B and A<B

A B A>B A=B A<B

0 0 0 1 0
0 1 0 0 1
1 0 1 0 0
1 1 0 1 0
 Digital Comparators
Inputs Outputs

A1 A0 B1 B0 A>B A=B A<B

• Table gives the truth table of a 2-
0 0 0 0 0 1 0
bit comparator.
0 0 0 1 0 0 1 • Simplified expressions for A>B,
0 0 1 0 0 0 1
A=B and A<B using k-maps are as
0 0 1 1 0 0 1
0 1 0 0 1 0 0
follows:
0 1 0 1 0 1 0
0 1 1 0 0 0 1
0 1 1 1 0 0 1
1 0 0 0 1 0 0
1 0 0 1 1 0 0
1 0 1 0 0 1 0
1 0 1 1 0 0 1
1 1 0 0 1 0 0
1 1 0 1 1 0 0
1 1 1 0 1 0 0
1 1 1 1 0 1 0
Digital Comparators

Circuit of a 2 bit
comparator
 Digital Comparators
• In a 4-bit comparator the condition of A>B can
be possible in the following four cases:
– If A3 = 1 and B3 = 0
– If A3 = B3 and A2 = 1 and B2 = 0
– If A3 = B3, A2 = B2 and A1 = 1 and B1 = 0
– If A3 = B3, A2 = B2, A1 = B1 and A0 = 1 and B0 = 0
 Digital Comparators
• Similarly the condition for A<B can be possible in
the following four cases:
– If A3 = 0 and B3 = 1
– If A3 = B3 and A2 = 0 and B2 = 1
– If A3 = B3, A2 = B2 and A1 = 0 and B1 = 1
– If A3 = B3, A2 = B2, A1 = B1 and A0 = 0 and B0 = 1
• The condition of A=B is possible only when all the
individual bits of one number exactly coincide
with corresponding bits of another number.
 Digital Comparators
Comparing inputs Outputs
The truth
A3B3 A2B2 A1B1 A0 B0 A>B A<B A=B
table of a
A3>B3 X X X H L L
4 bit
A3<B3 X X X L H L
comparat
or is A3=B3 A2>B2 X X H L L

given in A3=B3 A2<B2 X X L H L

the A3=B3 A2=B2 A1>B1 X H L L
following A3=B3 A2=B2 A1<B1 X L H L
table. A3=B3 A2=B2 A1=B1 A0>B0 H L L
A3=B3 A2=B2 A1=B1 A0<B0 L H L
A3=B3 A2=B2 A1=B1 A0=B0 H L L
A3=B3 A2=B2 A1=B1 A0=B0 L H L
A3=B3 A2=B2 A1=B1 A0=B0 L L H
H = High Voltage Level, L = Low Voltage Level, X = Don’t Care
 Digital Comparators
• The function table of 7485 4 bit comparator
is given in the following table.
 Digital Comparators
• 4-bit comparators: MSI 7485, which can compare straight
binary and natural BCD codes.
• These ICs can be cascaded to compare words of greater
lengths without external gates.
• The A>B, A=B, A<B outputs of a stage handling LSBs are
connected to the corresponding A>B, A=B, A<B cascading
inputs of the next stage handling MSBs.
• The stage handling LSBs must have A=B input connected to
logic 1 level and A>B and A<B inputs connected to logic 0
or 1 level.
• Example 6.6
• Design a 5 bit comparator using a single 7485 and one gate.
• Solution:
• The two 5-bit numbers to be compared are A4 A3 A2 A1 A0 and B4 B3 B2 B1 B0

A B EX-NOR
0 0 1
0 1 0
1 0 0
1 1 1

1) A=10001
B=11000
2) A=11001
B=11000
A<B
3) A=01011
B=10111
4) A=11111
B=11111
5) A=11110
B=11111
• 6.14 Design a 8 bit comparator using only 2 7485s.
• Solution:
• The comparator C1 compares the least significant 4 bits.
• It’s A>B, A=B, A<B outputs are connected to the corresponding
cascading inputs of C2 resp. The complete circuit is as follows:
• Example 6.7
• Design a 24
bit
comparator
using six
7485
comparator
s in two
levels.
• 6.15 Verify the operation of the 24 bit comparator of following figure
for the following numbers:
• A=100110000111011001010010
• B=101110000111011000100011
• Solution:
• 6.15 Verify the operation of the 24 bit comparator of following figure
for the following numbers:
• A=100110000111011001010010
• B=101110000111011000100011
• Solution:
 BCD to 7 Segment Decoder
• A digital display that consists of 7 LED segments is used to display decimal
numerals in digital systems.
• For using this display device, the data has to be converted from some
binary code to the code required for the display.
• The binary code used is natural BCD.
 Truth Table of BCD to 7 segment
Decoder
Decimal Inputs Outputs
Digit
Displayed A B C D a b c d e f g
0 0 0 0 0 1 1 1 1 1 1 0
1 0 0 0 1 0 1 1 0 0 0 0
2 0 0 1 0 1 1 0 1 1 0 1
3 0 0 1 1 1 1 1 1 0 0 1
4 0 1 0 0 0 1 1 0 0 1 1
5 0 1 0 1 1 0 1 1 0 1 1
6 0 1 1 0 0 0 1 1 1 1 1
7 0 1 1 1 1 1 1 0 0 0 0
8 1 0 0 0 1 1 1 1 1 1 1
9 1 0 0 1 1 1 1 0 0 1 1
 BCD to 7 Segment Decoder
• ABCD is the natural BCD code for numerals 0
through 9.
• The K-maps for each of the outputs a through g
are given below:
• The entries in the K-map corresponding to six
binary combinations not used in the truth table
are X-don’t-care.
a b
1 1
0 1
1 1
1 1
0 1
1 0
0 0
1 1
1 1
1 1
c d
1 1
1 0
0 1
1 1
1 0
1 1
1 1
1 0
1 1
1 0
e f
1 1
0 0
1 0
0 0
0 1
0 1
1 1
0 0
1 1
0 1
g
0
0
1
1
1
1
1
0
1
1
 Code Converters
• There is a wide variety of binary codes used in digital systems.
• Some of these are:
– BCD
– Excess-3
– Gray
– Octal
– Hexadecimal
• Often it is required to convert from one code to another.
• Ex. The input to a digital system may be in natural BCD and the
output may be seven segment LEDs.
• The digital system used may be capable of processing the data in
straight binary format.
• So the data has to be converted from BCD to binary at the output.
 BCD to Binary Converters
• The block diagram of BCD to binary converter IC 74184 is
given in the following fig.:
• This device can be used as a 1 ½ decade BCD-to-Binary
converter.
 BCD to Binary Converters
• The BCD inputs are applied at the input terminals A through E and
the LSB of the least significant BCD digit bypasses the converter and
appears as the LSB of the binary output.

• It accepts two BCD digits, a

full digit D1 C1 B1 A1 and the
two least significant bits of a
second digit B2 A2.
• The BCD inputs 00 through 39
can be converted to
corresponding binary output
by this circuit.
• Terminals Y6, Y7, and Y8 are
not used for BCD to Binary
conversion.
 BCD to Binary Converters
• DM74184 BCD-TO-BINARY CONVERTERS:
• The 6-bit BCD-to-binary function of the DM74184 is
analogous to the algorithm:
– The 6-bit BCD-to-binary function of the DM74184 is
analogous to the algorithm: a. Shift BCD number right one
bit and examine each decade. Subtract three from each 4-
bit decade containing a binary value greater than seven.
– b. Shift right, examine, and correct after each shift until
the least significant decade contains a number smaller
than eight and all other converted decades contain zeros.
 Truth Table of 74184 BCD to Binary Converter
BCD Inputs Outputs
Words E D C B A G Y5 Y4 Y3 Y2 Y1
0-1 0 0 0 0 0 0 0 0 0 0 0
2-3 0 0 0 0 1 0 0 0 0 0 1
4-5 0 0 0 1 0 0 0 0 0 1 0
6-7 0 0 0 1 1 0 0 0 0 1 1
8-9 0 0 1 0 0 0 0 0 1 0 0
10-11 0 1 0 0 0 0 0 0 1 0 1
12-13 0 1 0 0 1 0 0 0 1 1 0
14-15 0 1 0 1 0 0 0 0 1 1 1
16-17 0 1 0 1 1 0 0 1 0 0 0
18-19 0 1 1 0 0 0 0 1 0 0 1
20-21 1 0 0 0 0 0 0 1 0 1 0
22-23 1 0 0 0 1 0 0 1 0 1 1
24-25 1 0 0 1 0 0 0 1 1 0 0
26-27 1 0 0 1 1 0 0 1 1 0 1
28-29 1 0 1 0 0 0 0 1 1 1 0
30-31 1 1 0 0 0 0 0 1 1 1 1
32-33 1 1 0 0 1 0 1 0 0 0 0
34-35 1 1 0 1 0 0 1 0 0 0 1
36-37 1 1 0 1 1 0 1 0 0 1 0
38-39 1 1 1 0 0 0 1 0 0 1 1
Any X X X X X 1 1 1 1 1 1
 BCD to Binary Converters
• Terminals Y6, Y7, and Y8 are used to obtain 9’s complement and the 10’s
complement of BCD numbers, useful for BCD arithmetic operations.
• Following fig. gives block diagram of BCD 9’s complement converter.
 BCD to Binary Converters
• Terminals Y6, Y7, and Y8 are used to obtain 9’s complement and the 10’s
complement of BCD numbers, useful for BCD arithmetic operations.
• Following table gives its truth table.
 BCD to Binary Converters
• BCD input is applied at DCBA input terminals and its 9’s complement
appears at ND, NC, NB, NA terminals.
• Following fig. gives block diagram of BCD 10’s complement converter.
 BCD to Binary Converters
• BCD input is applied at DCBA input terminals and its 9’s
complement appears at ND, NC, NB, NA terminals.
• Following table gives its truth table.
Various Binary Codes
 Binary to Gray Code Converter
Binary Gray
A B C D G1 G2 G3 G4
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
.. .. .. .. .. .. .. ..
 Gray to Binary Code Converter
Binary Gray
A B C D G1 G2 G3 G4
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
.. .. .. .. .. .. .. ..
 BCD to Excess-3 conversion
BCD Code Excess-3
D C B A W X Y Z
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
BCD to Excess-3 conversion
 Excess-3 to BCD conversion K Map for C
K Map for D
Excess-3 BCD Code
W X Y Z D C B A
0 0 1 1 0 0 0 0
0 1 0 0 0 0 0 1
0 1 0 1 0 0 1 0
0 1 1 0 0 0 1 1
0 1 1 1 0 1 0 0
1 0 0 0 0 1 0 1 K Map for B K Map for A
1 0 0 1 0 1 1 0
1 0 1 0 0 1 1 1
1 0 1 1 1 0 0 0
1 1 0 0 1 0 0 1
 Excess-3 to BCD conversion

A= WX + WYZ

B= X’Y’ + X’Z’ + XYZ

C= Y’Z + YZ’

D=Z’

Here,
E3, E2, E1 and E0
corresponds to W, X, Y, Z
and B3, B2, B1 and B0
corresponds to A, B, C, D
 6.5 Design a Gray to BCD code converter using two
dual 4:1 multiplexer ICs (74153) and some gates

Gray Code BCD Code

G3 G2 G1 G0 D C B A
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 1 0 0 1 0
0 0 1 0 0 0 1 1
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
0 1 0 1 0 1 1 0
0 1 0 0 0 1 1 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
 6.5 Design a Gray to BCD code converter using two
dual 4:1 multiplexer ICs (74153) and some gates
For A output:
Gray Code BCD Code
G3 G2 G1 G0 D C B A
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 1 0 0 1 0
0 0 1 0 0 0 1 1
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
0 1 0 1 0 1 1 0
0 1 0 0 0 1 1 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
6.5 Design a Gray to BCD code converter using two
dual 4:1 multiplexer ICs (74153) and some gates
Similarly, we can obtain the expression for the D, C and B
outputs. These are given as follows:

The G3 and G2 are used as select inputs.

The complete circuit can be drawn which requires two
74153 packages and one 7486 (EX-OR) package.
6.7 Design a BCD to Gray code converter using
a) 8:1 multiplexers
b) Dual 4:1 multiplexers and some gates
Solution a)
BCD Code Gray Code
D C B A G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0 The circuit can now be designed using
0 1 0 0 0 1 1 0 74151A ICs (One for each of the
0 1 0 1 0 1 1 1 outputs).
The D, C, and B inputs are to be applied
0 1 1 0 0 1 0 1 to the S2, S1 and S0 select inputs resp.
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
6.7 Design a BCD to Gray code converter using
a) 8:1 multiplexers
b) Dual 4:1 multiplexers and some gates

Solution b)
BCD Code Gray Code This can be solved using the procedure
D C B A G3 G2 G1 G0 used in previous problem.
The circuit can be designed using two
0 0 0 0 0 0 0 0
74153 ICs and two (7486) Ex-OR gates.
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
 Assignment
• Solve following exercises:
– 6.1 a) and b)
– 6.4
– 6.5 a) and b)
– 6.6 a) and b)
– 6.14