DIGITAL LOGIC AND
COMPUTER ORGANIZATION
Lecture 11-12: Sequential Logic
Timing Analysis
ELEC3010
ACKNOWLEGEMENT
I would like to express my special thanks to Professor Zhiru Zhang
School of Electrical and Computer Engineering, Cornell University
and Prof. Rudy Lauwereins, KU Leuven for sharing their teaching
materials.
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COVERED IN THIS COURSE
❑ Binary numbers and logic gates
❑ Boolean algebra and combinational logic
❑ Sequential logic and state machines
❑ Binary arithmetic
Digital logic
❑ Memories
❑ Instruction set architecture
❑ Processor organization Computer
❑ Caches and virtual memory
❑ Input/output Organization
❑ Advanced topics
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PROPAGATION DELAY (T PD)
❑ Time for change in input to change the output
❑ Typically specified between 50% points
❑ Circuits have minimum and maximum propagation delays
– Minimum sometimes called the contamination delay and
maximum the propagation delay
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TIMING DIAGRAM
❑ Shows how outputs respond to changes in inputs over time
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GLITCH (HAZARD)
❑ Unplanned momentary switching of an output
❑ Types of glitches:
▪ Static 1-hazard: Input change causes output
to go from 1 to 0 to 1 (should have stayed 1)
▪ Static 0-hazard: Input change causes output
to go from 0 to 1 to 0 (should have stayed 0)
▪ Dynamic hazards: Input change causes a change
from 0 to 1 to 0 to 1 or from 1 to 0 to 1 to 0 (there
should be just one change)
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GLITCH EXAMPLE
❑ Glitches are typically caused by unequal signal propagation
delays through the circuit
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TIMING DIAGRAM SHOWING GLITCH
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DO GLITCHES MATTER?
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DO GLITCHES MATTER?
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BUT WHAT ABOUT THIS SITUATION?
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SYNCHRONOUS CIRCUITS
❑ On the triggering clock edge (clock tick), the input of a flip-
flop is transferred to the output and held
▪ All flip-flops (FFs) are synchronized to capture the inputs
simultaneously on the clock tick
❑ Must ensure the output of the combinational logic has
settled before the next clock tick
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STABLE FF SITUATION
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WHAT IF THIS HAPPENS?
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METASTABLE STATE
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AVOIDING TIMING FAILURE
❑ Possible causes of metastability and wrong value capture
▪ Clock pulse that is too narrow
▪ Input changes too soon before a clock edge
▪ Input changes too soon after a clock edge
❑ Avoid by meeting setup time, hold time, and minimum
clock pulse width specifications
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SEQUENTIAL CIRCUIT TIMING ANALYSIS
❑ Timing analysis involves calculating the time delays
between all FF pairs within the circuit
❑ To determine the maximum operating frequency and
ensure that setup time requirements are met
▪ The clock cannot be too fast
❑ To ensure that hold time requirements are met
▪ The minimum propagation delay of the combinational logic
(contamination delay) cannot be too small
▪ Independent of clock frequency
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IMPORTANT TIMING PARAMETERS
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SETUP TIME CONSTRAINT
❑tsetup is the minimum amount of time before the triggering
edge during which FF input must be stable
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DETERMINING CLOCK CYCLE TIME
❑ tffpd(max) + tcomb(max) + tsetup ≤ tclk
Every circuit path between every pair of FFs must satisfy the above
equation to run the circuit at a frequency of 1/tclk
❑ Consider maximum propagation delays (the longest timing
path) to determine the maximum clock frequency
▪ Worst case temperature and voltage
▪ Worst case manufacturing variations
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CAN YOU DO IT?
What’s the best achievable cycle time??
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DETERMINING CLOCK CYCLE TIME
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HOLD TIME CONSTRAINT
❑ thold is the minimum amount of time after the triggering
edge during which FF input must remain stable
▪ Otherwise, the receiving flip-flop may be contaminated with an
unexpected value
❑ Need to consider minimum propagation delays (the
shortest timing path) for hold time calculations
tffpd(min) + tcomb(min) ≥ thold
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EXAMPLE: HOLD TIME CONSTRAINT
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CAN YOU DO IT?
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CLOCK SKEW COMPLICATES MATTERS FURTHER
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CYCLE TIME WITH CLOCK SKEW
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CYCLE TIME WITH NEGATIVE CLOCK SKEW
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CYCLE TIME WITH POSITIVE CLOCK SKEW
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CAN YOU DO IT?
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CAN YOU DO IT?
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HOLD TIME WITH POSITIVE CLOCK SKEW
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HOLD TIME WITH NEGATIVE CLOCK SKEW
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CAN YOU DO IT?
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CAN YOU DO IT?
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TIMING ANALYSIS DISCUSSION (1)
❑ To achieve a higher clock frequency (i.e., smaller clock
period), would you prefer
1) A smaller combinational delay or a larger one?
2) A smaller setup time or a larger one?
3) A smaller hold time or a larger one?
4) A negative clock skew or a positive one?
• A smaller skew or a larger one?
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EXAMPLE: SETUP TIME ANALYSIS
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TIMING ANALYSIS DISCUSSION (2)
❑ To avoid hold time violation, would you prefer
1) A smaller combinational delay or a larger one?
2) A smaller setup time or a larger one?
3) A smaller hold time or a larger one?
4) A negative clock skew or a positive one?
• A smaller skew or a larger one?
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BEFORE NEXT CLASS
• Textbook: 5.2-5.5
• Next time: Binary Arithmetic
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