IF009

RFIT2007-IEEE International Workshop on Radio-Frequency Integration Technology, Dec. 9-11, 2007, Singapore

A Simulink Model for All-Digital-Phase-Locked-Loop

Xiaoyan Wang, Yeung Bun Choi, Mingkyu Je and Wooi Gan Yeoh
Integrated Circuits and Systems Laboratory
Institute of Microelectronics, Singapore
[email protected]

Abstract—A simulink model for All-Digital-Phase-Locked-

Look (ADPLL) is proposed in this paper. The study is based on
ADPLL implemented in an all-digital RF transceiver. Simulation
results in simulink give the performance overview of the ADPLL.

I. INTRODUCTION
Using digital techniques to implement RF circuits has
become a new trend in recent years. An all-digital transceiver
has been proposed recently [1]. Although it is intended to
Figure 1. Block diagram of ADPLL [1].
implement all the blocks as digital circuit, certain analog
circuits are not replaceable, such as oscillator. Therefore, the limited by the finest capacitance value controlled by the LSB
modeling and simulation of such kind of system becomes an digital bit. A solution to achieve even finer tuning step is to
important issue. A simulation platform based on behavior dither the LSB digital bit, thus controlling its time-averaged
model and digital circuit is needed in this case. value with a finer resolution [1]. The time-dithering is realized
In this paper, we focus on one of the key block in a by using an - converter. The structure proposed in [1]
transceiver, All-Digital-Phase-Locked-Loop (ADPLL). A works in phase domain instead of frequency domain,
VHDL model has been proposed in [1], taking advantage of therefore, the phase detector is realized as a simple subtractor.
event-driven process. Another ADPLL model implemented in The loop filter can be realized as a gain factor since there is no
Matlab is proposed in [2], taking advantage of the flexibility high frequency element in the output of the phase detector.
of modeling and mathematical manipulation that characterizes Referring back to Fig. 1, Frequency Control Word (FCW)
Matlab [2]. In this paper, we set our simulation platform in is to select the channel for PLL. Time-to-Digital Converter
simulink, taking fully use of the build-in blocks provided by (TDC) is used to convert the phase error into digital signal
the software. Simulations are done in both frequency and time with fine resolution. Assuming FCW is an arbitrary number Y,
domain to validate the model proposed in this paper. and the reference frequency is Fref. In the lock status, DCO
There has been such model for the traditional analog PLL oscillates at the frequency Y×Fref.
[3]. However, in such case, since most of the blocks are The working principle of ADPLL is described as below. In
analog circuits, the model of the PLL remains at behavior each period of the reference signal, the number of the DCO
level, and gives more indication about system performance, output periods is counted, and then compared with FCW. The
rather than guidance for circuit design. While for ADPLL, as difference therefore represents the phase error between DCO
most of the blocks are digital circuits, simulink model of such output and reference signal. This phase error is then separated
blocks gives a direct guidance to the later real circuit design. into integer and fractional part. The integer part is to control
switching capacitance in DCO, therefore to do the coarse
II. ADPLL DESCRIPTION tuning. The fractional part is fed to an - converter, and then
The ADPLL structure used to validate the simulink model to control the DCO for fine tuning.
is proposed in [1], and the block diagram is shown in Fig. 1.
Similar to analog PLL, an ADPLL comprises three sub blocks III. SIMULINK MODEL
as well, i.e., phase detector, loop filter and digital-controlled- Based on the above discussion, the whole ADPLL can be
oscillator (DCO). The frequency tuning in DCO is realized by simplified into two loops working concurrently, i.e., the
switching on and off the capacitance through digital control integer part of FCW, and the fractional part of FCW. The
bits in stead of voltage in VCO. In this case, the tuning step is block diagram is as shown in Fig. 2, where loop A is the
integer loop, and loop B is the fractional loop.

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 N (integer part of FCW)
Fref

Fref Fref-retimed DCO

Re-timing Counter A + Vctr
DCO
-
Counter A N=8 2*N=2*8 ……

Counter B 1 2 3 4 5 6 7 8 ………………… 14
Loop A Counter B
Vctr 2 2

Counter C
+ Sigma-delta

M(fractional part of FCW)

Figure 3. Waveform of counter A and B in integer phase comparator.
TDC -
Loop B
Ref
Figure 2. Block diagram of ADPLL in simulink.
Ref_retimed
Assuming first FCW is an integer number N, only loop A
is needed. In loop A, there are two counters A and B. Counter DCO
A accumulates by N at each rising edge of the reference
signal, and counter B accumulates by 1 at each rising edge of ε
the DCO output signal. The output from counter A and B are
compared at the rising edge of reference signal and the result
Figure 4. Waveform to demonstrate the fractional phase difference.
is the digital control bits of DCO. A timing diagram is shown
in Fig. 3. Assuming FCW is 8, the center frequency of DCO is
6×Fref, Kvco is Fref/bit, and DCO oscillates at the center A. System Model
frequency by default. In the first cycle, counter A gives a 8, A system model is set up first, for close-loop frequency
and counter B gives 6. Therefore the phase error is 2, i.e., the domain analysis. The model is shown in Fig. 5. The non-linear
control bit is 2. Thus, the output frequency of DCO changes components, such as sample/hold device and - converter
from 6×Fref to 8×Fref. Since the phase detector works are not included in this case. The input/output of the model are
continuously, the output remains 2 in the following cycles, so phases of the reference signal and DCO output. Integrator is
does the output frequency remain at 8×Fref. needed to convert from frequency to phase. The input phase is
Now considering the case that when FCW is a non-integer multiplied with FCW, and then compared with DCO output
number. Referring back to Fig. 2, there is a re-timing block phase. The phase difference, going through a gain stage,
after the reference signal. This block is to synchronize the controls the DCO frequency. The simulation result is shown in
reference signal with the DCO output. The waveform of the Fig. 6(a), which indicates the 3-dB cut-off frequency of the
reference signal, re-timed reference signal and DCO output closed-loop ADPLL. The loop bandwidth can be adjusted by
are shown in Fig. 4. It has been derived in [1] that  is the varying the gain factor, however, it compromises with phase
fractional part of the phase error between reference signal and noise performance.
DCO output. The  is measured by TDC, and then compared The second step is to include the non-linear components as
with the fractional part of FCW. The result is a fractional shown in Fig. 7. The blocks added are DCO control word
number, representing the fractional part of the phase error. converter and an - converter. In the first block, the phase
This number is thus converted into a train of ‘1’ and ‘0’ by an error is sampled and held at a sampling time of 1/Fref, and
- converter. Loop A and B work concurrently when FCW is then separated into integer and fractional part. The integer part
non-integer, to tune the DCO output at the right frequency. controls the DCO frequency directly, while the fractional part
is converted first by an - converter, and then to control the
DCO frequency. A differentiator is added to convert phase
information into frequency information.

Figure 5. System model of ADPLL for LTI analysis.

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 Phase of the reference signal

Phase difference

Phase of DCO

DCO frequency

DCO control voltage

(a) (b)
Figure 6. (a) Frequency response of the model shown in Fig. 5; (b) Output waveform of the model shown in Fig. 7.

Figure 7. System model of ADPLL for time-domain analysis.

The simulation result is shown in Fig. 6(b). As can be - converter implemented is of 3rd-mesh structure. The
seen, the phase of reference signal and DCO keep clock frequency is set to be ¼ of the DCO frequency. The
increasing, while the phase error settles down after 5μs, so DCO generates a sinusoidal signal of a certain frequency
does the DCO frequency. according to the control bits. The reference frequency is set
at 1MHz, FCW is set as 112.8, TDC resolution is 100KHz,
B. Time-Domain Model gain factor is 1/8, the center frequency of VCO is 100MHz
In the last step, a time-domain ADPLL model is set up, and Kvco/bit is 1MHz. Therefore, in the lock state, the
as shown in Fig. 8. There are five major blocks in the DCO should be oscillating at 112.8MHz. The output is
model: integer phase comparator, TDC as fractional phase downconverted to baseband and the Fourier transform is
comparator, gain stage, - converter and DCO. The done to show the spectrum.
integer phase comparator is implemented as two counters, Fig. 9 and 10 show the spectrum of the DCO output, -
as introduced in section II. The TDC follows the exact  output, and the waveform of the integer control bit and
circuit in [1]. The metastability faced in the real circuit is fractional control bit of DCO. The settling time as shown is
not discussed here for system analysis. The summation of about 50μs. As can be seen in Fig. 9, the output spectrum of
the fractional and integer part of phase error passes through DCO shows a similar profile as that from the -
the gain stage, and in this case it is divided by =8. The converter, meaning the noise is shaped by the converter.
output from the gain stage is separated into integer and However, there are some harmonics shown in both
fractional part again. The integer part goes directly to spectrums, which can also be improved by adopting or
control the output frequency of DCO. The fractional part is improving the converter structure. Fig. 10 shows the output
first limited to resolution of 0.1, and then goes to the - waveform of the integer control bit, fractional control bit
converter. The resolution limiter is necessary to keep the before and after the 1/10 resolution limiter. As can be seen,
whole system in lock status, and is related to the TDC the integer part settles at 12 in the end. Afterwards, the
resolution, and thus the resolution of tuning frequency. The fractional part settles at 0.8.

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 FCW=112.8
Integer
Phase Detector

Vector Scope
Gain Stage + DCO
1/α

D Flip-Flop Fractional
Phase Detector ¦Δ
(TDC)
/4
Fref
Figure 8. Time-domain model of ADPLL.

0
Fvco is 112.8MHz
Normalized Amplitude, dB

-50

-100

VCO output spectrum

Fcen=113MHz Sigma delta output spectrum

-150

Figure 9. Output spectrum of DCO and - converter in ADPLL model in Fig. 8.

REFERENCES
Fractional input of sigma-delta
[1] R. B. Staszewski and P. T. Balsara, “All-Digital Frequency
Synthesizer in Deep-Submicron CMOS” Wiley-Interscience
[2] J. Zhuang, Q. Du and T. Kwasniewski., “Event-Driven Modeling
and Simulation of an Digital PLL,” Proceeding of 2006 IEEE
Fractional part of the phase difference International Behavioral Modelling and Simulation Workship, Sep
2006, pp 67-72.
[3] M. H. Perrott, M. D. Trott and C. G. Sodini., “A Modeling
Approach for - Fractional-N Frequency Synthesizers Allowing
Integer control bits of VCO
Straightfoward Noise Analysis” IEEE JSSC, vol 37, Aug. 2002, pp.
1028–1038.

Figure 10. Output waveform of ADPLL model in Fig. 8.

IV. CONCLUSION
This paper introduced the modeling of ADPLL in
simulink, including one model at system level for LTI
analysis, and one at block level for time-domain analysis.
Simulations are done in both cases, to observe the setting
time and phase-lock process.

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