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SM2TDC2

This document contains 10 exercises related to designing combinational logic circuits using logic gates. The exercises involve implementing logic functions with NAND and NOR gates, designing circuits for functions, comparators, decoders, multiplexers, and parity checkers.

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0% found this document useful (0 votes)
39 views2 pages

SM2TDC2

This document contains 10 exercises related to designing combinational logic circuits using logic gates. The exercises involve implementing logic functions with NAND and NOR gates, designing circuits for functions, comparators, decoders, multiplexers, and parity checkers.

Uploaded by

younes.taiwan01
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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University M’Hamed Bougara – BOUMERDES

Faculty of Science
Computer science department

Level : LMD year 1 Course: SM 2 Section: 2 Groups: 10 to 18


Chapter 2' series of exercises

EXO 1
Consider the following logical function:

F =A B C DEF
a- Implement the logigram of F using two-input NAND gates.
b- Implement the logigram of F using two-input NOR gates.
EXO 2
Given a combinational logic circuit having the following behavior:

A + B fi C = 0 and D = 0
A B if C = 0 and D = 1
F(A,B,C,D) =
A B if C = 1 and D = 0
A B if C = 1 and D = 1
Use NAND and NOT logic gates to implement the corresponding circuit.

EXO 3
Consider the following logical function:

S = (A0 B0) (A1 B1) (A2 B2)


a- Give the logical circuit of S
b- Deduce the role (Function) of this circuit
c- Give the overall synoptic diagram of the circuit

EXO 4
You are asked to design a combinatorial logic circuit which must express the result of a vote by a
jury of four members who must vote on each decision to be taken during its meetings.
Each member has at his disposal a switch to be set to 1 for a YES vote and 0 for a NO vote.
Knowing that the jury is made up of a president P and three members M1, M2 and M3; the
decisions are taken by majority and the president's vote counts twice when there is equality.
Use only NAND logic gates to implement this circuit.
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EXO 5
Use two Half Adders (HA) to implement a Full Adder (FA).

EXO 6
Design a comparator of two two-bit-binary numbers A=A1A0 and B=B1B0 with three outputs: S1 for
A>B, S2 for A=B, and S3 for A<B.

EXO 7
Design a combinational logic circuit that has BCD inputs and a seven-segment display (a,b,c,d,e,f,g)
that displays the input value.

EXO 8
Use a MUX and a DeMux to design a serial transmission system between two remote computers
based on the ASCII transmission format (7 bits for information, 1 parity bit, 1 start bit, and 1 stop
bit).

EXO 9
Design a combinational logic circuit allowing the parity bit to be inserted before transmitting a
message and a circuit which detects parity upon reception of the message in a serial transmission
system.
Consider two cases:
a-The system communicates in even parity mode.
b-The system communicates in odd parity mode.

EXO10
Consider a combinational logic circuit having two inputs A and B and two outputs S1 andS2.

S1 = A AB B AB

S2 = AB
a- Give the corresponding circuit
b- Deduce the role (function) of this circuit

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