GATE-2023

Electronics Engineering

Analog Electronics
Chapterwise & Topicwise

Contents
S.No. Topic Page No.

1. Operational Amplifiers ...................................................................................................................... 1-53

2. Diodes Applications ........................................................................................................................ 54-82

3. BJT Analysis ..................................................................................................................................... 83-123

4. FET and MOSFET Analysis .......................................................................................................... 124-141

5. Frequency Response Amplifiers ............................................................................................ 142-145

6. Feedback Amplifiers .................................................................................................................. 146-150

7. Oscillator Circuits ........................................................................................................................ 151-165

 1 Operational Amplifiers

ELECTRO NICS EN GINEERIN G R2

(a) For Vi > 0, Vo = Vi
(GATE Previous Years Solved Papers) R1
(b) For Vi > 0, Vo = 0
Q.1 In figure shown below, if the CMRR of the
R2
operational amplifier is 60 dB, then the (c) For Vi < 0, Vo = Vi
R1
magnitude of the output voltage is
(d) For Vi < 0, Vo = 0
100 k
[EC-1989 : 2 Marks]
+ R R 1k
2V – Q.4 The op-amp of figure shown below has a very
– +
+ Vo
poor open-loop voltage gain of 45 but is
1k – otherwise ideal. The gain of the amplifier equals
R R 100 k
8k

2k
[EC-1987 : 2 Marks] –
Vout
+
Q.2 The op-amp shown in figure below is ideal, Vin

R = L /C . The phase angle between Vo and (a) 5 (b) 20

(c) 4 (d) 4.5
Vi, at = 1/ LC . [EC-1990 : 2 Marks]
L R
Q.5 The CMRR of the differential amplifier of the
R C figure shown below is equal to
Vi –
Vo 90 k
+
1k
V1 –
Vout
V2 +
(a) (b)
2 1k
3 100 k
(c) (d) 2
2
[EC-1988 : 2 Marks]
(a) (b) 0
Q.3 Refer to figure shown below:
(c) 1000 (d) 1800
R2
[EC-1990 : 2 Marks]
Vo
Q.6 If the input to the circuit of figure is a since wave
R1
the output will be
–
+ + –
Vi Input
+ Output
–
 2 Electronics Engineering Analog Electronics

(a) a half wave rectified sine wave. Q.10 For the ideal op-amp circuit of figure. Determine
(b) a full wave rectified sine wave. the output voltage Vo .
(c) a triangular wave.
(d) a square wave. 100 99
[EC-1990 : 2 Marks]
–
Q.7 An op-amp has an offset voltage of 1 mV and is 10 +
0
ideal in all other respects. If this op-amp is used
4V 0 Vo
in the circuit shown in figure. The output voltage 10
will be (select the nearest value).
1k
[EC-1993 : 2 Marks]
1k
– Q.11 The frequency compensation is used in op-amps
Vo
+ to increase its ______ .
[EC-1994 : 1 Mark]

Q.12 In the given circuit figure, if the voltage inputs

(a) 1 mV (b) 1 V
V– and V+ are to be amplified by the same
(c) ±1 V (d) 0 V
amplification factor, the value of ‘R’ should be
[EC-1992 : 2 Marks]
22 k
Q.8 The circuit of figure uses on ideal op-amp for
small positive values of Vin, the circuit works as 10 k
V– –
Vo
V+ +
Va
R 15 k
Vin – R=? Ideal op-amp
Vo
+

[EC-1995 : 1 Mark]
(a) a half wave rectifier
Q.13 An op-amp is used as a zero-crossing detector.
(b) a differentiator
If maximum output available from the op-amp
(c) a logarithmic amplifier
is ±12 Vp-p and the slew rate of the op-amp is
(d) an exponential amplifier 12 V/µ sec then the maximum frequency of the
[EC-1992 : 2 Marks] input signal that can be applied without causing
Q.9 Assume that the operational amplifier in figure a reduction in the P – P output is
is ideal the current I through the 1 k resistor is [EC-1995 : 1 Mark]
______ . Q.14 The circuit shown in the figure is that of
2k
Vin –
Vo
1k +
–
+ 1k
2 mA
2k R1
R2

[EC-1992 : 2 Marks]
 GATE Previous Years Solved Paper 3

(a) a non-inverting amplifiers (a) –1 V (b) 2 V

(b) an inverting amplifier (c) +1 V (d) +15 V
(c) an oscillator [EC-2000 : 1 Mark]
(d) a schmitt trigger
Q.19 If the op-amp in the figure, is ideal, then Vo is
[EC-1996 : 1 Mark]
C
Q.15 The output voltage Vo of the circuit shown in
V1 sin t C
the figure is
–
10 k Vo
+
V2 sin t C
5k
–
Vo
+
2V (a) Zero (b) (V1 – V2) sin t
(c) –(V1 + V2) sin t (d) (V1 + V2) sin t
100 k
[EC-2000 : 1 Mark]
10 k

Q.20 Assume that the op-amp of the figure is ideal. If

Vi is a triangular wave, then Vo will be
(a) –4 V (b) 6 V
R
(c) 5 V (d) –5.5 V
[EC-1997 : 2 Marks] C
Vi –
Q.16 One input terminal of high gain comparator Vo
+
circuit is connected to ground and a sinusoidal
voltage is applied to the other input. The output
of comparator will be (a) square wave (b) triangular wave
(a) a sinusoid (c) parabolic wave (d) sine wave
(b) a full rectified sinusoid
[EC-2000 : 1 Mark]
(c) a half rectified sinusoid
(d) a square wave Q.21 The most commonly used amplifier in sample
and hold circuits is
[EC-1998 : 1 Mark]
(a) a unity gain inverting amplifier.
Q.17 The first dominant pole encountered in the
(b) a unity gain non-inverting amplifier.
frequency response of a compensated op-amp
(c) an inverting amplifier with a gain of 10.
is approximately at
(d) an inverting amplifier with a gain of 100.
(a) 5 Hz (b) 10 kHz
[EC-2000 : 1 Mark]
(c) 1 MHz (d) 100 MHz
[EC-1999 : 1 Mark] Q.22 If the op-amp in the figure has an input offset
voltage of 5 mV and an open-loop voltage gain
Q.18 In the circuit of the figure, Vo is
of 10,000, then Vo will be
+15 V
+15 V
–
Vo –
+1 V + Vo
R +
–15 V
–15 V

R
 4 Electronics Engineering Analog Electronics

(a) 0 V (b) 5 mV Q.26 A 741-type op-amp has a gain bandwidth

(c) +15 V or –15 V (d) +50 V or –50 V product of 1 MHz. A non-inverting amplifier
[EC-2000 : 2 Marks] using this op-amp and having a voltage gain of
20 dB will exhibit a –3 dB bandwidth of
Q.23 The ideal op-amp has the following
(a) 50 kHz (b) 100 kHz
characteristics:
(a) Ri = , A = , R0 = 0 1000 1000
(c) kHz (d) kHz
17 7.07
(b) Ri = 0, A = , R0 = 0
(c) Ri = , A = , R0 = [EC-2002 : 1 Mark]
(a) Ri = 0, A = , R0 = Q.27 An amplifier using an op-amp with a slew-rate
[EC-2001 : 1 Mark] SR = 1 V/µsec has a gain of 40 dB. If this
amplifier has to faithfully amplify sinusoidal
Q.24 The inverting op-amp shown in the figure has
signals from dc to 20 kHz without introducing
an open-loop gain of 100. The closed-loop gain
any slew-rate induced distortion, then the input
Vo/Vs is
signal level must not exceed.
R2 = 10 k (a) 795 mV (b) 395 mV
(c) 79.5 mV (d) 39.5 mV
R1 = 1 k
–
[EC-2002 : 2 Marks]
Vs Vi +
– + Vo Q.28 If the input to the ideal comparator shown in
the figure is a sinusoidal signal of 8 V (peak to
peak) without any DC component, then the
(a) –8 (b) –9 output of the comparator has a duty cycle of
(c) –10 (d) –11
Vref = 2 V –
[EC-2001 : 2 Marks]
Input + Output
Q.25 In the figure assume the op-amps to be ideal.
The output Vo of the circuit is, 1 1
(a) (b)
10 mH 2 3
10 µF

1 1
10 k (c) (d)
Vs – 100 6 12
1 –
Vs = 10 cos(100t) + 2 3
+
[EC-2003 : 1 Mark]
Vo

Q.29 If the differential voltage gain and the common

mode voltage gain of a differential amplifier are
(a) 10 cos(100t) 48 dB and 2 dB respectively, then its common
t mode rejection ratio is
(b) 10 cos(100 ) d
(a) 23 dB (b) 25 dB
0
(c) 46 dB (d) 50 dB
t
4 [EC-2003 : 1 Mark]
(c) 10 cos(100 ) d
0
Q.30 If the op-amp in the figure is ideal, the output
4 d
(d) 10 cos(100t ) voltage Vout will be equal to
dt
[EC-2001 : 2 Marks]
 GATE Previous Years Solved Paper 5

5k R1 R1
Vs
1k
2V –
Vo –
3V + R2
1k +
8k

R2
iL RL

(a) 1 V (b) 6 V
(c) 14 V (d) 17 V
[EC-2003 : 2 Marks] vs vs
(a) (b)
R2 R2
Q.31 Three identical amplifiers with each one having
vs vs
a voltage gain of 50, input resistance of 1 k (c) (d)
RL R1
and output resistance of 250 , are cascaded.
The open-circuit voltage gain of the combined [EC-2004 : 2 Marks]
amplifier is Q.35 The input resistance Ri of the amplifier shown
(a) 49 dB (b) 51 dB in the figure is
(c) 98 dB (d) 102 dB
30 k
[EC-2003 : 2 Marks]

Q.32 An ideal op-amp is an ideal 10 k

(a) voltage controlled current source. –
+
(b) voltage controlled voltage source. Vs
(c) current controlled current source. Ideal operational amplifier

(d) current controlled voltage source. Ri

[EC-2004 : 1 Mark]
30
Q.33 The circuit in the figure is (a) k (b) 10 k
4
(c) 40 k (d) infinite
– [EC-2005 : 1 Mark]
R R Vo
Vi + Q.36 The voltage e0 indicated in the figure has been
measured by an ideal voltmeter. Which of the
following can be calculated?

1M
(a) low-pass filter
(b) high-pass filter
(c) band-pass filter –
eo
+
(d) band-reject filter
[EC-2004 : 1 Mark] 1M

Q.34 In the op-amp circuit given in the figure, the

load current iL is
 6 Electronics Engineering Analog Electronics

(a) Bias current of the inverting input only. Q.39 For the op-amp circuit shown in the figure, Vo is
(b) Bias current of the inverting and non- 2k
inverting inputs only.
(c) Input offset current only. 1k
–
(d) Both the bias currents and the input offset 1V Vo
+
current.
1k
[EC-2005 : 2 Marks] 1k

Q.37 The op-amp circuit shown in the figure is a filter.

The type of filter and its cut-off frequency are
respectively (a) –2 V (b) –1 V
(c) –0.5 V (d) 0.5 V
10 k
[EC-2007 : 2 Marks]

10 k Q.40 In the op-amp circuit shown, assume that the

– diode current follows the equation
Vo
+ I = Is exp(V/VT). For Vi = 2 V, Vo = V01 and for
Vi 1 µF Vi = 4 V, Vo = V02. The relationship between V01
1k
and V02 is

(a) high pass, 1000 rad/sec. 2k

Vi –
(b) low pass, 1000 rad/sec. Vo
+
(c) high pass, 10000 rad/sec.
(d) low pass, 10000 rad/sec.
[EC-2005 : 2 Marks] (a) V02 = 2 V01 (b) V02 = e2 V01

Q.38 For the circuit shown in the following figure, (c) V02 = V01 ln 2 (d) V01 – V02 = VT ln2
the capacitor C is initially uncharged. At t = 0, [EC-2007 : 2 Marks]
the switch S is closed. The voltage VC across the Linked Answer Questions (41 and 42):
capacitor at t = 1 millisecond is
Consider the op-amp circuit shown in the figure.
S R1
C = 1 µF
– +
VC R1
1k –
– Vi Vo
+
+ R C
10 V

Q.41 The transfer function Vo(s)/Vi(s) is

In the figure shown above, the op-amp is
supplied with ±15 V. 1 sRC 1 + sRC
(a) (b)
1 + sRC 1 sRC
(a) 0 Volt (b) 6.3 Volts
1 1
(c) 9.45 Volts (d) 10 Volts (c) (d)
1 sRC 1 + sRC
[EC-2006 : 2 Marks]
[EC-2007 : 2 Marks]
 GATE Previous Years Solved Paper 7

Q.42 If Vi = V1 sin( t) and Vo = V2 sin( t + ), then the 10 V

minimum and maximum values of (in radians)
are respectively 5k

(a) and (b) 0 and

2 2 2 V –

and 0
+
(c) – and 0 (d)
2
1.4 k 5V
[EC-2007 : 2 Marks]

Q.43 Consider the following circuit using an ideal

op-amp. The I-V characteristics of the diode is
(a) Positive feedback, V = 10 V
described by the relation I = I o ( e v / vT 1) (b) Positive feedback, V = 0 V
where VT = 25 mV, Io = 1 µA and V is the voltage (c) Negative feedback, V = 5 V
across the diode (taken as positive for foward (d) Negative feedback, V = 2 V
bias). [EC-2009 : 2 Marks]
D 4k
Q.46 Assuming the op-amp to be ideal, the voltage
gain of the amplifier shown below is
100 k
Vi = –1 V –
Vo R1
+ – Vo
+
R2
For an input voltage Vi = –1 V, the output voltage Vi
Vo is
(a) 0 V (b) 0.1 V R3

(c) 0.7 V (d) 1.1 V

[EC-2008 : 2 Marks]
R2 R3
Q.44 The op-amp circuit shown below represents a (a) (b)
R1 R1
C
R2 R3 R2 + R3
(c) (d)
R1 R1
R1 R2
L [EC-2010 : 1 Mark]
Vi –
Vo
+ Q.47 The transfer characteristic for the precision
rectifier circuit shown below is (assume ideal
op-amp and practical diodes).
(a) high-pass filter (b) low-pass filter
+20 V
(c) band-pass filter (d) band-reject filter R
[EC-2008 : 2 Marks]

Q.45 In the circuit shown below, the op-amp is ideal, 4R

D2
the transistor has VBE = 0.6 V and = 150. Decide VI –
R Vo
whether the feedback in the circuit is positive or + D1
negative and determine the voltage V at the
output of the op-amp.
 8 Electronics Engineering Analog Electronics

Q.49 The circuit shown is a

Vo

10 R2

(a)
C R1 +5 V +
+ – Output
VI Input
–10 –5 0 + –
–
–5 V
Vo

(a) low-pass filter with

(b) 5
1
f 3-dB = rad/sec
VI ( R1 + R2 ) C
–10 –5 0
(b) high-pass filter with
Vo 1
f 3-dB = rad/sec
R1C
(c) 5 (c) low-pass filter with
1
+5
VI f 3-dB = rad/sec
0 R1C
(d) high-pass filter with
Vo
1
10
f 3-dB = rad/sec
( R1 + R2 ) C
(d)
[EC-2012 : 2 Marks]
VI
0 +5 Q.50 In the circuit shown below what is the output
voltage (Vout) if a silicon transistor Q and an
[EC-2010 : 2 Marks] ideal op-amp are used?
Q.48 The circuit below implement a filter between the
input current ii and output voltage vo. Assume
that the op-amp is ideal. The filter implemented Q
+15 V
is a 1k
–
L1 Vo
+
5V
–15 V
I1 R1
–
+
(a) –15 V (b) –0.7 V
+ vo (c) +0.7 V (d) +15 V
–
[EC-2013 : 1 Mark]

(a) low-pass filter (b) band-pass filter Q.51 In the circuit shown below the op-amps are
ideal. Then Vout (in Volts) is
(c) band-stop filter (d) high-pass filter
[EC-2011 : 1 Mark]
 GATE Previous Years Solved Paper 9

Q.54 In the circuit shown, the op-amp has finite input

1k 1k impedance, infinite voltage gain and zero input
–2 V
+15 V offset voltage. The output voltage Vout is
+15 V
– R2
–
+ Vo
+ R1 I1
1k
–15 V –
–15 V Vo
+1 V +
I2
1k
1k

(a) –I2(R1 + R2) (b) I2R2

(a) 4 (b) 6 (c) I1R2 (d) –I1(R1 + R2)
(c) 8 (d) 10 [EC-2014 : 2 Marks]
[EC-2013 : 2 Marks] Q.55 In the differential amplifier shown in the figure,
Q.52 In the low-pass filter shown in the figure, for a the magnitudes of the common mode and
cut-off frequency of 5 kHz, the value of R2 (in k ) di fferenti al mode gai ns are A cm and A d ,
is ______ . respectively. If the resistance RE is increased,
then
R2

VCC
C
RC RC
10 nF
1k
Vi – Vo
R1 Vo + –
+
+

Vi
[EC-2014 : 1 Mark]
–
Q.53 In the voltage regulator circuit shown in the
figure, the op-amp is ideal. The BJT has
RE Io
VBE = 0.7 V and = 100, and the Zener voltage is
4.7 V. For a regulated output of 9 V, the value of
R (in ) is _______ . –VE

Vi = 12 V Vo = 9 V (a) Acm increase

(b) common mode rejection ratio increases
1k 1k (c) Ad increase
+
(d) common mode rejection ratio decreases
–
[EC-2014 : 1 Mark]

Vz = 4.7 V R Q.56 Assuming that the op-amp in the circuit shown

is ideal, Vo is given by

[EC-2014 : 2 Marks]
 10 Electronics Engineering Analog Electronics

Q.59 In the circuit shown, Vo = V0A for switch SW in

3R
position A and Vo = V0B for SW in position B.
Assume that the op-amp is deal. The value of
R V0B/V0A is _______ .
V1 –
Vo
V2 + 1k

2R R 1k
5V –

1k Vo
A
B +
5 5 SW
1k
(a) V1 3V2 (b) 2 V1 V2
2 2 1k
1V
3 7 11
(c) V1 + V2 (d) 3V1 + V2
2 2 2
[EC-2015 : 1 Mark]
[EC-2014 : 2 Marks]
Q.60 In the bistable circuit shown, the ideal op-amp
Q.57 The circuit shown represents
has saturation levels of ±5 V. The value of R1
C2 +12 V
(in k ) that gives a hysteresis width of 500 mV
vi –
vo is ______ .
R2 +
–12 V R2 = 20 k
R1
–2 V
C1 R1
+
Vo
(a) a bandpass filter Vi
–
(b) a voltage controlled oscillator
(c) an amplitude modulator
(d) a monostable multivibrator [EC-2015 : 1 Mark]
[EC-2014 : 1 Mark]
Q.61 For the voltage regulator circuit shown, the input
Q.58 In the circuit shown, assume that the op-amp is voltage (Vin) is 20 V ± 20% and the regulated
ideal. The bridge output voltage Vo (in mV) for output voltage (Vout) is 10 V. Assume the op-amp
= 0.05 is ______ . to be ideal. For a load RL drawing 200 mA, the
maximum power dissipation in Q1 (in Watts) is
1V
100 + _______ .
–
250(1 + ) 250(1 – )
Vi Q1 Vo
– +
Vo 4V
Vref + R1 RL
250(1 – ) 250(1 + ) –

100
50
R2 = 10 k

[EC-2015 : 2 Marks]
[EC-2015 : 2 Marks]
 GATE Previous Years Solved Paper 11

Q.62 Assuming that the op-amp in the circuit shown The load current Io through RL is
below is deal, the output voltage Vo (in Volts) is + 1 Vref
(a) I o =
______ . R
2k
Vref
(b) I o =
+12 V +1 R
1k
– + 1 Vref
Vo (c) I o =
+ 2R

1V –12 V Vref
(d) I o =
+ 1 2R
[EC-2015 : 2 Marks]
[EC-2016 : 1 Mark]
Q.63 In the circuit shown using an ideal op-amp, the
3-dB cut-off frequency (in Hz) is _____ . Q.66 The following signal Vi of peak voltage 8 V
applied to the non-inverting terminal of an ideal
vi +
10 k 10 k vo op-amp. The transistor has VBE = 0.7 V, = 100,
–
0.1 µF VLED = 1.5 V, VCC = 10 V and –VCC = –10 V.
10 k 10 k
10 V 10 V

100
[EC-2015 : 1 Mark] 8k

Q.64 In the circuit shown, assume that the op-amp is +VCC

LED
ideal. If the gain (Vo/Vin) is –12, the value of R –

(in k ) is ______ . + 15 k
2k Vi
10 k 10 k –VCC

10 k Vi
Vin –
Vo
+ 6V
4V
2V
[EC-2015 : 2 Marks] t
–2 V
Q.65 Consider the constant current source shown in
–4 V
the figure below. Let represent the current gain
–6 V
of the transistor.
+V CC The number of times the LED glows is _____ .
[EC-2016 : 1 Mark]
R
Vref Q.67 An ideal op-amp has voltage sources, V1, V3,
V5, ..... VN – 1 connected to the non-inverting input
–
and V2, V4, V6, ....., VN connected to the inverting
+ R2 input as shown in the figure below
(+VCC = 15 Volt, –VCC = –15 Volt). The voltages
R1 RL V1, V2, V3, V4, V5, V6, .... are 1, –1/2, 1/3, –1/4,
1/5, –1/6, .... Volt, respectively. As N approaches
infinity, the output voltage (in Volt) is _____ .
 12 Electronics Engineering Analog Electronics

10 k
The time t = t1 (in seconds) at which Vo changes
V2 state is ______ .
10 k 10 k
V4 [EC-2016 : 2 Marks]
10 k +VCC
VN –
Q.70 An op-amp has a finite open-loop voltage gain
1k Vo of 100. Its input offset voltage Vios (= +5 mV) is
V1 +
–VCC modeled as shown in the circuit below. The
1k
V3 amplifier is ideal in all other respects. Vinput is
1k 10 k 25 mV.
VN – 1
1k 15 k

[EC-2016 : 2 Marks]
–
Q.68 A p-i-n photodiode of responsivity 0.8 A/W is +
connected to the inverting input of an ideal Ao = 100
V ios = 5 mV
op-amp as shown in the figure, +VCC = 15 V,
–VCC = –15 V, Load resistor RL = 10 k . If 10 µW
V input
of power is incident on the photodiode, then
the value of the photocurrent (in µA) through
the load is ______ . The output voltage (in millivolts) is ______ .
[EC-2016 : 2 Marks]
1M
Q.71 For the circuit shown in the figure, R1 = R2 =
R3 = 1 , L = 1 µH and C = 1 µF. If the input
+VCC
Vin = cos(106 t), then the overall voltage gain
–
Vo (Vout/Vin) of the circuit is ______ .
+
R1
–VCC 10 k R3
1M
L
–
+VCC –
+ R2 C Vout
[EC-2016 : 2 Marks] +
Vin
Q.69 In the op-amp circuit shown, the Zener diode
Z1 and Z2 clamp the output voltage Vo to +5 V or
–5 V. The switch ‘S’ is initially closed and is [EC-2016 : 2 Marks]
opened at time t = 0.
Q.72 For the operational amplifier circuit shown, the
+10 V output saturation voltages are ±15 V. The upper
and lower threshold voltages for the circuit are,
S
10 µ F respectively
t=0 +10 V
+ –
– 470 Vout
Vo Vin +
+ – 10 k
Z1
–10 V
10 k 5k
4k
1k Z2
3V
–10 V
0V 0V
 GATE Previous Years Solved Paper 13

(a) +5 V and –5 V (b) +7 V and –3 V Q.75 In the circuit shown below, the op-amp is ideal
(c) +3 V and –7 V (d) +3 V and –3 V and Zener voltage of the diode is 2.5 Volts. At
[EC-2017 : 1 Mark] the input, unit step voltage is applied i.e.
VIN(t) = u(t) Volts. Also at t = 0, the voltage across
Q.73 The amplifier circuit shown in the figure is each of the capacitors is zero.
implemented using a compensated operational
1 µF
amplifier (op-amp), and has an open-loop
voltage gain, A0 = 105 V/V and an open-loop
1k 1 µF
cut-off frequency, fc = 8 Hz. The voltage gain of 1V –
the amplifier at 15 kHz, (in V/V), is _____ . vIN(t )
0V + vOUT(t)
t=0
R2 = 79 k

R2 = 1 k
The time t, in milliseconds, at which the output
– voltage vOUT crosses –10 V is
Vo
+ (a) 2.5 (b) 5

Vi (c) 7.5 (d) 10

[EC-2018 : 1 Mark]

Q.76 An op-amp based circuit is implemented as

[EC-2017 : 2 Marks]
shown below.
Q.74 In the voltage reference circuit shown in the 31 k
figure, the op-amp is ideal and the transistors
Q1, Q2, ...... Q32 are identical in all respects and +15 V
1k
have infinitely large values of common-emitter –
A
current gain ( ). The collector current (IC) of the + + +
1V
transistors is related to their base-emitter voltage Vo
– –
(VBE) by the relation IC = IS exp(VBE/VT), where –15 V

IS is the saturation current. Assume that the In the above circuit, assume the op-amp to be
voltage VP shown in the figure is 0.7 V and the ideal. The voltage (in volts correct to one decimal
thermal voltage VT = 26 mV. place) at node A, connected to the negative input
of the op-amp as indicated in the figure is ___ .
[EC-2018 : 2 Marks]
20 k
20 k +15 V
– Q.77 In the circuit shown below, all the components
+
V out are ideal. If Vi is +2 V, the current Io sourced by
–15 V the op-amp is ______ mA.
5k
1k
VP
+15 V
1k
Q1 Q2 Q3 Q32 – Io
Vi +
1k
–15 V
The output voltage Vout (in Volts) is _____ .
[EC-2017 : 2 Marks] [EC-2020 : 1 Mark]
 14 Electronics Engineering Analog Electronics

Q.78 The components in the circuit shown below are If Vout = 1 Volt for Vin = 0.1 Volt and Vout = 6 Volt
ideal. If the op-amp is in positive feedback and for Vin = 1 Volt, where Vout is measured across
the input voltage Vi is a sine wave of amplitude RL connected at the output of this op-amp, the
1 V, the output voltage Vo is value of RF/Rin is
1k (a) 3.285 (b) 3.825
(c) 5.555 (d) 2.860
1V 1k +5 V [EC-2021 : 1 Mark]
0 Vi –
–1 V Vo
+ Q.81 Consider the circuit with an ideal op-amp
–5 V shown in the figure.

R RF
(a) a square wave of 5 V amplitude.
(b) a inverted sine wave of 1 V amplitude.
R
(c) a non-inverted sine wave of 2 V amplitude.
+VCC
(d) a constant of either +5 or –5 V. Vin
Vref Vout
[EC-2020 : 1 Mark]

Q.79 The components in the circuit given below are –VCC

ideal. If R = 2 k and C = 1 µF, the –3 dB cut-off

frequency of the circuit (in Hz), is Assuming Vin << VCC and Vref << VCC ,
R
the condition at which Vout equals to zero is
C (a) Vin = 2 + Vref (b) Vin = 2Vref
R (c) Vin = Vref (d) Vin = 0.5Vref
Vi( j ) –
Vo( j ) [EC-2021 : 1 Mark]
+
2C 2R Q.82 An ideal op-amp circuit with a sinusoidal input
is shown in the figure. The 3-dB frequency is
the frequency at which the magnitude of the
(a) 34.46 (b) 79.58 voltage gain decreases by 3-dB from the
(c) 59.68 (d) 14.92 maximum value. Which of the options is/are
[EC-2020 : 2 Marks] correct?

Q.80 For the circuit with an ideal op-amp shown in 2k

the figure, Vref is fixed.

1 µF +15 V
1k
Rin RF
+
Vin +
Vo
– –15 V –
Vin
+12 V

R1 (a) The circuit is a low-pass filter.

Vout
(b) The circuit is a high-pass filter.
–12 V
(c) The 3-dB frequency is 1000 rad/sec.
Vref R2 RL = 100
1000
(d) The 3-dB frequency is rad/sec.
3
[EC-2022]
 GATE Previous Years Solved Paper 15

Q.83 For the following circuit with an ideal op-amp,

20log10(|Av|)
the difference between the maximum and the
minimum values of the capacitor voltage (VC) is 15

_______ . 12
9
R
6

VC +15 V 3
– +
0
C 1 2 3 4 log10( )

–12 V
(a) R = 3 k , C = 1 µF
R R R R (b) R = 1 k , C = 3 µF
(c) R = 4 k , C = 1 µF
(d) R = 3 k , C = 2 µF
D D
[EC-2022]
ID D
Q.85 Consider the circuit shown with an ideal
op-amp. The output voltage Vo is ______ V.
+ VD –
(Rounded off to two decimal places)
3R
20
ID(mA)

+15 V
10 R R R 2R

0 +
(V) 2R 2R 2R 2R 2R Vo
0 VD –15 V –

(a) 15 V (b) 27 V +1.6 V +1.6 V

(c) 13 V (d) 14 V [EC-2022]

[EC-2022]
ELECTRICAL EN GINEERIN G
Q.84 A circuit with an ideal op-amp is shown. The
(GATE Previous Years Solved Papers)
Bode plot for the magnitude (in dB) of the gain
transfer function (Av(j ) = Vout(j )/Vin(j ) of the Q.1 An ideal op-amp is used to make an inverting
circuit is also provide (here, is the angular amplifier. The two input terminals of the op-amp
frequency in rad/sec). The values of R and C are at the same potential because
are _______ . (a) the two input terminals are directly shorted
internally.
R
(b) the input impedance of the op-amp is
+15 V infinity.
1k
Vo (c) the open-loop gain of the op-amp is infinity.
+ (d) CMRR is infinity.
+
Vin 1k Vout
–12 V [EE-1992 : 1 Mark]
– C
–
Q.2 The circuit shown in figure is excited by the circuit
waveform shown. Sketch the waveform of the
output. Assume all the components are ideal.
 16 Electronics Engineering Analog Electronics

Vi (Volts) Q.6 A non-inverting op-amp amplifier is shown in

figure. The output voltage is

2R
R
–
0 0.5 1 2 3 t(sec)
–2 +
R
2 + sin100t
– R
Vo
Vi + VA D1 3
C D2 (a) sin 100t (b) 3 sin100t
2
(c) 2 sin100t (d) none of these
[EE-1996 : 1 Mark]
[EE-1992 : 2 Marks]
Q.7 A major advantage of active filters is that they
Q.3 Given figure, shows a non-inverting op-amp
can be realized without using
summer with V1 = 2 V and V2 = –1 V the output
voltage Vo = _______ . (a) op-amps (b) inductors
(c) resistors (d) capacitors
2R [EE-1997 : 1 Mark]
R
V
–
V
Vo Q.8 Match the following:
2V +
R Circuits:
–1 V VCC
R
R

[EE-1994 : 1 Mark] –
A. Vo
+
Q.4 The common mode voltage of a unity gain Vi
R
(voltage follower) op-amp buffer in terms of its
output voltage V is ______ .
[EE-1995 : 1 Mark]

Q.5 Let the magnitude of the gain in the inverting

op-amp circuit shown be x with switch S1 open.
When the switch is closed, the magnitude of –
B. Vo
gain becomes. +
Vi
R
S1

R R
R
Vi –
Vo
+
–
Vo
C. +
Vi
(a) x/2 (b) –x
(c) 2x (d) –2x
[EE-1996 : 1 Mark]
 GATE Previous Years Solved Paper 17

Functions: Q.12 For the circuit of figure with an ideal operational

P. High-pass filter amplifier, the maximum phase shift of the output
Q. Amplifier Vout with reference to the input Vin is
R. Comparator R1
S. Low-pass filter
[EE-1998 : 2 Marks] R
–
Vi Vo
Q.9 The feedback factor for the circuit shown in +
figure is R
C
100 k
–
+ Vo
+
Vs
(a) 0° (b) –90°
– 1k
90 k (c) +90° (d) ±180°
10 k
[EE-2003 : 1 Mark]

Q.13 Assuming the operational amplifier to be ideal,

9 9 the gain Vout/Vin for the circuit shown in figure
(a) (b)
100 10 is
1 1 1k 10 k
(c) (d)
9 10
[EE-2000 : 1 Mark] 1k

Q.10 The circuit shown in figure uses an ideal 1k

op-amp working with +5 V and –5 V power Vi –
Vo
supplies. The output voltage Vo is equal to +

1k

+5 V
(a) –1 (b) –20
–
Vo (c) –100 (d) –120
a + Va = 0
1 mA [EE-2003-04 : 2 Marks]
–5 V

Q.14 The input resistance RIN (= Vx/Ix) of the circuit

(a) +5 V (b) –5 V in figure is
(c) +1 V (d) –1 V R1 = 10 k R2 = 100 k

[EE-2000 : 1 Mark]

Q.11 An op-amp having a slew rate of 62.8 V/µsec is –

connected in a voltage follower configuration. Vy
+
If the maximum amplitude of the input
sinusoidal is 10 Volts, then the minimum
Vx
frequency at which the slew rate limited Ix R3 = 1 M
distortion would set in the output is
(a) 1 MHz (b) 6.28 MHz (a) +100 k (b) –100 k
(c) +1 M (d) –1 M
(c) 10 MHz (d) 62.8 MHz
[EE-2004 : 2 Marks]
[EE-2001 : 2 Marks]
 18 Electronics Engineering Analog Electronics

Q.15 Consider the inverting amplifier, using an ideal Vo

operational amplifier shown in the figure. The
designer wishes to realize the input resistance (d)
t
seen by the small signal source to be as large as
possible, while keeping the voltage gain
between –10 and –25. The upper limit on RF is [EE-2005 : 2 Marks]
1 M . The value of R1 should be Q.17 For a given sinusoidal input voltage, the voltage
waveform at point P of the clamper circuit
R1 RF
shown in figure will be
Vi –
Vo
+
C +12 V
–
(a) Infinity (b) 1 M –
RL
(c) 100 k (d) 40 k Vin + P
–12 V
[EE-2005 : 2 Marks] +

Q.16 In the given figure, if the input is a sinusoidal

signal, the output will appear as shown in
Vin
Vin

t
t

R +V
–

+ (a)
+
–V
Vi
RL Vo
R

(b)
Vo

(a)
t

Vo 12 V
(c)
–0.7 V
(b) t

Vo
(d) 0.7 V
(c) –12 V
t

[EE-2006 : 1 Mark]
 GATE Previous Years Solved Paper 19

Q.18 A relaxation oscillator is made using op-amp Q.19 The circuit shown in the figure is
as shown in figure. The supply voltages of the
op-amp are ±12 V. The voltage waveform at point R1
P will be +
+ R2 –
V Load
R1 –

R2 r

C
– rV
+
(a) a voltage source with voltage
R1 R2
2k
P r R2
(b) a voltage source with voltage V
R1
10 k 10 k
r R2 V
(c) a current source with current
R1 + R2 r

R2 V
(d) a current source with current
R1 + R2 r
[EE-2007 : 1 Mark]
6
(a) Q.20 The switch ‘S’ in the circuit of the figure is
initially closed, it is opened at time, t = 0. You
–10
may neglect the Zener diode forward voltage
drops. What is the behaviour of Vout for t > 0?

10 +10 V
+10 V
1k
(b)
–
6 Vo
+
S +10 k 5.0 V
0.01 µF

–10 V

100 k 5.0 V
6
(c) –10 V

(a) It makes a transition from –5 V to +5 V at

–10
t = 12.98 µs.
(b) It makes a transition from –5 V to +5 V at
t = 2.57 µs.
10
(c) It makes a transition from +5 V to –5 V at
(d) t = 12.98 µs.
6 (d) It makes a transition from +5 V to –5 V at
t = 2.57 µs.
[EE-2006 : 2 Marks] [EE-2007 : 2 Marks]
 20 Electronics Engineering Analog Electronics

Q.21 The block diagrams of two of half wave rectifiers Statement for Linked Answer Questions (22 and 23):
are shown in the figure with the transfer A general filter circuit is shown in the figure:
characteristics of the rectifiers.
R2
It is desired to make full wave rectifier using
above two half-wave rectifiers. The resultant
circuit will be
R1 C
P Q
Vi –
Vo Vo VA Vo
Vin Vo Vin Vo +
Vin
0 R3
Vin
0 R4

It is desired to make full wave rectifiers using

above two-half-wave rectifiers. The resultants
circuit will be
Q.22 If R1 = R2 = RA and R3 = R4 = RB, the circuit acts
R as a
P R (a) all pass filter (b) band pass filter
(a) Vi –
Vo (c) high pass filter (d) low pass filter
+
Q R [EE-2008 : 2 Marks]

Q.23 The output of the filter is (Q.22) is given to the

R circuit shown in figure.
RA/2
P R
(b) Vi –
Vo
+
Q R Vi C Vo
R

The gain vs frequency characteristic of the

R output (Vo) will be

Gain
Q R
(c) Vi –
Vo
+ (a)
P R
R

R R Gain

– (b)
P R Vo
(d) Vi +

Q R

[EE-2008 : 2 Marks]
 GATE Previous Years Solved Paper 21

(a) 10 mA leading by 90°

Gain
(b) 20 mA leading by 90°
(c) 10 mA leading by 90°
(c) (d) 10 mA lagging by 90°
[EE-2009 : 2 Marks]

Q.26 Transformer and emitter follower can both be

used for impedance matching at the output of
Gain
an audio amplifier. The basic relationship
between the input power Pin and output power
Pout in both the cases is
(d)
(a) Pin = Pout for both transformer and emitter
follower.
(b) Pin > Pout for both transformer and emitter
[EE-2008 : 2 Marks] follower.
(c) Pin < Pout for both transformer and Pin = Pout
Q.24 The nature of feedback in the op-amp circuit
for emitter follower.
shown is
(d) Pin = Pout for both transformer and Pin < Pout
for emitter follower. [EE-2009 : 2 Marks]
1k +6 V
2k
– Q.27 An ideal op-amp circuit and its input waveform
V out
+ are shown in the figures. The output waveform
–6 V of this circuit will be
Vin
Vin

3
2
(c) current-current feedback 1
t4 t5 t6
(b) voltage-voltage feedback V0
t1 t2 t3
t
–1
(c) current-voltage feedback
–2
(d) voltage-current feedback –3

[EE-2009 : 1 Mark]
1k 6V
Q.25 The following circuit has R = 10 k , C = 10 µF. Vi –
Vo
The input voltage is a sinusoid at 50 Hz with +
2k
an rms value of 10 V. Under ideal conditions, –3 V
the current is from the source is
1k
R

10 k
is
– Vo
op-amp
6
Vs(rms) = 10 V, +
50 Hz
10 k (a)
t3 t6
R 0 t
C 10 µF
–3
 22 Electronics Engineering Analog Electronics

Vo (a) an all-pass filter

(b) an all-stop filter
6
(c) a band-stop (band-reject) filter
(d) a band-pass filter
(b)
t3 t6 [EE-2011 : 1 Mark]
0 t

Q.30 For the circuit shown below.

–3
R

Vo
R +12 V
– +12 V
6 Vi –
+
R –12 V +
(c) R –12 V
Vo
t6
0 t
t2 t4
R R
–3

Vo
Vo
+12 V
6

+6 V
(d) (a) Vi
–6 V
0 t
t2 t4 t6

–3
–12 V

[EE-2009 : 2 Marks]
Vo
Q.28 Given that the op-amp is ideal, the output voltage
Vo is +12 V

2R
+6 V
(b) Vi
–6 V
+10 V
R
–
Vout –12 V
+

–10 V
+2 V
Vo

+12 V
(a) 4 V (b) 6 V
(c) 7.5 V (d) 12.12 V
[EE-2010 : 1 Mark] (c) Vi
–6 V +6 V
Q.29 A low-pass filter with a cut-off frequency of 30 Hz
is cascaded with a high-pass filter with a cut-off
frequency of 20 Hz. The resultant system of –12 V

filters will functions as

 GATE Previous Years Solved Paper 23

Q.33 In the circuit shown below the op-amps are

Vo
ideal. Then Vout (in Volts), is
+12 V
1k 1k

2V
+15 V
– +15 V
(d) Vi –
–6 V +6 V +
+ Vout
–15 V
1k –15 V

–12 V +1 V
1k
1k

[EE-2011 : 1 Mark]

Q.31 The circuit shown is a (a) 4 (b) 6

R2 (c) 8 (d) 10
[EE-2013 : 2 Marks]

C R1 +5 V + Q.34 Given that the op-amps in the figure are ideal,

+ – Output the output voltage Vo, is
Input –
+
– V2 + R
–5 V
–
R R
1 –
(a) low pass filter with f 3dB = rad/s 2R Vo
( R1 + R2 ) C +
R R
1 – R
(b) high pass filter with f 3dB = rad/s
R1C V1 +

1 (a) (V1 – V2) (b) 2 (V1 – V2)

(c) low pass filter with f 3dB = rad/s
R1C
(V1 V2 )
1 (c) (d) (V1 + V2)
(d) high pass filter with f 3dB = rad/s 2
( R1 + R2 ) C
[EE-2014 : 2 Marks]
[EE-2012 : 2 Marks]
Q.35 In the figure shown, assume the op-amp to be
Q.32 In the circuit shown below what is the output
ideal. Which of the alternatives gives the correct
voltage (Vout) if a silicon transistor Q and an
ideal op-amp are used? Vo ( )
Bode plots for the transfer function ?
Vi ( )

Q
+VCC
1k +15 V 1k
– Vi +
V out Vo
+ –
5V 1 µF
–15 V
–VCC

(a) –15 V (b) –0.7 V Rf

(c) +0.7 V (d) +15 V
[EE-2013 : 1 Mark]
 24 Electronics Engineering Analog Electronics

The output of the circuit for a given input vi, is

Vo ( )
20 log
Vi ( ) R2 R2
(a) vi (b) 1+ vi
0 10 10
2
10
3
0 10 10
2 3
10 R1 R1
(a) 1 1
–10 – /4
R2
–20 – /2 (c) 1+ vi (d) +Vsat or –Vsat
R1
–30

[EE-2014 : 1 Mark]

Q.37 The transfer characteristic of the op-amp circuit

20 log
Vo ( )
Vi ( )
/2 shown in figure is
/4
2 3 3 R
(b) 0
1
10 10 10 0
1
10
2
10
10
–10 – /4 R
–20 – /2
R +Vsat
–30 vi – R +Vsat
–
+
–Vsat + vo
R –Vsat
20 log
Vo ( )
/2 R
Vi ( )
/4
2 3 2 3
(c) 0 10 10 10 0 10 10 10
1 1
–10 – /4 vo
–20 – /2

–30

(a)
–1
vi
Vo ( )
20 log /2
Vi ( )
/4
0 10 10
3
0 10 vo
(d) 1 10
2
1 10
2
10
3

–10 – /4

–20 – /2
(b)
–30
–1
vi
[EE-2014 : 2 Marks]

Q.36 An operational amplifier circuits is shown in vo

the figure.
vi
R (c) 1

R +Vsat
+Vsat –
vi – + vo vo
+ –Vsat
–Vsat vi
(d)
R2 –1
R1

[EE-2014 : 2 Marks]
 GATE Previous Years Solved Paper 25

Q.38 Consider the circuit shown in the figure. In this

0.1 µF
circuit R = 1 k , and C = 1 µF. The input voltage
is sinusoidal with a frequency of 50 Hz,
represented as a phasor with magnitude Vi and
1k
phase angle 0 radian as shown in the figure. 1k
The output voltage is represented as a phasor Vi –
Vo
with magnitude Vo and phase angle (in radian) +
relative to the phase angle of the input voltage?

C R
[EE-2015 : 1 Mark]
–
vi = Vo 0
+ v o = Vo Q.41 The filters F1 and F2 having characteristics as
C shown in Fig. (a) and (b) are connected as shown
R
in Fig. (c).

F1
(a) 0 (b) Vo/Vi

Vi Vo
(c) (d)
2 2
f1
[EE-2015 : 1 Mark] f

Q.39 The op-amp shown in the figure has a finite (a)

gain A = 1000 and an infinite input resistance.
A step voltage Vi = 1 mV is applied at the input F2
Vo/Vi
at time t = 0 as shown. Assuming that the
Vi Vo
operational amplifier is not saturated, the time
constant (in millisecond) of the output voltage, f2
f
Vo, is
(b)
C
R/2
1 µF
R
– +Vsat
1k R
+ + F1 –
1 mV Vi
A = 1000 Vo Vi + Vo
t = 0s – F2 –Vsat
R
(c)

The cut-off frequencies of F1 and F2 are f1 and f2

(a) 1001 (b) 101
respectively. If f1 < f2, the resultant circuit
(c) 11 (d) 1
exhibits the characteristic of a
[EE-2015 : 2 Marks]
(a) Band-pass filter (b) Band-stop filter
Q.40 The operational amplifier shown in the figure (c) All-pass filter (d) High Q-filter
is ideal. The input voltage (in Volt) is [EE-2015 : 1 Mark]
Vi = 2 sin(2 × 2000t). The amplitude of the
output voltage Vo (in Volt), is ______ . Q.42 The saturation voltage of the ideal op-amp
shown below is ±10 V. The output voltage Vo of
the following circuit in the steady-state is
 26 Electronics Engineering Analog Electronics

1k 9

+10 V 1 VCC
0.25 µF V3 –
– Vout
Vo 1
+ V2 +
2k –VSS
4
–10 V
V1

2k
(a) 1.8V1 + 7.2V2 – V3
(b) 2V1 + 8V2 – 9V3
(c) 7.2V1 + 1.8V2 – V3
(a) square wave of period 0.55 ms (d) 8V1 + 2V2 – 9V3 [EE-2016 : 2 Marks]
(b) triangular wave of period 0.55 ms
Q.46 The approximate transfer characteristic for the
(c) square wave of period 0.25 ms circuit shown below with an ideal operational
(d) triangular wave of period 0.25 ms amplifier and diode will be
[EE-2015 : 2 Marks] VSS
Vin +
Q.43 Of the four characteristics given below, which
are the major requirements for an –
D
instrumentation amplifier? –V SS
Vo
P. High common mode rejection ratio
R
Q. High input impedance
R. High linearity
S. High output impedance Vo
(a) P, Q and R only (b) P and R only
(c) P, Q and S only (d) Q, R and S only
(a)
[EE-2015 : 1 Mark]
Vin
Q.44 The circuit shown below is an example of a
Vo
R2

(b)
C

Vin
R1 +15 V
Vi + Vo
Vo
–
–15 V (c)

Vin
(a) low pass filter (b) band pass filter
Vo
(c) high pass filter (d) notch filter
[EE-2016 : 1 Mark]
(d)
Q.45 For the circuit shown below, taking the op-amps
Vin
as ideal, the output voltage Vout in terms of the
input voltages V1, V2 and V3 is [EE-2017 : 2 Marks]
 GATE Previous Years Solved Paper 27

Q.47 For the circuit shown below, assume that the R1 R2

op-amp is ideal. Which one of the following is (a) Z (b) Z
R2 R1
true?
R2
R (c) Z (d) Z
R1 + R2
R R [EE-2018 : 1 Mark]

R Q.49 In the circuit below, the operational amplifier is

– ideal. If V1 = 10 mV and V2 = 50 mV, the output
+ vo voltage (Vout), is
2R
100 k
vs
2R
10 k
(a) vo = vs (b) vo = 1.5 vs V1 –
Vout
(c) vo = 2.5 vs (d) vo = 5 vs V2 +
10 k
[EE-2017 : 2 Marks]
100 k
Q.48 The op-amp shown in the figure is ideal. The
input impedance Vin/iin is given by
Z
(a) 400 mV (b) 500 mV
(c) 600 mV (d) 100 mV
iin [EE-2019 : 2 Marks]
+
Vo
–
Vin

R1
R2
28 Electronics Engineering Analog Electronics

Electronics & Electrical Engineering

GATE Previous Years Solved Paper

A n swe rs & Expl a n a t i o n s

Answers
EC O perational Amplifiers

1. (100) 2. (c) 3. (b, c) 4. (d) 5. (c) 6. (d) 7. ( ) 8. (c)

9. (–4) 10. (0.02) 11. (Sol.) 12. (33) 13. (159) 14. (d) 15. (d) 16. (d)

17. (a) 18. (d) 19. (c) 20. (a) 21. (b) 22. (c) 23. (a) 24. (b)

25. (a) 26. (b) 27. (c) 28. (b) 29. (c) 30. (b) 31. (c) 32. (b)

33. (a) 34. (a) 35. (b) 36. (c) 37. (a) 38. (c) 39. (c) 40. (d)

41. (a) 42. (c) 43. (b) 44. (b) 45. (d) 46. (a) 47. (b) 48. (d)

49. (b) 50. (b) 51. (c) 52. (3.18) 53. (1093.02) 54. (c) 55. (b) 56. (d)

57. (d) 58. (250) 59. (1.5) 60. (1) 61. (2.8056) 62. (12) 63. (159.15) 64. (1)

65. (b) 66. (3) 67. (15) 68. (800) 69. (0.798) 70. (413.79) 71. (–1) 72. (b)

73. (44.4) 74. (1.145) 75. (c) 76. (0.5) 77. (6) 78. (d) 79. (b) 80. (c)

81. (c) 82. (b, c) 83. (c) 84. (a)

Solutions
EC O perational Amplifiers

1. Sol. A+ A
By voltage divider rule: Ad =
2
R 100 ( 100)
V– = 2 =1V = 100
R+R =
2
R Q CMRR = 60 dB = 103
V+ = 2 =1V
R+R
Ad
So, Vd = V + – V– = 1 – 1 = 0 V So, = 10 3
Ac
V+ +V 1+1
Vc = = =1V Ad 1
2 2 Ac = =
3 10
R f 100 k 10
A– = = = 100
R1 k Now, Vo = Ac Vc + Ad vd
Rf 100 1
A+ = 1+ × Vo = Ac Vc = × 1 = 100 mV
R1 100 + 1 10

100 k 100
= 1+ = 100
1 101
 GATE Previous Years Solved Paper 29

2. (d) When Vi is negative then Vo is positive.

So, diode D1 is reverse bias and diode D2 is
Vo Zf
= ...(For inverting amplifiers) forward bias,
Vi Z1
R2
Vo ( R + j L) Vo = Vi
= R1
Vi 1
R+
j C 4. (d)
L 1 1 Rf 8k
R= and = = 1+ = 1+
C LC R1 2k
L 1 = 1+4=5
+j L
Vo C LC 1
= == 0.2
Vi L 1 5
+
C j 1 A = 45 × 0.2 = 9
C
LC So, A is not very greater than 1.
L L L A 45
+j (1 + j ) So, Af = = = 4.5
C C C 1+ A 1+9
= =
L 1 L L 1
+ 1+ 5. (c)
C j C C j
Rf 90 k
(1 + j ) A1 = = = 90
Vo = R1 1k
1 j
Rf 100
Vo 3 A2 = 1+ = 90.09
= =2 = R1 100 + 1
Vi 2 2 2
A2 90.09 ( 90)
A1
3. (b, c) Ad = = = 90
2 2
Case-1 : Vi > 0 Ac = A1 + A2 = –90 + 90.09 = 0.09
D1
Ad 90
R1 CMRR = = = 1000
Ac 0.09
Vi – Vo
D2 Vo
+ 6. (d)
The open-loop gain of amplifier is very high, so
it will act as a comparator.
When Vi > 0 then Vo is negative.
So, if sinusoidal signal is applied to the input of
So, diode D1 is forward bias and diode D2 is the high comparator, then the comparator
reverse bias. generates the square wave output.
So, Vo = 0 V
Case-2 : Vi < 0 7. ( )

R2
Vo = Gain (Vin)
Vin = Voffset voltage = 1 mV
D1 Rf 1k
R1 Gain = 1 + = 1+ =2
R1 1k
Vi –
Vo Vo = 2 × 1 × 103 = 2 mV
+ D2
30 Electronics Engineering Analog Electronics

8. (c) 11. Sol.

Logarithmic amplifier, To increase the stability of op-amps, frequency
Vin compensation is used in op-amps.
I=
R
12. Sol.
If = I o e vd / VT
Rf
I = I f = I o e vd / VT A– =
R1
Vin 22 k
= I o e vd / VT
A– = = 2.2
R 10 k
Vin
e vd / VT = A = 2.2
RI o

Vd Vin R
Va = V+
= ln R + 15
VT RI o
Vo = –Vd Rf
A+ = 1 +
R1
Vin
Vo = VT ln Rf
RI o Vo Vo
= 1+ =
Va R1 R
V+
9. Sol. R + 15

2k Vo 22 R
= 1+ ×
V+ 10 R + 15
R
– I A+ = 3.2
Vo R + 15
+ 1k
2 mA 3.2 R
2k
= 2.2
R + 15
3.2 R = 2.2R + 33
Vo = –2 × 10–3 × 2 × 103 R = 33 k
= –4 V
Apply KCL at output node, 13. Sol.

Vo 4 S.R.
I + 2 mA = = = 2 mA fmax =
2k 4k 2 vo
I = –4 mA 12 1
fmax = 6
× = 159 kHz
10 2 × 12
10. Sol.
Rf 14. (d)
99
Vo = Vin = ×4
R1 100 The given figure has positive feedback and an
= –0.99 × 4 = –3.96 input at inverting terminal, so the given figure
is Schmitt trigger.
100
Vx = 4 × =2V
100 + 100 15. (d)
Rf 99 Rf
Vo+ = 1+ Vx = 1 + ×2 Vin
R1 100 Vo =
R1
= 1.99 × 2 = 3.98
10 k
= ×2 V = 4 V
Vo = Vo+ + Vo = 3.98 – 3.96 = 0.02 V 5k
 GATE Previous Years Solved Paper 31

10 k Vo C C
Vx = Vo × = Here, Vo = V1 sin t V2 sin t
10 k + 100 k 11 C C
Rf = –(V1 + V2) sin t
Vo+ = 1+ Vx
R1 20. (a)
10 k Vo 3Vo This circuit acts as a differentiator and
= 1+ = differentiation of triangular wave gives square
5k 11 11
wave,
Apply superposition principle,
R
Vo = Vo+ + Vo Vo = Vi = sCRVi
1 / sC
3Vo dVi d
Vo = 4 Vo = RC s=
11 dt dt
3 Vo
Vo = –4
11 21. (b)
Vo = –5.5 V

16. (d) –
Vo
When one input terminal of high gain Vi +

comparator circuit is connected to ground and C

a sinusoidal voltage is applied to the other input.
Then the output of comparator will be a square Control
gate Sample and
wave, hold circuit
va = +ve sinusoidal half Vo = +Vsat
va = –ve sinusoidal half Vo = –Vsat 22. (c)

Vi
Vo = Vio A
= 5 mV × 10,000
= 50 V
t
But, Vo = ± 15 V
Vo can never be greater than ±Vsat.

Vo 24. (b)
If open-loop gain is not infinite then,
t 1 Rf 10 k
= = = 10
R1 1k

18. (d) 1
=
10
In positive feedback op-amp act in saturation
region ±Vsat. Here applied voltage is positive, A 100 100
Af = = =
Vo = +Vsat = +15 V 1+ A 1 11
1 + 100 ×
10
19. (c)
Af –9
Rf
Vo = Vin
R1
32 Electronics Engineering Analog Electronics

25. (a) SR
Vm =
10 mH
A 2 fm
10 µF
1
10 = 6
Vs 100 10 × 100 × 2 × 20 × 10 3
–
1 – Vm = 79.5 mV
Vs = 10 cos(100t) + 2 3
+ Vo
28. (b)

V
KCL at node 1,
4V
V2 L
=
Vs R 2V
t
3
100 × 10 × 10 1 /6 5 /6 2
= =
10 10
–4 V
Vs
V2 = = cos 100t
10
Vp - p = 8 V
Vo 1/ C So, Vi = 4 sin t
V2 = 100 At, Vi = 2
1 1
= 6
= 10 sin t = t=
100 × 10 × 10 × 100 2 6
Vo = –10 V2 5
Another crossover at, =
= –10(–cos100t) 6 6
Vo = 10 cos100t 4
5
Ton 6 6 6 1
26. (b) Duty cycle = = = =
T 2 2 3
20 log x = 20 dB
x = 10 29. (c)
Gain × B.W. = 1 × 106 CMRR = 20 log Ad – 20 log Ac
1 × 106 = 48 dB – 2 dB = 46 dB
B.W. =
Gain 30. (b)
6
10 Rf Rf 8
= = 100 k = 10 5 Vo = ×2 + 1+ ×3
10 R1 R1 9

27. (c) 8
= 5× 2 + 6× =6V
3
Slew rate = A 2 f Vm
V = AVm sin t 31. (c)
dV 250 V2 250 V3 250
= AVm cos t
dt
+ + +
dV V1 1k – 50V1 1k – 50V2 1k – 50V3 V4
= SR = AVm 2 fm
dt max

20 log x = 40 V4
x = 100 = A Av =
V1
 GATE Previous Years Solved Paper 33

V4 V3 V2 35. (b)
Av = × ×
V3 V2 V1 Connect a Vs voltage source across inverting
Voltage across 1 k after 1st stage is, terminal of op-amp.
1000 × 50 V1 30 k
V2 =
1250
V2 Ii 10 k
= 40 –
V1 VA
+
Vs
V3 Ideal operational amplifier
Similarly, = 40
V2
Ri
Av = 40 × 40 × 50 = 8 × 104
By virtual short,
Av in (dB) = 20 log(8 × 104) = 98 dB VA = 0 V
33. (a) Vs VA Vs 0 Vs
Ii = = =
10 k 10 k 10 k
Vo
At = , =0 Vs
Vi = 10 k
So, Ri =
and at = 0, Ii

Vo 36. (c)
=1
Vi
1M
– +
34. (a)
IB2
R1 R1 V2 –
Vs eo
V1 +
IB1
–
R2 VC 1M
V +

R2
iL RL V1 = –IB1 × 1 M
V2 = V1 = –IB1 × 2 M
(Due to virtual ground)
V V V Vo Drop in feedback resistor,
+ + = 1 M = IB2 × 1 M
R2 RL R2 R2
eo = V2 + IB2 × 1 M
2V V Vo eo = –IB1 × 1 M + IB2 × 1 M
+ = ...(i)
R2 RL R2 eo = (IB2 – IB1) × 1 M
Vs V V Vo where, (IB2 – IB1) is offset current.
=
R1 R1
37. (a)
Vs – 2V = –Vo ...(ii)
High pass filter,
Putting Vo from equation (i),
1
Vs + 2 V 2V V c =
RC
= + +
R2 R2 RL 1
= 3 6
V Vs V 1 × 10 × 1 × 10
iL = = = = iL = 1000 rad/sec.
RL R2 RL
34 Electronics Engineering Analog Electronics

38. (c) = –tan–1 RC – tan–1 RC

Vc = 15 (1 – e–t/RC) = –2 tan–1 RC
= 15 (1 – e–1) = 9.45 V Minimum value of =– (at )
Maximum value of =0 (at = 0)
39. (c)
43. (b)
2k

1k I = I o ( eV /VT 1)
X –
y Vo 0 ( 1)
1V + =
100 k
1k
1k V
6 25 × 10 3 1
10 e 1 =
10 5
X = 1 Volt
y = 0.5 V (using voltage division rule) V = 0.06 V

2k 2k Vo V 1
+ y 1+ =
So, Vo = x 4k 100 k
1k 1k
= 1 × (–2) + 0.5 × (3) = –0.5 V Vo 0.06 1
=
4k 100 k
40. (d) Vo = 0.1 V
VI
Vo = VT ln 44. (b)
R1 I s
Vi Vo
2 4 =
V01 –V02 = VT ln + VT ln R1 + Ls R2
R1 I s R1 I s R2C 2 s + 1
4 Vo R2
= VT ln = VT ln 2 =
2 Vi ( R1 + Ls) ( R2C 2 s + 1)
which is equivalent to standard form of transfer
41. (a)
function of low pass filter, i.e.,
From the figure given the question,
a
R1 1/ sC R H(s) = 2
+ Vi 1+ 1 ps + qs + r
Vo = Vi R1 1 R1
+R
sC 45. (d)
Vo 1
= 1+ ×2 10 V
Vi 1 + RsC
5k I
Vo 2 (1 + RsC )
=
Vi 1 + RsC 5V

Vo 1 RsC V
= +
Vi 1 + RsC
– V BE
+
+
42. (c) 1.4 k V
5V
– –
Vo 1 RsC I
=
Vi 1 + RsC
(1 – sRC) – 1 + sCR
 GATE Previous Years Solved Paper 35

10 5 48. (d)
I= = 1 mA
5 At = 0, XL = L = 0
V = 1.4 × 1 = 1.4 Volt Hence circuit can be redrawn as below,
V = V + VBE
R1
= 1.4 + 0.6 = 2 Volts
i1
46. (a) –
+
+ vo
R1 VA = 0
– –
Vo
I1 +
I2 R2
vo = 0
Vi At = , XL =
Hence, circuit can be redrawn as below,
R3
R1

i1
Assuming ideal op-amp, voltage at point A is –
zero. So, the given circuit can be considered as +
+ vo
shown below:
–
R2
v o = R1 i L
R1 Hence given circuit is a high pass filter.
–
Vo
+ 49. (b)
Vi R3
(O/P) R2 R2 sC
T(s) = = =
(I/P) 1 R1sC + 1
R1 +
Cs
R2
Av =
R1 R2
s
R1
47. (b) T(s) = 1
s+
At, VI = –10 V R1C
Vo 0 0 20 0 ( 10) It is the transfer function of high pass filter with
= +
R 4R R cut-off frequency.
Vo = –5 + 10 1
= 5V = rad/sec.
R1C
At, VI = –5 V
Vo 0 0 20 0 ( 5) 50. (b)
= +
R 4R R Due to virtual short,
Vo = –5 + 5 VC = VB = 0 V
= 0V (Collector voltage of transistor Q)
For VI > –5 V, both diodes are conducting. and given that, base voltage of transistor Q,
So, Vo = 0 V VB = 0 V
So, VC = 0 V
36 Electronics Engineering Analog Electronics

It means collector to base of transistor Q are short cut-off frequency,

circuited. 1 + R2Cs = 0
If any junction of transistor is short-circuited
or, R2Cs = 1
then the junction acts as reverse bias.
So, the C-B junction is reverse bias.
1 1
or, R2 = =
Cs 2 fC
The given op-amp is an inverting configuration
which have positive voltage as input. So, the = 3184.7 or 3.18 k
output voltage of op-amp will be negative
53. Sol.
voltage,
Given circuit is a op-amp series regulator Vo is
Vout = –ve voltage
given by
Emitter voltage of transistor
VE = –ve voltage R1
Vo = 1+ Vz
Given transistor is npn transistor and R2
VB = 0 V
1k
VE = –ve voltage 9V = 1+ 4.7
R
So, the E-B junction will be forward bias. Thus,
R = 1093.02
the transistor is in active region and will behave
as closed switch. 54. (c)
So, VBE = 0.7 V(for silicon transistor)
R2
VB – VE = 0.7 V
VE = VB – 0.7 I
VE = 0 – 0.7 R1 V2 I1
–
VE = –0.7 V Ri Vo
I V1 +
I2
51. (c)
Output of first op-amp,
IB = I1 = I2
1 1
Vout 1 = 2 +1 1+
1 1 V2 = ( R1 R2 ) I1 ...(i)
= 2 + 1(2) = 4 V KCL at node ‘2’,
1 I + I = I1
Vout = 4 1 + = 4(2) = 8 V
1 0 V2 Vo V2 V2
+ =
R1 R2 Ri
52. Sol.
Vo R1 + R2
0 Vo 0 Vi = V2 ...(ii)
+ =0 R2 R1 R2
Z2 Z1
Q Ri is very high for op-amp.
where, Z 2 = R2 10 nF By using equations (i) and (ii),
Z 1 = R1 = 1 k Vo = I1R2
1
Vo R2 55. (b)
Z2 Cs
or, = = If the resistance R E is increased then A cm
V1 Z1 R1
decreases.
R2
= Ad
R1 ( R2Cs + 1) Hence, CMRR = increases
Acm
 GATE Previous Years Solved Paper 37

56. (d) Hysteresis = VTH – VTL

3R R1 R1
= L + L+
R2 R2
R 1
V1 –
Vo R1 R1
+ 500 mV = ( 5) +5
V2 20 k 20 k
2R R
R1
=
2k
R 1 = 500 × 2 × 103 × 10–3
By applying KCL at node, we get
= 1000 = 1 k
V2 V1 V2 V2 Vo
+ + =0
R 2R 3R 61. Sol.
6V2 6V1 + 3V2 + 2V2 PQ1(max) = VCE(max) × IC max ...(i)
= Vo
2 VCE(max) = Vimax – Vo
11 = (24 – 10 V) = 14 V
Vo = 3V1 + V2
2 IE = IC = 200 mA + 0.4 mA
58. Sol. 4 0
ICmax = 200.4 mA IR2 = mA
10
1
I50 = A = I 100 Put values in equation (i), we get,
50
PQ1(max) = 14 × 200.4 × 10–3 Watt
1
Vo = [250(1 + ) 250(1 )] = 2.8056 Watt
100
1 62. Sol.
= × 250 = 0.25 V = 250 mV
1000 V+ > V–
59. Sol. So, Vo = Vsat
= 12 Volts
1k 1k
VOB = 5 1 = 6V
1k 1k 63. Sol.

1k 1 1k 1
5 + 1+ f3-dB = = 159.15 Hz
VOA = 2 RC
1k 2 1k
1 64. Sol.
= –4 V V+ = V
2
10 k Vx 10 k
VOB
= 1.5
VOA R

10 k
60. Sol. Vin –
Vo
Vo +
L+

Apply nodal analysis at inverting terminal,

VTL VTH
V1 Vin 0 0 Vx
=
10 k 10 k
Vin = –Vx ...(i)
L–
38 Electronics Engineering Analog Electronics

Again apply nodal analysis at node Vx , When V1 exceeds 2 V output of op-amp V01 goes
0 Vx Vx 0 Vx Vo to VCC and drives BJT into saturation shorted
= + ...(ii)
10 k R 10 k LED will glow.
Put the value of V x from equation (i) in In the given problem Vi exceeds 2 V three times
equation (ii), we get and hence output V01 of op-amp goes to VCC
R = 1k thrice so that LED glow three times.

65. (b) 67. Sol.

10 k
+VCC V2
10 k 10 k
V4
R IC VB = VA
+
Vref 10 k +VCC
VB VN –
– VB 1k Vo
– +
V1
+ –VCC
VA R2 1k
V3 VB
R1 IC = IE RL 1k 1k
VN – 1

Node A:
VA = VCC – Vref VA V1 VA V3 V VN 1 VA
VB = VA (since virtual short) + + .... A + =0
1k 1k 1k 1k
VCC VB
IC = N
R VA + 1 = V1 + V3 + ... + VN – 1
2
VCC (VCC Vref ) Vref VB = VA (Q Virtual short)
= =
R R Node B:
IC Vref VA V2 VA V4 V VN VA Vo
Io = I E = = + + .... A + =0
1+ R 10 k 10 k 10 k 10 k
N
66. Sol. Vo = VA +1 (V2 + V4 + V6 + ... + VN )
2
10 V 10 V N (V1 + V3 + ... + VN 1)
= +1
2 N
+1
100 2
8k
–(V2 + V4 + ... + VN)
+VCC
= V1 – V2 + V3 – V4 + ...
VB – V01
1 1 1
Vi + = 1+ + + ...
15 k 2 3 4
2k
–VCC 1
= =
N
Output of op-amp goes to saturation
10 V + 2 k Vo = Vsat = VCC
VB = =2V
8k +2k = 15 V
 GATE Previous Years Solved Paper 39

68. Sol. Let at t = T1,

1M VB exceeds VA(–1 V) so that V01 changes from
–10 V to 10 V.
+VCC
Vo charges from –5 V to 5 V
–
0V Vo VB = Vt + (Vi – Vf ) e–t/
+
= –10 + [10 – (10)] e–t/RC
–VCC 10 k At t = T1, VB = –1
1M
–1 V = –10 + 20 e–T1/RC
VCC
20
T1 = RC ln
Generated photo current 9
Responsivity =
Incident light power = 10 × 10 × 100 × 10–6 × 0.798
3

Io = 0.798 sec.
=
Pi
70. Sol.
Io Overall input = Vios + Vinput
0.8 A/W =
10 × 10 6 = 5 mV + 25 mV = 30 mV
Io = 8 µA
Rf
Vo = Io × 1 M 1+
R1
= 8 × 10–6 × 1 × 106 = 8 V Vo = × Overall input
1 Rf
The photo current through load RL = 10 k is 1+ 1+
AOL R1
given by
Vo 8 15 k
IL = = 1+
RL 10 × 10 3 1k
× 30 × 10 3
=
1 15 k
= 800 µA (in upward direction) 1+ 1+
100 1k
69. Sol.
= 413.79 mV
Initially switch is closed and VB = 10 V
V01 = –10 V 71. Sol.
V0 = –V2 = –5 V V01 R
H1(s) = = 1+ 1
Vo Vi sL
VA = ×1 k = –1 V
4 k +1k 1 1
= 1+ = 1+ 6
10 V sL / R1 s × 10
V0 R3 sR3C
H2(s) = = =
10 µF V01 R2Cs + 1 1 + sR2C
+10 V Cs
– 470
VB Vo Cs 1
+ V01 = =
10 k 1 + Cs 1 + 1
VA –10 V Cs
–10 V 4k H(s) = H1(s) H2(s)
1k
6
1 s × 1 × 10
= 1+ 6 6
s × 10 1 + s × 10
At t = 0;
= –1
The switch is opened and as t , VB
approaches –10 V.
40 Electronics Engineering Analog Electronics

72. (b) 74. Sol.

+15 V 20 k
Vin –
V out 5k
+
Vp –
–15 V 31I a Vo
Vx +
V1
I1
10 k
5k
20 k
3V KCL at a,
3 × 10 + Vo × 5 6 + Vo Vo Vx Vx0.7
V1 = = =
15 3 20 5
Vo – Vx = 4Vx – 2.8
6 + 15
VUT = =7 V Vo = 5Vx – 2.8 ...(i)
3
Now, I1 = 31 I
6 15
VLT = = 3V Is eVx /VT = 31 Is eVP /VT
3
Vx V
73. Sol. = ln 31 + P
VT VT
• In the given circuit: Vx VP
= ln 31
Feedback factor, VT
R1 1 Vx = 0.789 V
= =
R1 + R2 80 From equation (i),
Vo = 5 × 0.789 – 2.8 = 1.145 V
Gain
Without feedback 75. (c)
5
A0 : 10 For t > 0,
With feedback 1 µF
+ – +
V1 +
I
Aof : 80 2.5 V 1 µF V2
1k
1V – – –
0V
Af + vOUT(t )

f
fc fc 15 k
1V
I= = 1 mA
Ao 1k
• Aof = 80
1 + Ao The capacitor charges with constant current I
and both V1 and V2 will increase till V2 reaches
10 5
• f c = f c (1 + Ao ) = 8 1 + Hz = 10008 Hz 2.5 V. Thereafter, V2 = 2.5 V and V1 increases
80
with time.
• Gain at f = 15 kHz = 15000 Hz is When, vout(t) = –10 V
Aof 80 V1 = 7.5 V
Af = = 44.4 t
2
f 15000 2 1
1+ 1+ So, (1 mA) dt = 7.5 V
fc 10008 1 µF
0
103t = 7.5
t = 7.5 msec
 GATE Previous Years Solved Paper 41

76. Sol. 78. (d)

Applying the concept of virtual ground, we get 1k
R2
Vo = Vin
R1 1k +5 V
Vi –
[Q Non-inverting amplifier] Vo
+
31 k
Vo = ×1 V –5 V
1k
Vo = –31 V < –15 V Given circuit is a Schmitt trigger of non-inverting
which is not possible. type,
Hence, the output voltage of the op-amp is equal Vo = ± 5 V
to –15 V. Vo + 1 + Vi × 1 Vo + V
V+ = +
1+1 2
31 k
Let, Vo = –5 V
+15 V
1k 5 + Vi
–
V+ =
A
2
+ + +
1V Vo = –15 V Vo can change from –5 V to +5 V if V + > 0 i.e.
– –
–15 V 5 + Vi
>0 Vi > 5 V.
2
Now applying KCL of node ‘A’, we get,
Similarly Vo can change from +5 V to –5 V if
VA ( 15) VA 1
+ =0 Vi < –5 V.
31 k 1k
But given input has peak value 1 V. Hence
VA V 15 1 output cannot change from +5 V to –5 V or –5 V
+ A = +
31 k 1k 31 k 1k to +5 V.
1 1 15 Output remain constant at +5 V or –5 V.
VA + = +1 Correct answer is option (d).
31 1 31
VA = 0.5 V 79. (b)

77. Sol. Op-amp active filter (LPF) inverting type 3-dB

cut-off frequency,
1k
1 1
fc = =
2 RC 2 × 2 × 10 3 × 10 6
1k
– Io 500
Vo = = 79.58 Hz
2V + 2
1k
80. (c)

Vo = (1 + 1) × 2 = 4 V Rin
RF

2 4 0 4
+ Io + =0 (KCL at node Vo) V01
1k 1k V1

–2 + Io – 4 = 0 R1
Io = 6 mA Vref R2
42 Electronics Engineering Analog Electronics

Rf Rf Step-1 : KVCL at V2,

Vref R2
V01 = 1+ Vx = 1 + Iin + IF = Iref ...(1)
Rin Rin R1 + R2
Vin V2 Vout V2 V2 + Vref
+ = ...(2)
R Rf R
RF
Rin Step-2 :
Vin
Q V1 = 0 V2 = 0
V 02
Vin Vout Vref
R1 + =
R Rf R
R2
Vout Vref Vin Vref Vin
= =
Rf R R R

Rf Rf
V02 = Vin Vout = (Vref Vin ) ...(3)
Rin R
Step-3 :
Total, V0 = V01 + V02
For, Vout = 0
Rf R2 Rf
V0 = 1+ Vref + Vin Rf
Rin R1 + R2 Rin (Vref Vin ) = 0
R
Given,
Vref –Vin = 0
Rf R2 Rf Vin = Vref ...(4)
1 = 1+ Vref (0.1)
Rin R1 + R2 Rin
82. (b, c)
...(1)
Given circuit is a high-pass filter.
Rf R2 Rf
6 = 1+ Vref (1) R2 = 2 k
Rin R1 + R2 Rin
...(2) +15 V
1 µF R1 = 1 k
Rf
(1 0.1) +
(2) – (1) 6–1 = Vin +
Rin Vo
– –15 V –
Rf 5
= = 5.555
Rin 0.9
1 1
Rf = =
c R1C1 10 3 × 10 6
= 5.555
Rin
= 1000 rad/sec
Hence, option (b) and (c) is correct.
81. (c)
83. (c)
Given: Vin << VCC ; Vref << VCC

R V2 RF
15 V
Iin IF VCmax
R Iref
+VCC t
Vin VCmin
Vref V1 Vout
–12 V
–VCC
 GATE Previous Years Solved Paper 43

If, V0 = +15 V
R
D1 is ON.
R2
D2 is OFF. 1k

R 1k Vo
Vi
+15 V R3
C

C Vo

–12 V Maximum gain = 12 dB

R R R R 20 × log Amax = 12
Amax = 4
R2
1+ =4 R2 = 3R1
Capacitor charge upto VUT, R1
15 × R R = 3×1=3k
VCmax = VUT = =5V
R + 2R log10 c = 3
If, V0 = –12 V c = 1000 rad/sec
D1 is OFF. 1 1
D2 is ON. c = C=
R3C R3 × c
Capacitor discharge upto VLT,
1
R C= = 1 µF
1000 × 1000
+15 V 85. (–0.5)

Vo Analog output,
C
Vo = –Resolution × Gain ×
–12 V
Decimal equivalent of
R R R R binary data
vr 1.6
Resolution = n
= = 0.4
2 24
12 × 2 R Decimal equivalent = 5
VC min = VLT = = 8V
2R + R Gain = 1
VCmax – VCmin = 5 – (–8) = 13 V vo = –(0.1) (5) (1)
= –0.5 V
84. (a)

20 log A

12
9

3 log10( )
44 Electronics Engineering Analog Electronics

Answers
EE O perational Amplifiers

1. (c, d) 3. (1) 5. (a) 6. (a) 7. (b) 9. (d) 10. (d) 11. (a)

12. (d) 13. (d) 14. (b) 15. (d) 16. (c) 17. (d) 18. (a) 19. (d)

20. (c) 21. (b) 22. (c) 23. (d) 24. (b) 25. (d) 26. (d) 27. (d)

28. (b) 29. (d) 30. (d) 31. (b) 32. (b) 33. (c) 34. (b) 35. (a)

36. (d) 37. (c) 38. (d) 39. (d) 40. (1.245) 41. (b) 42. (a) 43. (a)

44. (a) 45. (d) 46. (a) 47. (c) 48. (b) 49. (a)

Solutions
EE O perational Amplifiers

2. Sol. Vi(volts)

– D1
Vo t(sec)
Vi + VA 0.5 1 2
C D2 Vout

1V

For 0 < t < 0.5 s

t(sec)
Capacitor get charged upto 1 Volt. D1 is forward
bias and D2 is reversed bias.
3. Sol.
2R
–

Vi + Vo = 1 V R V
+ –
1V R Vo
– V +
2V
R
–1 V
There is no discharging path providing for this R
capacitor. It will remain charged with 1 V.

2 V 1 V V
– + =
Vo R R R
Vi +
+ 1
1V V = Volts
– 3
0 V V Vo
=
R 2R
Vo = 3 V = 1 Volt
 GATE Previous Years Solved Paper 45

4. Sol. 9. (d)

100 k
a –
– Vo
Vo + +
Vi + Vs
b
– 1k
Here, Vi = Vo 90 k
10 k
Vcm = Va + Vb
1
= (Vi + Vo ) = Vi = Vo
2 I2 = 0, I1 = I
V+ = 10 k × I
5. (a)
V0 = (90 + 10) k × I
2R = 100 k × I
x = = 2
R V+ 10 k × I 1
= = =
R V0 100 k × I 10
x = = 1
R
10. (d)
x 1 1
= x = x
x 2 2 1k

6. (a)
–
V0
2R +
1 mA

R
–
V+ + V0
–2 V0 = –1 mA × 1 k
R = –1 V
2 + sin100t
R
11. (a)
2 V+ 2 + sin 100t V+ S.R. = Vm
+ =0
R R 65.8 V/µs = 2 f × 10
1 62.8 × 10 6
V+ = sin 100t f=
2 2 × 10
0 V+ V+ V0 = 1 MHz
=
R 2R
12. (d)
3
V0 = 3 V+ = sin 100t 1
2 Vin ×
jC Vin
8. Sol. V(+) = =
1 1 + jRC
R+
(A) (R) : There is no feedback. jC
(B) (S) : Input impedance is resistive and where, V(–) = V(+) (For ideal op-amp)
feedback is capacitive in nature.
Vin V( ) V( ) V0
(C) (P) : Input impedance is capacitive and =
feedback is resistive in nature. R1 R1
V0 = 2V(–) – Vin
= 2V(+) – Vin (V(–) = V(+))
46 Electronics Engineering Analog Electronics

2 100 k
= 1 Vin But, Vy = 1+ Vx = 11Vx
1 + j RC 10 k

1 j RC 10 Vx Vx
= Vin Ix = = 100 k
1 + j RC 1M Ix

V0 15. (d)
= 2 tan–1 RC
Vin V0 Rf
=
For –90° 90°, maximum phase shift occurs Vin R1
(±180°). If, gain = –25
13. (d) 1000 k
then, R1 = = 40 k
Using KCL at node 1 we have, 25
If, gain = –10
10 k 1 10 k 1000 k
then, R1 = = 100 k
1k
10
1k
Vi So, if we keep R1 to be 100 k then we never get
the gain –25 for any RF so we can keep R1 to be
– 40 k .
Vo
+
16. (c)
Output will be at its saturation values and it is
having a phase difference of (–180°).
V1 0 V1 V1 Vout
+ + =0 For +ve half of the input 1st diode will be on
10 1 10
making –ve terminal of op-amp to 0.7 V larger
12V1 = Vout ...(i)
than the voltage at +ve input so output will be
Also, using KCL at inverting node, we get
–Vsat.
Vin 0 0 V1 For –ve half of input reverse of above will
=
1 10 happen and output will go +Vsat.
V1 = –Vin × 10 ...(ii)
From equation (i) and (ii) we get, 17. (d)
Vout For –ve half of the input +ve terminal of op-amp
= –120 is at higher potential than –ve terminal and
Vin
output goes to +V sat but due to this high
14. (b) potential diode gets on and restricts the output
to 0.7 V only. And for +ve half of the input +ve
100 k
terminal of op-amp is at lower potential than
–ve terminal’s potential and output goes to –Vsat
10 k and remains at –Vsat.
–
Vy
+ 18. (a)
0A Output will be either at +Vsat or –Vsat. When
Vx output will be at +Vsat diode connected to 10 k
Ix Ix R3 = 1 M resistance will be on making voltage at point P
equal to 6 V.
Vx Vy
Here, Ix = When output is at –Vsat diode connected to 2 k
R3 resistance will be on making voltage at point P
equal to –10 V.
 GATE Previous Years Solved Paper 47

19. (d) R
It behaves as current source because the output
V01 R
current (I0) depends upon (Vin) and resistance Vi P –
only. Vo
+
Q
V × R2 V02 R
R1 + R2 R2 V R
Where, I0 = =
r R1 + R2 r
Vo will be positive due to non-inverting action.
20. (c)
So, output is always rectified.
Let the voltage at the non-inverting terminal of
the op-amp be Va volts and the voltage at 22. (c)
inverting terminal be Vb volts.
R2
At t = 0+ switch is open V0 = 5 V and Vb = –10 V
V0 × 10 k 50
Va = = Volts
100 k + 10 k 11 R1 C
Vi –
At t , VA Vo
+
Vb 10 V
R3
Vb = Vf + (Vi – Vf ) e–t/RC ...(i) R4

50
Putting, Vb = at t = T1
11
Vi = –10 V R4
VA = × Vi
and Vf = 10 V in equation (i), R4 + R3
we get, T1 = 12.98 µ-sec RB V
VA = × Vi = i
At, t = 12.98 µ-sec RB + RB 2
V0 changes from 5 V to –5 V Let, Vi only on inverting terminal,
21. (b) Rf
V01 = Vi
For (Vin > 0), R1
P V01 = Negative 1 R2
Q V02 = 0 Here, R f = R2 =
sC 1 + sCR2
R
Let, Vi only on non-inverting terminal,

V01 R Rf Vi
Vi P – V02 = 1+
Vo R1 2
+
Q V0 = V01 + V02
V02 R
R Rf Vi
= 1
R1 2
Putting the value of Rf , we get,
V0 will be positive due to inverting action.
For (Vin < 0), R2 Vi
V0 = 1
P V01 = 0 R1 (1 + sCR2 ) 2
Q V02 = Positive Here, (R1 = R2 = RA)
48 Electronics Engineering Analog Electronics

1 Vi 26. (d)
V0 = ×
1 2 For emitter follower:
1+
sCR A Av 1; AI is high
So, it is a high pass filter. Ap = Av AI is high Pout > Pin
For transformer,
23. (d) Pin = Pout
(sCR A ) V
Vin = × i 27. (d)
1 + (sCR A ) 2
1k +6 V
1/ sC 1 Vi –
V0 = 1 R Vin = Vin Vo
C
+ A 1 + sRA V1 +
sC 2 2 –3 V 2k

sRAC
1
V0 = V
C (1 + sR AC ) in
1 + sRA 1k
2
Which is similar to equation of a band pass
filter. when Vi < V1 (upto t2);
V0 = +ve
24. (b) when Vi > V1 (t2 t t4);
Voltage-series feedback arrangement or voltage- V0 = –ve
voltage feedback.
1 1
V1 = V0 = V0
25. (d) 1+ 2 3

Is R = 10 k 28. (b)

2R
V0 = 1 + V = (1 + 2) (2) = 6 V
Vs +
R
Vs Vo
– 29. (d)

Vs
High pass filter
R = 10 k Los pass filter
C = 10 µ F

Vs V0
Is = ...(i)
R
1/ j C 20 Hz 30 Hz
Vs = V0 ...(ii)
1
R+ Pass band
j C
Is = –Vs j C It is a band pass filter.
= –j(10 × 2 × 50 × 10 × 10–6)
30. (d)
= –j10 .... mA
First section is differential amplifier having
= 10 mA lagging by 90°
gain –1.
 GATE Previous Years Solved Paper 49

31. (b)
Vo

R2
+12 V

C R1 Vo
12 V Vi –
Vi
–12 V
+

–12 V

Vin 0 0 V0
Rf =
1 R2
R1 +
SC
R1
V1 –
Vo V0 R2
V2 +
=
R2 Vi 1
R1 +
Rg sC
It is a high pass filter with
1
f3-dB = rad/sec.
Output is, R1C
R f + R1 Rg Rf
Vo = V2 V1 32. (b)
R g + R2 R1 R1

Vo = V2 – V1 = –Vi
Q
Second stage-schmitt trigger,
1k +15 V
– –
V V out
Vo +
+ 5V
–15 V

Vt
Rf
Rg Using the concept of virtual ground, V = 0

Rg V0
Vt = ± V0 = =±6V Q
R f + Rg 2

Vo
Vout

+12 V Vout = –0.7 V

33. (c)
Vi Output of first op-amp,
–6 V +6 V
1 1
Vout 1 = 2 +1 1+ = 2 + 1(2) = 4 V
1 1
–12 V
1
Vout = 4 1 + = 4(2) = 8 V
1
50 Electronics Engineering Analog Electronics

34. (b)
Op-amp ‘3’ circuit is a differential amplifier so,
V0 = V01 – V02 ...(i) Corner
frequency
Now, apply KCL at node ‘2’,
V2 V1 V2 V02 0 10 10
2
10
3
0 10 10
2 3
10
+ =0 ...(ii) 1 1
2R R
–10 – /4
and apply KCL at node ‘1’,
–20 – /2
V1 V2 V1 V01
+ =0 ...(iii) –30
–20 dB/dec
2R R
From equation (i), (ii) and (iii), we get,
V0 = 2(V1 – V2)
36. (d)
35. (a) The circuit of op-amp ‘1’ is a Schmitt trigger,
Rf therefore,
V01 = ±Vsat
and the circuit of op-amp ‘2’ is a non-inverting
–
R=1k Vo amplifier.
Vi +
V0 R
1 µF = 1+
V01 R
V0 = 2V01
where, V01 = ±Vsat
1k
– Therefore, the answer is V0 = ±Vsat.
Vo
Vi +
37. (c)
1 µF
Case-I : Vi > 0, the circuit will look like.
Buffer

R
R +Vsat
Low pass vi – R
–
+
This filter is considered as low-pass filter (LPF). +
–Vsat vo
The transfer function for LPF, R
R
V0 1/ sC 1
= =
Vi 1 1 + sCR
R+
SC
Hence, V0 = 0
1 1 Case-II : Vi < 0, the circuit will look like.
= =
1 + j (10 3 ) (10 6
) 1 + j (10 3
) R

1000 1
= = R
1000 + j s
1+ +Vsat
1000 R
vi – R +Vsat
c (corner frequency) = 103 rad/sec. –
+ V01
The gain at low frequencies, + vo
–Vsat
1 1 R –Vsat
Av = = =1 R
1 + sCR 1
 GATE Previous Years Solved Paper 51

V01 R 39. (d)

= ...(i)
Vi R The circuit is,
V01 = –Vi ...(ii) C = 1 µF

V0 R
and = R = 1000
V01 R
–
V0 = –V01 ...(iii) VA Vo
Vi +
From equation (ii) and (iii), A = 1000

V0 = Vi

38. (d) Now, the gain of op-amp is 1000.

The circuit is, So, V0 = 1000(V+ – V–)
Since, V+ = 0 (grounded)
I R
V– = VA
The above circuit can be redrawn as,
C
– C = 1 µF
B
Vi Vo
A 1000
+
‘A ’ Vo
I C VA

I R Vi –1000 VA

So, V0 = –1000 VA
Since, circuit has negative feedback, so with help
Now, KCL at node ‘A’,
of virtual short VA = VB.
VA Vi VA V0
So, KVL in the loop from A to B given, =
1000 1 / SC
I I
I Vi + I =0 VA Vi VA ( 1000 VA )
sC sC =
1000 1/SC
Vi (sC )
So, I= VA – Vi = (1001 VA) sC
2
VA – Vi = (1001) × 1000 VA sC
So, VA = –IR
VA – Vi = s (1001000 × 10–6) VA
sCRVi VA – s1.001 VA = Vi
VA =
2
Vi
and VA = VB VA =
1 s(1.001)
sCRVi
so, VB = Since, V0 = –1000 VA
2
1000
VB V0 = Vi
Now, =I 1 s(1.001)
R
So, V0 = VB – IR Since, pole is at (1/1.001), so time constant is
approx ‘1’.
Vi (sCR ) Vi (sCR )
V0 =
2 2 40. Sol.
= –Vi (sCR) Vi = 2 sin(2 × 2000t)
So, V0 = –j RCVi The transfer function of the system is,
So, V0 lag Vi by 90° or phase or V0 w.r.t. Vi is –90°.
1000
H(s) =
(1000 × 0.1 × 10 6 s + 1)1000
52 Electronics Engineering Analog Electronics

1 44. (a)
H(s) = 4
(10 s + 1) R2
The input is 2 sin(2 × 2000t)
= 4000
V0 = 2 H ( j ) = 4000 × sin(4000 t ) R1
C
Vi –
Output = 1.245 sin(4000 t – 51.46°) Vo
So, amplitude of output is 1.245. +

41. (b)
To check the type of system:
1 1
We apply a delta function at input Vi = (t) R2 R2 +
Vout j C j C
R/2 =
Vin R1
R
F1 –
Vo Vout R2
Vi + =
A Vin R1 ( R2 j C + 1)
F2
R So the system is a low pass filter.
So, voltage at A will be same as voltage at output
45. (d)
V0. VA will be equal to voltage due to F1 + voltage
due to F2. Since, f1 < f2, so VA/Vi will be 9

VA /Vi 1 VB
V3 –
1 Vout
VA
V1 +

f 4
f1 f2

V0/Vi will be V2

Vo/Vi 4 1
VA = V1 + V2
5 5
Vout = –9 V3 + 10 VA
= –9 V3 + 8 V1 + 2 V2
f 46. (a)
f1 f2

So, the system work as a band stop filter. +V ss

Vin +
42. (a) VA
–
D
The given circuit in a astable multivibrators so –Vss
Vo
output will be a periodic square wave and from
the circuit = 0.5. R

1+
So, time period will be 2 ln ,
1
Vin > 0 VA = +VSS, D on, V0 = Vin
1 + 0.5 Vin < 0 VA = –VSS, D off, V0 = 0
T = 2 × RC ln = 0.55 ms
1 0.5
 GATE Previous Years Solved Paper 53

Vo 1 1 V0
Vin + =
R2 R1 R1
V in
=
Vo
R1 + R2
Vo = 0
V in
Vin × R1 = V0
R1 R2

R1 + R2
V0 = Vin × ...(ii)
R2
Equation (ii) in equation (i),
47. (c) Vin V0
= iin
I3 R VB R I1 Z
R1 + R2
I2 R Vin Vin
R2
I3 R = iin
– Z
VA Vo
+ I1 Vin R1 + R2
2R
VA 1 = Z
iin R2
Vs Vin R2 R1 + R2
2R
iin R2 = Z
Vs
VA = Vin R2
2 = Z
iin R1
VA Vs
I3 = = ...(i)
R 2R 49. (a)
VB – VA = I 3 R
100 k
V V
VB = VA + I 3 R = s + s = Vs
2 2
10 k
VB Vs V3 = 10 mV
I2 = = ...(ii) –
R R Vo
I1 = I2 + I3 V2 = 50 mV +
10 k
Vs Vs Vs
= + = [1.5] R2 = 100 k
R 2R R
V0 – VB = I 1 R
V
V0 = VB + s [1.5] R R2
R V0 = (V2 V1 )
R1
= Vs + 1.5 Vs = 2.5 Vs
100 k
48. (b) = 10 k (50 mV 10 mV)
According to virtual ground,
= 10 (40 mV) = 400 mV
VA = VB = Vin
At node A,
Vin V0
= iin ...(i)
Z
 2 Diodes Applications

ELECTRO NICS EN GINEERIN G Vo

(GATE Previous Years Solved Papers)

(d) 5.9
Q.1 The 6 V Zener diode shown below has zero 0
Zener resistance and a knee current of 5 mA.
The minimum value of R. So that the voltage [EC-1993 : 1 Mark]
across it does not fall below 6 V is Q.3 The Ebers Moll model is applicable to
50 I (a) Bipolar junction transistors
(b) NMOS transistors
10 V 6V R 6V (c) Unipolar junction transistors
(d) Junction field effect
[EC-1995 : 1 Mark]
(a) 1.2 k (b) 50
Q.4 A Zener diode in the circuit shown in below
(c) 80 (d) 0
figure has a knee current of 5 mA, and a maximum
[EC-1992 : 2 Marks]
allowed power dissipation of 300 mW. What are
Q.2 The wave shape of Vo in figure is the minimum and maximum load currents that
4.1 V 4.1 V can be drawn safely from the circuit, keeping the
output voltage Vo constant at 6 V?
50
10 sin314t 10 k Vo +
+ +
9V Load
–
–
Vo –

5.9
(a) 0 mA, 180 mA (b) 5 mA, 110 mA
(a)
0 (c) 10 mA, 55 mA (d) 60 mA, 180 mA
–5.9 [EC-1996 : 2 Marks]

Vo Q.5 For small signal ac operation, a practical

forward biased diode can be modeled as
4.1
(a) a resistance and a capacitance.
(b)
0 (b) an ideal diode and resistance in parallel.
–4.1 (c) a resistance and an ideal diode in series.
(d) a resistance.
Vo
[EC-1998 : 1 Mark]
4.1
Q.6 For full wave rectification, a four diode bridge
(c)
0 rectifier is claimed to have the following
advantages over a two diode circuit:
–4.1
 GATE Previous Years Solved Paper 55

1. Less expensive transformer R

2. Smaller size transformer and +
IZ IL = 10 mA
3. Suitability for higher voltage application of
these Vin Vo
DZ
(a) only (1) and (2) are true.
–
(b) only (1) and (3) are true.
(c) only (2) and (3) are true. (a) R 1800
(d) (1), (2) as well as (3) are true. (b) 2000 R 2200
[EC-1998 : 1 Mark] (c) 3700 R 4000
(d) R > 4000
Q.7 A dc power supply has a no-load voltage of 30 V,
and a full load voltage of 25 V at a full load [EC-2002 : 2 Marks]
current of 1 A. Its output resistance and load Q.10 The circuit shown in the figure is best described
regulation, respectively are as a
(a) 5 and 20% (b) 25 and 20%
(c) 5 and 16.7% (d) 25 and 16.7%
[EC-1999 : 2 Marks]
Output
Q.8 The transistor shunt regulator shown in the
figure has a regulated output voltage of 10 V,
when the input varies from 20 V to 30 V. The
(a) bridge rectifier
relevant parameters for the Zener diode and the
transistor are: VZ = 9.5, VBE = 0.5 V, = 99. (b) ring modulator
Neglect the current through R B. Then the (c) frequency discriminatory
maximum power dissipated in the Zener diode (d) voltage doubler
(PZ) and the transistor (PT) are: [EC-2003 : 1 Mark]
20 Q.11 The output voltage of the regulated power
IZ IC supply shown in the figure is

VZ
Vin = 20-30 V Vo = 10 V +
+
VBE – 1k
RB
+
15 DC
Vz = 3 V
unregulated –
(a) PZ = 75 mW, PT = 7.9 W power source 40 k
(b) PZ = 85 mW, PT = 8.9 W Regulated
20 k
(c) PZ = 95 mW, PT = 9.9 W DC output
–
(d) PZ = 115 mW, PT = 11.9 W
[EC-2001 : 2 Marks] (a) 3 V (b) 6 V
Q.9 A Zener diode regulator in the figure is to be (c) 9 V (d) 12 V
designated to meet the specifications: IL = 10 mA, [EC-2003 : 2 Marks]
Vo = 10 V and Vin varies from 30 V to 50 V. The
Q.12 In the voltage regulator shown in the figure, the
Zener diode has Vz = 10 V and Izk (knee current)
load current can vary from 100 mA to 500 mA.
= 1 mA. For satisfactory operation.
 56 Electronics Engineering Analog Electronics

Assuming that the Zener diode is ideal (i.e., the Q.15 For the circuit shown below, assume that the
Zener knee current is negligibly small and Zener Zener diode is ideal with a breakdown voltage
resistance is zero in the breakdown region), the of 6 Volts. The waveform observed across R is
value of R is 6V
R
+

+ 12 sin t R VR
Variable load
12 V 5V 100 to 500 mA
– –

6V
(a) 7 (b) 70 (a)
70
(c) (d) 14 6V
3
[EC-2004 : 2 Marks] (b)
Q.13 In a full wave rectifier using two ideal diodes,
Vdc and Vm are the dc and peak values of the –12 V

voltage respectively across a resistive load. If

12 V
PIV is the peak inverse voltage of the diode, then
the appropriate relationship for this rectifier are (c)
Vm
(a) Vdc = , PIV = 2 Vm
–6 V
V
(b) Vdc = 2 m , PIV = 2 Vm (d)
–6 V
Vm [EC-2006 : 2 Marks]
(c) Vdc = 2 , PIV = Vm

V Common Data for Questions (16 and 17):

(d) Vdc = m , PIV = Vm
A regulated power supply, shown in figure below, has
[EC-2004 : 2 Marks] an unregulated input (UR) of 15 Volts and generates a
regulated output Vout. Use the component values
Q.14 The Zener diode in the regulator circuit shown shown in the figure.
in the figure has a Zener voltage of 5.8 Volts
15 V(UR)
and a Zener knee current of 0.5 mA. The Q1
maximum load current drawn from this circuit
ensuring proper functioning over the input 12 k 10
1k
voltage range between 20 and 30 Volts, is
1k +
–

Vi V1 = 5.8 V Load
20-30 6V 24 k

(a) 23.7 mA (b) 14.2 mA

(c) 13.7 mA (d) 24.2 mA Q.16 The power dissipation across the transistor
[EC-2005 : 2 Marks] shown in the figure is
 GATE Previous Years Solved Paper 57

(a) 4.8 Watts (b) 5.0 Watts Q.19 For the Zener diode shown in the figure, the
(c) 5.4 Watts (d) 6.0 Watts Zener voltage at knee is 7 V, the knee current is
[EC-2006 : 2 Marks] negligible and the Zener dynamic resistance is
10 . If the input voltage (Vi) range is from 10 to
Q.17 If the unregulated voltage increases by 20%, the 16 V, the output voltage (Vo) ranges from
power dissipation across the transistor Q1
200
(a) increases by 20%
+
(b) increases by 50%
(c) remains unchanged Vi Vo
(d) decreases by 20%
–
[EC-2006 : 2 Marks]

Q.18 The correct full wave rectifier circuit is (a) 7.00 to 7.29 V (b) 7.14 to 7.29 V
(c) 7.14 to 7.43 V (d) 7.29 to 7.43 V
[EC-2007 : 2 Marks]

Q.20 In the following limiter circuit, an input voltage

(a) Input Vi = 10 sin100 t is applied. Assume that the
Output diode drop is 0.7 V when it is forward biased.
The Zener breakdown voltage is 6.8 V.
1k

D1

Vi D2 Vo
Z 6.8 V
(b) Input

Output
The maximum and minimum values of the
output voltage respectively are
(a) 6.1 V, –0.7 V (b) 0.7 V, –7.5 V
(c) 7.5 V, –0.7 V (d) 7.5 V, –7.5 V
[EC-2008 : 1 Mark]

Input Q.21 In the circuit below, the diode is ideal. The

(c)
voltage V is given by
Output
1 1
+ V –

Vi 1A

(d) Input

Output
(a) min (Vi , 1) (b) max (Vi , 1)
(c) min (–Vi , 1) (d) max (–Vi , 1)
[EC-2009 : 2 Marks]
[EC-2007 : 1 Mark]
 58 Electronics Engineering Analog Electronics

Statement for Linked Answer Questions (22 and 23):

In the circuit shown below, assume that the voltage
drop across a forward biased diode is 0.7 V. The thermal 100
voltage Vt = kT/q = 25 mV. The small signal input ILoad
10 V
vi = Vp cos( t) where Vp = 100 mV.
9900 VZ = 5 V RL

12.7 V

IDC + IAC VDC + VAC

(a) 125 and 125 (b) 125 and 250
Vi (c) 250 and 125 (d) 250 and 250
[EC-2013 : 2 Marks]

Q.26 A voltage 1000 sin t volts is applied across YZ.

Assuming ideal diodes, the voltage measured
across WX (in Volts), is
Q.22 The bias current IDC through the diodes is
(a) 1 mA (b) 1.28 mA
(c) 1.5 mA (d) 2 mA 1k
[EC-2011 : 2 Marks] W Y X

Q.23 The ac output voltage vac is Z

(a) 0.25 cos( t) mV (b) 1 cos( t) mV
(c) 2 cos( t) mV (d) 22 cos( t) mV
1k
[EC-2011 : 2 Marks] + –

Q.24 The diodes and capacitors in the circuit shown

are ideal. The voltage v(t) across the diode D1 is (sin t + sin t )
(a) sin t (b)
2
v (t )
(sin t sin t )
C1 D2 (c) (d) 0 for all t
2
+
cos( t) [EC-2013 : 2 Marks]
D1 C2
– Q.27 In the figure, assume that the forward voltage
drops of the PN diode D1 and schottky diode D2
are 0.7 V and 0.3 V, respectively. If ON denotes
conducting state of the diode and OFF denotes
(a) cos( t) – 1 (b) sin( t) non-conducting state of the diode, then in the
(c) 1 – cos( t) (d) 1 – sin( t) circuit.
[EC-2012 : 1 Mark]
1k 20
Q.25 In the circuit shown below, the knee current of
the ideal Zener diode is 10 mA. To maintain 5 V
10 V D1 D2
across RL, the minimum value of RL in and
the minimum power rating of the Zener diode
(in mW) respectively, are
 GATE Previous Years Solved Paper 59

(a) Both D1 and D2 are ON. (a) –0.3 V < Vi < 1.3 V
(b) D1 is ON and D2 is OFF. (b) –0.3 V < Vi < 2 V
(c) Both D1 and D2 are OFF. (c) –1.0 V < Vi < 2.0 V
(d) D1 is OFF and D2 is ON. (d) –1.7 V < Vi < 2.7 V
[EC-2014 : 1 Mark] [EC-2014 : 1 Mark]

Q.28 The diode in the circuit shown has Von = 0.7 V Q.31 For the circuit with ideal diodes shown in the
but is ideal otherwise. If Vi = 5 sin( t) Volts, the figure, the shape of the output (vout) for the given
minimum and maximum values of Vo (in Volts) sine wave input (vin) will be
are, respectively
R1
Vi Vo T
0 0.5 T
1k
R2 1k

2V
+
Vin Vout

(a) –5 and 2.7 (b) 2.7 and 5 –

(c) –5 and 3.85 (d) 1.3 and 5 –

[EC-2014 : 2 Marks]

Q.29 The figure shows a half-wave rectifier. The

diode D is ideal. The average steady-state
(a) T
current (in Amperes) through the diode is 0 0.5 T
approximately ______ .

D
0.5 T
10 sin t 100 R C 4 mF (b) 0 T
f = 50 Hz

[EC-2014 : 1 Mark] 0.5 T

0 T
(c)
Q.30 Two silicon diodes, with a forward voltage drop
of 0.7 V, are used in the circuit shown in the
figure. The range of input voltage Vi for which
the output voltage Vo = Vi, is (d)
0 T
0.5 T
R
[EC-2015 : 1 Mark]
+ +
D1 D2
Q.32 In the circuit shown below, the Zener diode is
Vi Vo ideal and the Zener voltage is 6 V. The output
–1 V 2V voltage, Vo (in Volts) is ______ .
– –
 60 Electronics Engineering Analog Electronics

Q.36 In the circuit shown, assume that the diodes D1

1k and D2 are ideal. The average value of voltage
+
10 V 1k Vo
Vab (in Volts), across terminals ‘a’ and ‘b’ is
– ________ .

[EC-2015 : 1 Mark] D1 D2
10 k
6 sin( t) + –
Q.33 If the circuit shown has to function as a a b
clamping circuit, then which one of the Vab
10 k 20 k
following conditions should be satisfied for the
sinusoidal signal of period T ?
[EC-2015 : 2 Marks]
+ –
C
Q.37 The figure shows a half-wave rectifier with a
V R 475 µF filter capacitor. The load draws a
constant current Io = 1 A from the rectifier. The
figure also shows the input voltage Vi, the output
(a) RC << T (b) RC = 0.35 T voltage VC and the peak-to-peak voltage ripple
(c) RC T (d) RC >> T u on VC. The input voltage Vi is triangle wave
with an amplitude of 10 V and a period of 1 ms.
[EC-2015 : 1 Mark]

Q.34 The diode in the circuit given below has

VON = 0.7 V but is ideal otherwise. The current
+
(in mA) in the 4 k resistor is ______ . Vi 475 µF VC Io = 1 A
–

2k 3k

D 1k +10 V Vi
1 mA
0 t

4k 6k

–10 V
VC
[EC-2015 : 2 Marks] u

Q.35 In the circuit shown, assume that diodes D1 and 0 t

D2 are ideal. In the steady-state condition the The value of the ripple u (in Volts) is ______ .
average voltage Vab (in Volts) across the 0.5 µF [EC-2016 : 2 Marks]
capacitor is ______ .
Q.38 Assume that the diode in the figure has
1 µF
Von = 0.7 V, but is otherwise ideal.

D1 D2
50 sin( t) R1

2k
0.5 µF i2

2V
b –V + a R2 6k
ab

[EC-2015 : 1 Mark]
 GATE Previous Years Solved Paper 61

The magnitude of the current i2 (in mA) is equal (a) D1 only (b) D2 only
to _______ . (c) Both D1 and D2 (d) None of D1 and D2
[EC-2016 : 1 Mark] [EC-2016 : 2 Marks]
Q.39 The diodes D1 and D2 in the figure are ideal and Q.41 The output Vo of the diode circuit shown in the
the capacitors are identical. The product RC is figure is connected to an averaging DC
very large compared to the time period of the ac voltmeter. The reading on the DC voltmeter in
voltage. Assuming that the diodes do not volts, neglecting the voltage drop across the
breakdown in the reverse bias, the output diode, is ________ .
voltage Vo (in Volt) at the steady-state is _____ .
+

+ 10 sin t
D1 1k Vo
f = 50 Hz
C
10 sin t –
R Vo
[EC-2017 : 1 Mark]
AC
C
Q.42 In the figure, D1 is a real silicon pn-junction
D2
– diode with a drop of 0.7 V under forward bias
condition and D 2 is a Zener diode with
[EC-2016 : 1 Mark] breakdown voltage of –6.8 V. The input Vin(t) is
a periodic square wave of period T, whose one
Q.40 The I-V characteristics of the Zener diodes D1
and D2 are shown in Fig. (i). These diodes are period is shown in the figure.
used in the circuit given in Fig. (ii). If the supply Vi(t)
voltage is varied from 0 to 100 V, then breakdown +14 V
occurs in
T
I 0
t(sec)
–80 V –70 V
V
–14 V

10 µF

D1 D2 D1
10 V o (t )

D2
Fig. (i)

Assuming 10 << T, where is the time constant

D1
of the circuit, the maximum and minimum
0 - 100 V values of the output waveform are respectively.
(a) 7.5 V and –20.5 V
D2 (b) 6.1 V and –21.9 V
(c) 7.5 V and –21.2 V
Fig. (ii) (d) 6.1 V and –22.6 V [EC-2017 : 1 Mark]
 62 Electronics Engineering Analog Electronics

Q.43 A DC current of 26 µA flows through the circuit Q.45 In the circuit shown, Vs is a square wave of
shown. The diode in the circuit is forward period T with maximum and minimum values
biased and it has an ideality factor of one. At of 8 V and –10 V, respectively. Assume that the
the quiescent point, the diode has a junction diodes is ideal and R1 = R2 = 50 . The average
capacitance of 0.5 nF. Its neutral region value of VL is _____ Volts. (Rounded off to one
resistances can be neglected. Assume that the decimal place).
room temperature thermal equivalent voltage is
26 mV.
+8 V

5 sin( t) mV 0
T/2 T
100

V
–10 V

R1
For = 2 × 106 rad/sec, the amplitude of the
small signal component of diode current (in µA,
correct to one decimal place) is _____ .
+
[EC-2018 : 2 Marks] +
Vs R2 VL
Q.44 The circuit shown in the figure is used to provide
–
regulated voltage (5 V) across the 1 k resistor. –
Assume that the Zener diode has a constant
reverse breakdown voltage for a current range, [EC-2019 : 1 Mark]
starting from a minimum required Zener
Q.46 In the circuit shown, Vs is a 10 V square wave of
current, IZmin = 2 mA to its maximum allowable
period. T = 4 ms with R = 500 and C = 10 µF.
current. The input voltage V1 may vary by 5%
The capacitor is initially uncharged at t = 0, and
from its nominal value of 6 V. The resistance of
the diode is assumed to be ideal. The voltage
the diode in the breakdown region is negligible.
across the capacitor (VC) at 3 ms is equal to _____
R Volts (rounded off to one decimal place).

VI 1k +10 V
5V
0
T/2 T

–10 V
The value of R and the minimum required
t=0
power dissipation rating of the diode,
respectively, are R

(a) 186 and 10 mW +

(b) 100 and 40 mW

Vs C VC
(c) 100 and 10 mW
(d) 186 W and 40 mW –
[EC-2018 : 2 Marks]
[EC-2019 : 2 Marks]
 GATE Previous Years Solved Paper 63

Q.47 In the circuit shown, the breakdown voltage and TOFF = 1 µs is applied to the circuit shown in the
the maximum current of the Zener diode are 20 V figure. The diode D1 is ideal.
and 60 mA, respectively. The values of R1 and 20 nF
RL are 200 and 1 k , respectively. What is the +
range of Vi that will maintain the Zener diode
in the ‘ON’ state? Vin 500 k D1 Vo

R1
–
Vi RL
The difference between the maximum voltage
and minimum voltage of the output waveform
V0 (in integer) is _______ V.
(a) 20 V to 28 V (b) 24 V to 36 V
[EC-2021 : 2 Marks]
(c) 18 V to 24 V (d) 22 V to 34 V
[EC-2019 : 2 Marks] Q.51 A circuit and the characteristics of the diode (D)
in it are shown. The ratio of the minimum to the
Q.48 In the circuit shown below, all the components
are ideal and the input voltage is sinusoidal. Vout
maximum small signal voltage gain is
The magnitude of the steady-state output Vo Vin
(rounded off to two decimal places) is _____ V. _____ (Rounded off to two decimal places).
C1 = 0.1 µF D2
2k 2k
+
+

230 V(rms) D1 C2 = 0.1 µF Vo D

V in
+
– V out 2k
– –
[EC-2020 : 1 Mark]
ID D
Q.49 A circuit with an ideal Op-amp is shown in the
figure. A pulse VIN of 20 ms duration is applied + VD –
to the input. The capacitors are initially
uncharged. 20
ID(mA)

5V
10
10 k
0
0V ( V)
0 0.7 VD
t = 0 t = 20 ms 1 µF
+12 V
[EC-2022]
VIN –
VOUT
+
1 µF ELECTRICAL EN GINEERIN G
–12 V

(GATE Previous Years Solved Papers)

The output voltage VOUT of this circuit at t = 0+
(in integer) is _____ V. Q.1 Figure shows an electronic voltage regulator.
[EC-2021 : 2 Marks] The zener diode may be assumed to require a
minimum current of 25 mA for satisfactory
Q.50 An asymmetrical periodic pulse train Vin of 10 V operations. The value of R required for
amplitude with on time TON = 1 ms and off time satisfactory voltage regulation of the circuit is,
 64 Electronics Engineering Analog Electronics

D I
R

20 V 10 V 100
Vi = Vm sin t Vi 45
= 314 rad/sec

[EE-1991 : 2 Marks]
Vm Vm
Q.2 The depletion region (or) space change region (a) (b)
50 50 2
(or) transition region in a semiconductor p-n
junction diode has Vm 2Vm
(c) (d)
(a) electronics and holes 100 2 50 2
(b) positive ions and electrons [EE-2002 : 1 Mark]
(c) positive and negative ions
Q.7 The cut-in voltage of both zener diode Dz and D
(d) negative ions and holes shown in figure is 0.7 V, while breakdown
[EE-1996 : 1 Mark] voltage of the zener is 3.3 and reverse
Q.3 As temperature is increased, the voltage across breakdown of D is 5 V. The other parameters
a diode carrying a constant current can be assumed to be the same as those of an
ideal diode. The values of the peak output
(a) increases
voltage (Vo) are
(b) decreases
(c) remains constant 1k

(d) may increase or decrease depending upon

the doping levels in the junction
[EE-1999 : 1 Mark] = 314 rad/sec 10 sin t 1k Vo

Q.4 The mobility of an electron in a conductor

expressed in terms of
(a) cm2/V-sec (b) cm/V-sec
(a) 3.3 V in the positive half cycle and 1.4 V in
(c) cm2/V (d) cm2/sec
the negative half cycle.
[EE-1999 : 1 Mark]
(b) 4 V in the positive half cycle and 5 V in the
Q.5 A diode whose terminal characteristics are negative half cycle.
related as iD = Is eV/VT, where Is is the reverse (c) 3.3 V in the both positive and negative half
saturation current and VT is thermal voltage cycle.
(= 25 mV), is biased at iD = 2 mA. Its dynamic
(d) 4 V in the both positive and negative half
resistance is
cycle.
(a) 25 (b) 12.5
[EE-2002 : 1 Mark]
(c) 50 (d) 100
[EE-2000 : 2 Marks] Q.8 In the single-phase diode bridge rectifier shown
in figure, the load resistor is R = 50 . The source
Q.6 The forward resistance of the diode shown in
voltage is V = 200 sin t, where = 2 × 50 rad/s.
figure is 5 and the remaining parameters are
The power dissipated in the load resistor R is
same as those of ideal diode. The dc components
of the source current is
 GATE Previous Years Solved Paper 65

Q.11 Assuming that the diodes are ideal in figure,

the current in diode D1 is
1k 1k

A
V
B R D2
5V D1

8V

3200 (a) 8 mA (b) 5 mA

(a) W (b) 400 W
(c) 0 mA (d) –3 mA
[EE-2004 : 2 Marks]
400
(c) W (d) 800 W
Q.12 Assume that D1 and D2 in figure are ideal diodes.
[EE-2002 : 2 Marks] The value of current I is,

Q.9 A voltage signal 10 sin t is applied to the circuit

with ideal diodes, as shown in figure. The D1 2k
maximum and minimum values of the output
waveform Vout of the circuit are respectively. 1 mA
(DC)
I
10 k
2k
+ D2

Vin Vout
(a) 0 mA (b) 0.5 mA
4V 4V
(c) 1 mA (d) 2 mA
10 k [EE-2005 : 1 Mark]
–
Q.13 What are the states of the three ideal diodes of
(a) +10 V and –10 V (b) +4 V and –4 V the circuit shown in figure?
(c) +7 V and –4 V (d) +4 V and –7 V 1
[EE-2003 : 2 Marks]
1

Q.10 The current through the Zener diode in figure is D2

2.2 k
10 V D1 1 D3 5A
RZ = 0.1 k
IZ

+ +
10 V R1 3.5 V
VZ = 3.3 V (a) D1 ON, D2 OFF, D3 OFF
–
– (b) D1 OFF, D2 ON, D3 OFF
(c) D1 ON, D2 OFF, D3 ON
(a) 33 mA (b) 3.3 mA (d) D1 OFF, D2 ON, D3 ON
(c) 2 mA (d) 0 mA [EE-2006 : 1 Mark]
[EE-2004 : 1 Mark]
 66 Electronics Engineering Analog Electronics

Q.14 Assuming the diodes D1 and D2 of the circuit

+10 V
shown in figure to be ideal ones, the transfer
characteristics of the circuit will be 1k

Vin RL = 10
D1 6.6 V
D2 Zener diode
2
Vi Vo RL =
0

10 V 5V
(a) 0.6 W (b) 2.4 W
(c) 4.2 W (d) 5.4 W
Vo
[EE-2007 : 1 Mark]

10 Q.16 The equivalent circuits of a diode, during

(a)
forward biased and reverse biased conditions,
Vi are shown in the figure.
10

+ – + –
Vo
– + + –
(a)

(b) 5 10 k

Vi
5
10 sin t 5V Vo 1k

Vo

10
(b)

(c) If such a diode is used in clipper circuit of figure

5
given above, the output voltage (Vo) of the circuit
Vi will be
5 10

+5 V
Vo

(a) t
10 0 2
(d)
–5 V
Vi
10

10 V
[EE-2006 : 2 Marks]

Q.15 The three-terminal linear voltage regulator is (b) t

0 2
connected to a 10 load resistor as shown in
–5 V
the figure. If Vin is 10 V, what is the power
dissipated in the transistor?
 GATE Previous Years Solved Paper 67

(a) 4 V (b) 5 V
(c) 7.5 V (d) 12.12 V
+5.7 V
[EE-2010 : 1 Mark]
(c) t
0 2 Q.19 The transistor used in the circuit shown below
has a of 30 and ICBO is negligible.
–10 V

2.2 k
15 k
+5.7 V
1k D
VBE = 0.7 V
(d) t
0 2 VCE(sat) = 0.2 V

–5 V Vz = 5 V

[EE-2008 : 1 Mark]
–12 V
Q.17 In the voltage doubler circuit shown in the
If the forward voltage drop of diode is 0.7 V,
figure, the switch ‘S’ is closed at t = 0. Assuming
then the current through collector will be
diodes D1 and D2 to be ideal, load resistance to
(a) 168 mA (b) 108 mA
be infinite and initial capacitor voltages to be
zero. The steady-state voltage across capacitors (c) 20.54 mA (d) 5.36 mA
C1 and C2 will be [EE-2011 : 2 Marks]

V C1 Q.20 A clipper circuit is shown below.

S
+ –
1k
C1 D2
t=0 +
+ D
Vz = 10 V

5 sin t D1 C2 VC2 RL
Vi Vo
–
5V
–

(a) VC1 = 10 V, VC2 = 5 V Assuming forward voltage drops of the diodes

(b) VC1 = 10 V, VC2 = –5 V to be 0.7 V, the input-output transfer
(c) VC1 = 5 V, VC2 = 10 V characteristics of the circuit is
(d) VC1 = 5 V, VC2 = –10 V Vo
[EE-2008 : 2 Marks]

Q.18 Assuming that the diodes in the given circuit (a) 4.3
are ideal, the voltage Vo is Vi
4.3
10 k

Vo
10 k 10

10 V Vo 15 V
(b)
10 k 4.3
Vi
4.3 10
 68 Electronics Engineering Analog Electronics

Vo (a) 125 and 125 (b) 125 and 250

(c) 250 and 125 (d) 250 and 250
–0.7 [EE-2013 : 2 Marks]
(c) Vi
–0.7 Q.23 A voltage 1000 sin t Volts is applied across YZ.
Assuming ideal diodes, the voltage measured
across WX (in Volts), is
Vo

10
1k

(d) W Y X
Z
–5.7
Vi
10
–5.7
+ –
1k
[EE-2011 : 2 Marks]
(sin t + sin t )
(a) sin t (b)
Q.21 The i-v characteristics of the diode in the circuit 2
given below are: (sin t sin t )
(c) (d) 0 for all t
v 0.7 2
A, v 0.7 V
i = 500 [EE-2013 : 2 Marks]
0 A, v < 0.7 V
Q.24 The sinusoidal ac source in the figure has an
The current in the circuit is
rms value of 20 / 2 V. Considering all
1k
possible values of RL, the minimum value of Rs
i (in ) to avoid burn out of the Zener diode is
+
10 V +
______ .
–
D v
–
Rs

(a) 10 mA (b) 9.3 mA

(c) 6.67 mA (d) 6.2 mA 20 5V RL
V 1/4 W
[EE-2012 : 1 Mark] 2

Q.22 In the circuit shown below, the knee current of

the ideal Zener diode is 10 mA. To maintain 5 V
across RL, the minimum value of RL in and
the minimum power rating of the Zener diode [EE-2014 : 1 Mark]
(in mW), respectively are
Q.25 Assuming the diodes to be ideal in the figure,
for the output to be clipped, the input voltage vi
100 must be outside the range.

Iload 10 k
10 V

Vz = 5 V RL
Vi 10 k Vo

1V 2V
 GATE Previous Years Solved Paper 69

(a) –1 V to –2 V (b) –2 V to –4 V is biased so that voltage, V > 0 and current, I < 0.

(c) +1 V to –2 V (d) +2 V to –4 V If you had a design this circuit to transfer
[EE-2014 : 2 Marks] maximum power from the current source (I1) to
a resistive load (not shown) at the output, what
Q.26 A non-ideal diode is biased with a voltage of values R1 and R2 would you choose?
–0.03 V, and a diode current of I1 is measured.
R1 I
The thermal voltage is 26 mV and the ideality
factor for the diode is 15/13. The voltage, (in V), +

at which the measured current increases to 1.5I1 I1 D R2 V

is closest to
(a) –4.50 (b) –0.09 I –
(c) –0.02 (d) –1.50
(a) Small R1 and small R2
[EE-2020 : 2 Marks]
(b) Large R1 and large R2
Q.27 Consider the diode circuit shown below. The (c) Small R1 and large R2
diode, D, obeys the current-voltage characteristic, (d) Large R1 and small R2
VD [EE-2020 : 2 Marks]
ID = I s exp 1
nVT
where n > 1, VT > 0, VD is the voltage across the
diode and ID is the current through it. The circuit

Electronics & Electrical Engineering

GATE Previous Years Solved Paper

A n swe rs & Expl a n a t i o n s

Answers
EC Diodes Applications

1. (c) 2. (a) 3. (a) 4. (c) 5. (d) 6. (d) 7. (b) 8. (c)

9. (a) 10. (d) 11. (c) 12. (d) 13. (b) 14. (c) 15. (b) 16. (d)
17. (b) 18. (c) 19. (c) 20. (c) 21. (a) 22. (a) 23. (b) 24. (a)
25. (b) 26. (d) 27. (d) 28. (c) 29. (0.10) 30. (d) 31. (c) 32. (5)
33. (d) 34. (0.6) 35. (100) 36. (5) 37. (2.105) 38. (0.25) 39. (0) 40. (a)
41. (3.183) 42. (a) 43. (6.40) 44. (b) 45. (–3) 46. (3.3) 47. (b) 48. (650.40)
49. (–12) 50. (10) 51. (0.75)
70 Electronics Engineering Analog Electronics

Solutions
EC Diodes Applications

1. (c) Vo
10 6 4
I= = = 80 mA
50 50
I= IZ + IL
5.9 V
= IZmin + ILmax
IZmin = 5 mA
80 = 5 + ILmax 3. (a)
ILmax = 75 mA Ebers Moll model is a composite model and is
VL used to predict the operation of BJT all of its
ILmax =
Rmin possible modes.
VL 6 4. (c)
Rmin = = 3
I L max 75 × 10
Current through 50 resistance = I
= 80
9 6 3
I= = = 60 mA
2. (a) 50 50
Given that,
Vo
IZmin = 5 mA
5.9 PZmax = IZmaxVz = 300 mW
0 3
300 × 10
–5.9
IZmax =
Vz
3
DA DB 300 × 10
= = 50 mA
6
4.1 V 4.1 V I= IZmin + ILmax
10 sin314t 10 k Vo
= IZmax + ILmin
60 = 50 + ILmin
ILmin = 10 mA
60 = 5 + ILmax
Case-1: During +ve half cycle
ILmax = 55 mA
Diode DA is forward bias, so DA is short-circuit.
Diode DB is reverse bias, so DB is in conducting 5. (d)
state when Vi > 4.1 V. A resistance: For small signal ac operation, a
Vo practical forward biased diode can be modeled
5.9 V as a resistance.

6. (d)
A four diode bridge rectifier uses the smaller
size of transformer, which is less expensive
Case-2: During –ve half cycle
transformer and these rectifiers are suitable for
Diode DB is forward bias, so DB is short-circuit.
higher voltage applications, because of low PIV
Diode DA is reverse bias, so DA is in conducting
rating required of each diode.
state when Vi > 4.1 V.
 GATE Previous Years Solved Paper 71

7. (b) Vin Vo
IZ + IL
VNL VFL R
Regulation = when, Vin = 30 V
VFL
30 10
30 25 1 (10 + 1) mA
= = = 20% R
25 5
20
VDCNL VDCFL 11 mA
Ro = =5 R
IDC
R 1818
8. (c) 11. (c)
I1 20 As voltage at non-inverting terminal is 3 V due
to zener diode, voltage at inverting terminal will
IZ IC
be 3 V because of virtual ground.
IB 3 3
Vin = 20-30 V
+
Vo = 10 V So, current in 20 k is = mA
20 k 20
RB VBE –
IE 3
Vo = × 60 k =9V
20 k
Vinmax Vo
I1max = 12. (d)
20
I = IZ + IL
30 10 = IZmin + ILmax
I1 = = 1 A (i.e. when, IZ = 0)
20
= 0 + 500 mA
IE = IC + IZ ...(i)
Vin Vz 12 5
IB = IZ (as no current flows in RB) R= =
I 500 mA
I I
= C = C = 14
I B IZ
IC = IZ 14. (c)
From equation (i), I1 1k I2
IE = IZ + IZ = (99 + 1) IZ
IE = 100 IZ IZ

I1 = IE = 100 IZ 20-30 5.8 V Load

I1 1
IZ = = = 0.01 A
100 100
PZ = VZ IZ = 9.5 × 0.01 = 95 mW
VL = 5.8 V
IC = 99IZ = 99 × 0.01 = 0.99 A Maximum load current will be drawn, when
PC = VC IC = 10 × 0.99 = 9.9 W Vi = Vmin = 20 V
9. (a) 20 5.8
= = IL + IZ
1k
R
14.2 mA = IL + IZ
+
IL
IZ IL = 14.2 mA – 0.5 mA
Vin Vo RL = 13.7 mA
DZ

–
72 Electronics Engineering Analog Electronics

15. (b) 20. (c)

Zener diode works as normal diode is FB. For the positive half of Vi ,
So, when Vin < 0, VR = Vin D1 is forward biased and Zener diode is in
when 0 < Vin < 6, Diode is OFF and VR = 0 breakdown stage,
when Vin > 6, Diode conducts and VR = Vin Vo = 0.7 + 6.8 = 7.5 V
For the negative half of Vi , D2 is forward biased,
16. (d)
Vo = –0.7 V
15 V
Q1 22. (a)
+
For d.c. biasing a.c. will be short-circuited,
1k 12 k 12 k
Vout 9900
+ –
+
–
(6 V)

6V 24 k VD = 4 × 2.7
12.7 V
= 2.8

Volt across 24 = 6 V due to virtual ground

concept. So volt across 12 is 13 V, –

Vout = V12 + V24

= 3+6=9V 12.7 2.8
IDC = = 1 mA
VCE = 15 – Vout 9900
= 15 – 9 = 6 V
23. (b)
9V 9V
IC = + =1A For a.c. analysis diode will be replaced by its
12 36
dynamic resistance,
P = VCE IC = 6 V × 1 A
VT 1 × 25 mV
P = 6 Watts rd = =
I 1 mA
17. (b) = 25
New unregulated voltage = 18 V vi
(vo)ac = × 100
VCE = 18 – 9 = 9 V 9900 + 100
IC = 1 A vp
vi
P = 9 × 1 = 9 Watts = = cos t
100 100
9 6 (vo)ac = 1 cos( t) mV
% increase = × 100 = 50%
6
24. (a)
19. (c)
It is voltage doubler circuit in which C1 will be
V Vz charged to maximum value of input that is 1 V.
Vo = in rz + Vz
R + rz So, v(t) = (cos t – 1) according to KVL.
If Vin = 10 V,
25. (b)
10 7
Vo = × 10 + 7 = 7.14 V
200 + 10 Vin Vz 10 5
I= = = 50 mA
If Vin = 15 V, R 100
16 7 Vz Vz
Vo = × 10 + 7 = 7.43 V RLmin = = = 125
200 + 10 I L max I IZ min
 GATE Previous Years Solved Paper 73

Minimum power rating of Zener diode, Vin 0.7 2

Vo = × 1 k + 0.7 + 2
Pz = Vz IZmax 1k +1k
IZmax = 50 mA
5 2.7
Pz = 5 × 50 = 250 mW = + 2.7 = 3.85 V
2
26. (d)
29. Sol.
Case-1: When VYZ is positive.
The average current through the diode is
Then all the four diodes are reverse bias.
approximate,
So, Vw = Vx = 0
Vp 10
Vwx = 0 V iD(avg) = = 0.10 A
R 100
Case-2: When VYZ is negative.
So, all the diodes will be short-circuit, 30. (d)
Vw = Vx For case-(i): Vi < –1.7
Vwx = Vw – Vx D1 ON
= Vw – Vw = 0 D2 OFF
Vwx = 0
So, Vwx = 0 for all t R
+ +
27. (d)
Consider D1 OFF and D2 ON then, Vi Vo
–1 V
1k I 1k
– –

+ Vo = –1.7 V
10 V VD1 0.3 V For case-(ii):
–
–1.7 < Vi < 2.7
D1 OFF
Apply KVL, D2 OFF
10 = 1000I + 20I + 0.3 R
9.7 + +
I= = 9.5 mA
1020
Vi Vo
Now, we calculate VD of
1

10 = 9.5 + VD1 – –

VD1 = 0.5 V Vo = Vi

31. (c)
Since, VD1 < 0.7 V, D1 is in OFF state i.e. our
The circuit can be redrawn as:
assumption is correct and hence (d) is the correct
D1
option. a d
vin +
vout
–
28. (c) Vo
R t
t
If, Vin = –5 V Diode is off D2
+
–
Vo = Vin = –5 V b c

If, Vin = 5 V Diode is on

74 Electronics Engineering Analog Electronics

• During positive pulse, both diodes are 37. Sol.

forward biased. 3
IDC T 1 × 1 × 10
• During negative pulse, both diodes are Vripple = = 6
= 2.105 Volts
C 475 × 10
reverse biased.
So, Vo = 0 V 38. Sol.
id
32. Sol.
Zener is not in breakdown region.
i1
1 VA
Hence, Vo = 10 × =5V 2k
2 i2

2V
34. Sol. 6k
The bridge is balanced bridge, so diode will be
OFF.
Let diode: ON
Current through 4 k resistor can be obtained
VA = 2 – 0.7 = 1.3 V
by applying current division rule.
1.3
i2 =
6k
2k 3k 0.7
i1 =
2k
1 mA i d = i2 – i1
i
1.3 0.7
4k 6k = mA mA = ve
6 2
Diode is OFF:
Current through 4 k resistor is 0.6 mA.

35. Sol.
2k
The circuits work as a voltage doubler. i2
Vab = 2 × 50 = 100 2V
6k
36. Sol.
During positive cycles,
2V
V i2 = = 0.25 mA
V1 = in 2 k +6 k
2
During negative cycles, 39. Sol.
Vin During first positive quarter cycle both diodes
Vo =
3 D1 and D2 conduct and at t = T/4 both will be
Vo OFF.

Vm/2 +
Vm/3
10 V
t 10 sin t – +
R Vo = 0
Vm 1 Vm 1 6 6 – –
VDC = + = + =5V 10 V
2 3 2 3 +
 GATE Previous Years Solved Paper 75

Both the capacitors will charge to 10 V as shown

1 (1000) ( j1000)
is above figure and Vo = 0 in steady-state. rd =
j Cj 1000 j 1000
41. Sol.
j(1 + j )
The given circuit is a halfwave rectifier. = k
2
Voltmeter reads the average value of Vo.
1
Vm = (1 j ) k
Average value of Vo = 2
= (500 – j500)
Vm = peak value of the applied sine wave = 10 V Z = 600 – j500
10
So, reading of meter = V = 3.183 V Z = 100 36 + 25

= 100 61
42. (a)
Its a negative clamper with Vref = 6.8 V Vm 5 mV
Im = =
In steady-state, Z 100 61
Vcap = 14 – 0.7 – 6.8 = 6.5 V 50
= µA = 6.40 µA
Vomax = Vin max – Vcap 61
= 14 – 6.5 V
Vo min = Vin in – Vcap 44. (b)
= –14 – 6.5 = –20.5 V VI = 6 V ± 5%
= 6 V ± 0.3 V
43. Sol.
= 5.7 V to 6.3 V
The small-signal equivalent model of the given
5V
circuit can be drawn as shown below: IL = = 5 mA
1k
Is(min) = IL + IZ(min)
Cj
= 5 mA + 2 mA = 7 mA
i(t)
rd VI Vz
Is =
5 sin( t) mV 100 R
VI (min) Vz
Is(min) = = 7 mA
R
Given that, = 2 × 106 rad/sec 5.7 5
So, R= k
Cj = 0.5 nF 7
IDC = 26 µA 700
= = 100
VT = 26 mV 7
= 1 When R = 100 ,
VT 26 mV 6.3 5
So, rd = = =1k A = 13 mA
I DC 26 µA Is(max) =
100
1 1 Iz(max) = Is(max) – IL
= 6 9
Cj 2 × 10 × 0.5 × 10 = 13 mA – 5 mA
= 1k = 8 mA
So, total impedance of the circuit will be Pz(min) = Vz Iz(max)
= (5 × 8) mW
1
Z= rd + 100 = 40 mW
j Cj
76 Electronics Engineering Analog Electronics

45. Sol. For 2 ms < t < 4 ms, diode is OFF and capacitor
When, Vs = 8 V Diode is in reverse bias, has no path to discharge.
50
Hence, at t = 3 ms, Vcap = 3.3 V

47. (b)
+
Vs 50 VL R1 = 200
– +
I1 IZ IL

Vi RL = 1 k Vo
8 × 50
VL = =4V
50 + 50
–
If Vs = –10 V, diode is in forward bias,
Vz = 20 V
IZmax = 60 mA
+
Vs 50 VL
Set zener diode be OFF,
– Vi × 1 Vi
Vo = =
0.2 + 1 1.2
Average value of VL Zener diode can become ON i.e. it goes into
breakdown, when
Area
= Vi
Time period > 20 V
1.2
4 × 0.5T + ( 10) × 0.5T
= = –3 V Vi > 24 V
T
When Zener diode is in breakdown region,
46. Sol. Vi 20 Vi 20
I1 = = mA
vi 0.2 k 0.2

+10 V Vo 20
IL = = = 20 mA
RL 1 k
0 t
2 ms 4 ms
Vi 20
–10 V Iz = I1 IL = 20
0.2
vcap For safe operation,
10 V
Iz Izmax
Vi 20
20 60
0 t 0.2
2 ms 4 ms
Vi 36 V
= RC = 500 × 10 × 10–6 Hence, 24 < Vi < 36 V
= 5 ms
t 48. Sol.
0<t< ; Vcap = Vf + (Vi – Vf ) e–t/
2 Voltage doubles,
= 10 + (0 – 10) e–t/RC Vo = 2 Vm
At t = 2 msec,
= 2 × 230 2
2 × 10 3 650.4 V
5 × 10 3
Vcap = 10 10 e
= 3.296 V 3.3 V
 GATE Previous Years Solved Paper 77

49. (–12) 20 nF
+ –
+ +
5V
10 k
10 V 500 k D1 Vo = 0

0 20 m 1 µF
+12 V – –
VIN –
VOUT
+ and VC (Voltage across capacitor) = 10 V ...(1)
1 µF
–12 V
Case (ii) : If Vin = 0 V D1 is OFF.
20 nF

+ + – +
5V VC
10 k
Vi 500 k D1 Vo
iC
0 20 m
C = 2 µF +12 V – –
VIN –
0V VOUT
iC + The duration of input pulse with amplitude 0 V
–12 V is, TOFF = 1 µsec
and discharge time for capacitor,
Tdischarge = 20 nF × 500 k
0 Vo dV = 10 msec
iC = = C in
R dt i.e., Tdischarge >>TOFF
d Vo = Vi – VC
Vo = RC Vin
dt = 0 V – 10 V = –10 V ...(2)
= –RC [Slope of input Vin] Note : The difference between maximum voltage
= –RC [ ] and minimum voltage of the output waveform
= –Vsat = 0 – (–10 V)
= –12 V = 10 V ...(3)
vi
50. (10)
10 V TOFF
Given: Vin = 10 V TON = 1 ms
Asymmetrical periodic pulse train, t
0
TON = 1 m-sec vo
and TOFF = 1 µsec 1 µs
t
Diode is ideal, 0
–10 V
20 nF
+
51. (0.75)
Vin 500 k D1 Vo When diode is OFF :
I 2k 2k

Vin
Case (i) : If Vin = 10 V D1 is ON. Vout
2k
78 Electronics Engineering Analog Electronics

Vo = 4I; Vi = 6I (Vo 0.7)

Vi = 0.7 + (4 k )
Vo 4 2 (2 k )
Av = = =
Vi 6 3 = 0.7 + 2Vo – 1.4
When diode is ON, voltage drop across diode is Vi + 0.7
0.7 V. Vo =
2
2k 2k Vo 1
I Av = =
Vi 2
I
+
Maximum voltage gain,
Vin 0.7 V 2k 2
Vout Av =
3
– Minimum voltage gain,
1
Vo = 0.7 + 2 (k ) I Av =
2
Vi = 0.7 + (4 k ) I
( Vo / Vi )min Av 1 3 3
V 0.7 = = × = = 0.75
I= o ( Vo / Vi )max Av 2 2 4
2k

Answers
EE Diodes Applications

1. (80) 2. (c) 3. (b) 4. (a) 5. (b) 6. (a) 7. (b) 8. (b)

9. (d) 10. (c) 11. (c) 12. (a) 13. (a) 14. (a) 15. (b) 16. (a)

17. (d) 18. (b) 19. (d) 20. (c) 21. (d) 22. (b) 23. (d) 24. (300)

25. (b) 26. (b) 27. (c)

Solutions
EE Diodes Applications

1. Sol. 2. (c)
Current in 100 resistance, Charge recombination occurs in depletion
10 V region.
I100 = = 100 mA
100
3. (b)
I2 = 25 mA
dVD
Current in resistance, = 2.5 mV/°C
dT
R = 100 mA + 25 mA
= 125 mA 4. (a)
Also, 20 – 10 = 125 × 10–3 × R
Drift velocity
10 × 1000 µ=
R= = 80 Electric field
125
 GATE Previous Years Solved Paper 79

5. (b) 9. (d)

V 25 mV 10 k
rD = T = = 12.5
ID 2 mA
D1 D2
6. (a)
Vin I 4V 4V
Vm
Vav = 10 k

Vav Vav
Iav = = For +ve cycle, when Vin < –4 V
R (5 + 45)
(Vin > 4 V) D2 ON, D1 OFF, Vout = 4 V
Vav Vm where Vin < 4 V, then Vout = Vin because D2 also
= =
50 50 become (OFF).
For –ve cycle, when Vin < –4
7. (b)
D1 ON, D2 OFF:
For positive half cycle, at peak input voltage,
Vin + 4
I=
1k 4 mA 20 k
But, Vin = –ve
+ 3.3 V Vin + 4 3
I= = mA
10 V 1k Vo 20 10
– (Q for minimum output, Vin = –10 V)
0.7 V
3
Vout = × 10 k 4 = 7 V
10
So, Vo = 4 V
For negative half cycle, at peak input voltage, 10. (c)
Vz 3.5 3.3
1k 2 mA Rz = =
Iz Iz

– 0.2
Iz = = 2 mA
Vo
0.1 k
10 V 1k
+ O.C. 11. (c)
From the circuit, if ‘D1’ is ‘ON’ Kirchoff’s law is
not satisfied.
1
So, Vo = 10 × =5V D1 is OFF and D2 is ON.
1+1 I = 0 mA

8. (b) 12. (a)

Vm Current will pass through its simplest path (for)
Vrms =
2 low resistance path. D1 become forward biased
2
and D2 is reverse biased, I = 0 mA.
Vrms V2
P= = m
R 2R 13. (a)
Analyzing the circuit, we can see that D1 and
200 2
= = 400 W D2 are in forward bias and D3 is in reverse bias.
2 × 50
But no current flow through D2, because current
gets shortest path through D1.
80 Electronics Engineering Analog Electronics

14. (a) 17. (d)

Vi < 10 V D1 OFF, D2 OFF VC1
S
Vo = 10 V + –

Vi > 10 V D1 ON, D2 OFF t=0

C1 D2
Vo = Vin +
5 sin t D1 VC2 C2 RL
15. (b) –
IC1 IC2
+10 V + VCE – Vo
IR 1k IL First capacitor charge through diode (D1) upto
IB
Vmax (5 V) with shown polarities.
RL = 10
VC1 = 5 V
IZ 6.6 V Now diode D1 will be reversed biased and D2
will be forward biased and capacitor C2 will
charge in reverse direction through diode D2
V0 = Vz – VBE upto 2 Vmax.
= 6.6 V – 0.7 V = 5.9 V VC2 = –10 V

V0 5.9 18. (b)

IL = = = 0.59 A = IC
RL 10 Diode D1 is on and diode D2 is off.
VCE = Vi – V0 10
= 10 – 5.9 = 4.1 V So, V0 = 10 × =5V
10 + 10
PQ = VCE × IC
= 4.1 × 0.59 = 2.4 W 19. (d)

16. (a) 0 ( 12) 0.2

IC(sat) =
RC
10 k P
11.8
= = 5.3636 mA
2.2 k
10 sin t 10 k This is the maximum current possible in any
case.
5V

20. (c)
10 For positive voltage the waveform clips at +5.7 V.
VP = × 10 sin t
10 + 10 For negative voltage at –0.7 V, the zener diode
= 5 sin t conducts and clips out.
Since maximum voltage across at point P may Vo
be 5 V, hence voltage across the diode always
will be less than or equal to zero. So it will be 5.7 V

reversed always. –0.7

Vi
10 5.7 V
V0 = × 10 sin t –0.7
10 + 10
= 5 sin t
 GATE Previous Years Solved Paper 81

21. (d) For negative half cycle,

By applying KVL in loop,
1k 1k

i W Y X
+
10 V + Z
–
v
–

10 = 103 i + v 1k

3 v 0.7 Short circuit condition,

10 = 10 +v
500 VWX = 0
10 = 2v – 1.4 + v
24. Sol.
3v = 11.4
Is Iz + IL
v = 3.8
1 20 5
i = (10 – 3.8) × 10–3 (Putting IL = 0)
20 Rs
= 6.2 mA
R s 300
22. (b) Hence, Rsmin = 300
Is 100 Iload
25. (b)
Case-I : Vi –4 V
D2 conducts
10 V Vz = 5 V RL
D1 OFF
So, Vo = –2 V
Case-II : –4 V Vi –2 V
Both the diodes will be OFF,
10 5
Is = = 50 mA Vo = V1
100
Iload = 50 mA – 10 mA = 40 mA Case-III : Vi –2 V
5V D1 conducts
RL = = 125 D2 OFF
40 mA
Vo = –1 V
Pmin = 50 mA × 5 V = 250 mW
26. (b)
23. (d)
0.03
For positive half cycle,
15/13×26 mV
I1 = I0 e 1

1k
As, VD = –ve
W Y X ‘1’ can not be neglected in diode current
Z equation,

I1 = I0 [ e 30 mV /30 mV 1]

1k
= I0 [e–1 – 1]
= –0.64 I0 ...(i)
VWX = 0
82 Electronics Engineering Analog Electronics

27. (c)
1.5 I1 = I0 [ eVD /30 mV 1]
R1, low, R2 high,
–1.5 × 0.64I0 = I0 [ eVD /30 mV 1] R2
VD = V ×
R1 + R2
V /30 mV
–0.96 = e D 2 1
If R2 is large Vd (high).
V /30 mV
1 – 0.96 = e D R1 is less VD = V.
30 mV ln(0.04) = VD = –0.09 V So for maximum power to deliver to load R1 is
small and R2 is large.
 3 BJT Analysis

ELECTRO NICS EN GINEERIN G All capacitances are large. gm of the MOSFET =

2 mA/V, and hfa of the bipolar = 99. The overall
(GATE Previous Years Solved Papers)
transconductance gm of the composite
Q.1 The configuration of cascade amplifier is transistor is
(a) CE-CE (b) CE-CB (a) 198 mA/V (b) 9.9 mA/V
(c) CC-CB (d) CC-CC (c) 4.95 mA/V (d) 1.98 mA/V
[EC-1987 : 2 Marks] [EC-1988 : 2 Marks]
Q.2 The quiescent collector current IC of a transistor Q.5 The transistor in the amplifier shown below has
is increased by changing resistance. As a result following parameters:
(a) gm will not be affected.
hfe = 100, hje = 2 k , hre = 0, hoe = 0.05
(b) gm will decrease.
C is very large. The output impedance is
(c) gm will increase.
VCC
(d) gm will increase or decrease depending
upon bias stability. 5k
58 k
[EC-1988 : 2 Marks]
Vo
C
Q.3 Each transistor in the Darlington pair 100 nF
(see figure) below) has hFE = 100. The overall hFE
of the composite transistor neglecting the 10 k
leakage currents is 1k C

(a) 20 k (b) 16 k
B (c) 5 k (d) 4 k
[EC-1988 : 2 Marks]

Q.6 Of the four biasing circuits shown in figure. For

E
a BJT, indicate the one which can have
(a) 10000 (b) 1001 maximum bias stability?
(c) 10100 (d) 10200
V CC VCC V CC
[EC-1988 : 2 Marks]

Q.4 The amplifier circuit shown below uses a VCC

composite transistor of a MOSFET and bipolar

in cascade.

C (a) (b) (c) (d)

C
Vin [EC-1989 : 2 Marks]
 84 Electronics Engineering Analog Electronics

Q.7 For good stabilized biasing of the transistor of Q.10 If the transistor in figure has high value of
the CE amplifier of figure, we should have and VBE of 0.65 the current I flowing through
the 2 k resistance will be ______ .
+VCC
RC I
R2

6.5 k 2k
+
+ R1 R2 = RB
Vo
Vin R1 +
RE
10 V
– – 1.85 k –

RE RE
(a) << 1 (b) >> 1
RB RB
1.65 k
1k
RE RE
(c) << hFE (d) >> hFE
RB RB
[EC-1990 : 2 Marks]
[EC-1992 : 2 Marks]
Q.8 Which of the following statements are correct
for basic transistor amplifier configurations? Q.11 The bandwidth of an n-stage tuned amplifier,
with each stage having a bandwidth of B, is
(a) CB amplifiers has low input impedance and
given by
low current gain.
(b) CC amplifiers has low output impedance B B
(a) (b)
and high current gain. n n
(c) CE amplifiers has very poor voltage gain B
(c) B 2 1/ n 1 (d)
but very high input impedance. 2 1 /n
1
(d) The current gain of CB amplifier is higher [EC-1993 : 1 Mark]
than the current gain of C amplifiers.
Q.12 For the amplifier circuit of figure. The transistor
[EC-1990 : 2 Marks]
has a of 800. The mid-band voltage gain Vo/Vi
Q.9 In figure all transistors are identical and have a of the circuit will be
high value of beta. The voltage VDC is equal to
_______ . +15 V

10 V
470
200 k
5 mA 1k
4.74 µF 6.4 µF +
V DC = ?
+
Vo
Vin 100 k

– –

(a) 0 (b) < 1

(c) 1 (d) 800
[EC-1993 : 1 Mark]
[EC-1991 : 2 Marks]
 GATE Previous Years Solved Paper 85

Q.13 cut-off frequency of a bipolar junction (a) gm1 (b) 0.5 gm1
transistor (c) gm2 (d) 0.5 gm2
(a) increase with the increase in base width. [EC-1996 : 2 Marks]
(b) increase with the increase in emitter width.
Q.18 Match the following:
(c) increase with the increase in collector
(a) Cascade amplifier
width.
(b) Differential amplifier
(d) increase with decrease in base width.
(c) Darlington pair common-collector amplifier
[EC-1993 : 2 Marks]
1. does not provide current gain
Q.14 In order to reduce the harmonic distortion in an 2. is a wide band amplifier
amplifier its dynamic range has to be _____ . 3. has very low input impedance emitter
[EC-1994 : 1 Mark] amplifier
4. has very high input impedance and very
Q.15 A common emitter transistor amplifier has a
high current gain
collector current of 1.0 mA when its a base
5. provides high common mode voltage
current is 25 µA at the room temperature. It’s
rejection
input resistance is approximately equal to ___ .
[EC-1996 : 2 Marks]
[EC-1994 : 1 Mark]
Q.19 In the BJT amplifier shown in the figure is the
Q.16 A transistor having = 0.99 and VBE = 0.7 V, is
transistor is biased in the forward active region
used in the circuit of the figure is the value of
putting a capacitor across RE will
the collector current will be
+VCC
+12 V

1k RL
Rbias
+
1k
10 k +
Vout
Vin
RE
– –
1k
(a) decrease the voltage gain and decrease the
input impedance.
[EC-1995 : 1 Mark] (b) increase the voltage gain and decrease the
input impedance.
Q.17 A Darlington stage is shown in the figure is, if
(c) decrease the voltage gain and increase the
the transconductance of Q1 is gm1 and Q2 is gm2,
input impedance.
then the overall transconductance is given by
gm is (d) increase the voltage gain and increase the
input impedance.
VCC
[EC-1997 : 1 Mark]

Q1 ic Q.20 A cascade amplifier stage is equivalent to

(a) a common emitter stage followed by a
Q2
common base stage.
Vbe (b) a common base stage followed by an emitter
follower.
 86 Electronics Engineering Analog Electronics

(c) an emitter follower stage followed by a Q.24 The emitter coupled pair of BJT’s gives a linear
common base stage. transfer relation between the differential output
(d) a common base stage followed by a common voltage and the differential input voltage Vid
emitter stage. only. When the magnitude of Vid is less ‘ ’ times
[EC-1997 : 1 Mark] the thermal voltage, when ‘ ’ is
(a) 4 (b) 3
Q.21 The circuit of the figure is an example of
(c) 2 (d) 1
feedback of the following type:
[EC-1998 : 1 Mark]
+VCC
Q.25 A multistage amplifier has a low pass response
Vo
with three real poles at s = – 1, – 2 and 3. The
approximate overall bandwidth B of the
amplifier will be given by
Vi
(a) B = 1 + 2 + 3

1 1 1 1
(a) current series (b) current shunt (b) = + +
B 1 2 3
(c) voltage series (d) voltage shunt 1/3
(c) B = ( 1 + 2+ 3)
[EC-1998 : 1 Mark]
(d) B = 2 2 3
1 + 2 + 3 [EC-1998 : 1 Mark]
Q.22 From measurement of the rise time of the output
pulse of an amplifier whose input is a small
Q.26 In a series regulated power supply circuit the
amplitude square wave, one can estimate the
voltage gain Av of the “pass”, transistor satisfies
following parameter of the amplifier
the condition
(a) gain-bandwidth product
(a) Av (b) 1 << Av <<
(b) slew rate
(c) Av » 1 (d) Av << 1
(c) upper 3-dB frequency
[EC-1998 : 1 Mark]
(d) lower 3-dB frequency
[EC-1998 : 1 Mark] Q.27 In the cascade amplifier shown in the figure, if
the common-emitter stage (Q 1 ) has a
Q.23 A distorted sinusoid has the amplitude, A1, A2, transconductance gm1, and the common base
A3,...... of the fundamental, second harmonic, stage (Q2) has a transconductance gm2, then the
third harmonic, ..... respectively. The total overall transconductance g(= i o/v i) of the
harmonic distortion is cascade amplifier is
A 2 + A3 + .....
(a) Q2 Vo
A1 io

A22 + A32 + .....

(b) RL
A1 Vi Q1

A22 + A32 + .....

(c)
A12 + A22 + A32 + .....
(a) gm1 (b) gm2
( A22 + A32 + ......)
(d) gm1 gm 2
A1 (c) (d)
2 2
[EC-1998 : 1 Mark] [EC-1999 : 1 Mark]
 GATE Previous Years Solved Paper 87

Q.28 In the differential amplifier of the figure, if the (a) indeterminate since Rc is not given
source resistance of the current source IEE is (b) 1 mA
infinite, then the common mode gain is (c) 5 mA
(d) 10 mA
VCC
[EC-2000 : 2 Marks]

R R
Q.31 The current gain of a bipolar transistor drops at
high frequencies because of
(a) transistor capacitances
Vin 1 V in2 (b) high current effects in the base
(c) parasitic inductive elements
IEE (d) the early effect

–VEE
[EC-2000 : 1 Mark]

Q.32 The current gain of a BJT is

(a) zero (b) infinite gm
(a) gm ro (b)
Vin1 + Vin 2 ro
(c) indeterminate (d)
2VT gm
(c) gm r (d)
[EC-2000 : 1 Mark] r
[EC-2001 : 1 Mark]
Q.29 Introducing a resistor in the emitter of a common
emitter amplifier stabilizes the dc operating Q.33 Three identical RC coupled transistor amplifiers
point against variation in are cascaded. If each of the amplifiers has a
(a) only the temperature frequency response as shown in the figure, the
(b) only the of the transistor overall frequency response is as given in
(c) both temperature and A v dB
(d) none of the above
0
[EC-2000 : 1 Mark] –3

Q.30 In the circuit of the figure, assume that the

transistor is in the active region. It has a large f
20 Hz 1 kHz
and its base-emitter voltage is 0.7 V. The value
of Ic is Av dB

0
15 V
–3
(a)
RC
10 k f
IC 20 Hz 1 kHz

Av dB

0
5k
430 –3
(b)

f
40 Hz 0.5 kHz
 88 Electronics Engineering Analog Electronics

Av dB
(a) CB-LO, CC-MO, CE-HI
(b) CB-LO, CC-HI, CE-MO
0
(c) CB-MO, CC-HI, CE-LO
–3
(c) (d) CB-HI, CC-LO, CE-MO
[EC-2003 : 1 Mark]
f
40 Hz 1 kHz Q.36 Generally, the gain of a transistor amplifier falls
at high frequencies due to the
(a) internal capacitances of the device
Av dB
(b) coupling capacitor at the input
0 (c) skin effect
–3
(d) (d) coupling capacitor at the output
[EC-2003 : 1 Mark]
f
40 Hz 2 kHz Q.37 In the amplifier circuit shown in the figure, the
values of R1 and R2 are such that the transistor
is operating at VCE = 3 V and IC = 1.5 mA when
[EC-2002 : 1 Mark]
its is 150. For a transistor with of 200, the
Q.34 If the transistor in the figure is the saturation, operating point (VCE, IC) is
then VCC = 6 V
C R2
R1
IC

dc denotes the
B
IB dc current gain

E
(a) (2 V, 2 mA) (b) (3 V, 2 mA)
(a) Ic is always equal to dcIB. (c) (4 V, 2 mA) (d) (4 V, 1 mA)
(b) Ic is always equal to – dcIB. [EC-2003 : 2 Marks]
(c) Ic is greater than or equal to dcIB. Q.38 Assuming V CEsat = 0.2 V and = 50, the
(d) Ic is less than or equal to dcIB. minimum base current (IB) required to drive the
[EC-2002 : 1 Mark] transistor in the figure to saturation is
Q.35 Choose the correct match for input resistance of 3V
various amplifier configurations shown below: IC
Configuration: 1k
CB : Common Base
IB
CC : Common Collector
CE : Common Emitter
Input resistance:
LO : Low
(a) 56 µA (b) 140 µA
MO : Moderate
(c) 60 µA (d) 3 µA
HI : High
[EC-2004 : 1 Mark]
 GATE Previous Years Solved Paper 89

Q.39 Assuming that the of the transistor is extremely

VCC
large and VBE = 0.7 V, IC and VCE in the circuit
shown in the figure are RC RC

5V

IC
V1 V2
2.2 k
4k
RE
+
VCE –VEE

–
1k (a) increases both the differential and common
300 mode gains.
(b) increases the common mode gain only.
(c) decreases the differential mode gain only.
(a) IC = 1 mA, VCE = 4.7 V (d) decreases the common mode gain only.
(b) IC = 0.5 mA, VCE = 3.75 V [EC-2005 : 2 Marks]
(c) IC = 1 mA, VCE = 2.5 V
Q.43 The circuit using a BJT with = 50 and
(d) IC = 0.5 mA, VCE = 3.9 V VBE = 0.7 V is shown in the figure. The base
[EC-2004 : 2 Marks] current I B and collector voltage V C are
Q.40 The cascade amplifier is a multistage respectively
configuration of
20 V
(a) CC-CB (b) CE-CB
2k Vo
(c) CB-CC (d) CE-CC 430 k
[EC-2005 : 1 Mark]

Q.41 For an npn transistor connected a shown in the

10 µF
figure, VBE = 0.7 Volts. Given that reverse
saturation current of the junction at room 1k 40 µF
temperature 300°K is 10–13 A, the emitter current
is

(a) 43 µA and 11.4 volts

IC
(b) 40 µA and 16 volts
(c) 45 µA and 11 volts
(d) 50 µA and 10 volts
VBE
[EC-2005 : 2 Marks]

(a) 30 mA (b) 39 mA Common Data for Questions (44 to 46):

(c) 49 mA (d) 20 mA In the transistor amplifier circuit shown in the figure
[EC-2005 : 2 Marks] below, the transistor has the following parameters:
dc = 60, VBE = 0.7 V, hje , hfe
Q.42 In an ideal differential amplifier shown in the
The capacitance CC can be assumed to be infinite.
figure, a large value of (RE)
 90 Electronics Engineering Analog Electronics

(a) cut-off (b) saturation

12 V
(c) normal active (d) reverse active
1k
[EC-2007 : 2 Marks]
53 k
+ Q.48 The DC current gain ( ) of a BJT is 50. Assuming
5.3 k that the emitter injection efficiency is 0.995, the
VC
CC base transport factor is
Vs – (a) 0.980 (b) 0.985
(c) 0.990 (d) 0.995
[EC-2007 : 2 Marks]
In the figure above, the ground has been shown by the Statement for Linked Answer Questions (49 and 50):
symbol. In the following transistor circuit, V BE = 0.7 V,
Q.44 Under the DC conditions, the collector-to-emitter re = 25 mV/IE, and and all the capacitances are very
voltage drop is large.
(a) 4.8 Volts (b) 5.3 Volts
(c) 6.0 Volts (d) 6.6 Volts VCC = 9 V
[EC-2006 : 2 Marks] 3k
20 k
Q.45 If dc is increased by 10%, the collector-to-emitter CC 2
voltage drop
CC 1
(a) increases by less than or equal to 10%.
3k
IE
(b) decreases by less than or equal to 10%. 10 k
CE
(c) increases by more than 10%. 2.3 k
(d) decreases by more than 10%.
[EC-2006 : 2 Marks]

Q.46 The small signal gain of the amplifier Vc/Vs is

(a) –10 (b) –5.3 Q.49 The value of dc current IE is

(c) 5.3 (d) 10 (a) 1 mA (b) 2 mA

[EC-2006 : 2 Marks] (c) 5 mA (d) 10 mA

[EC-2008 : 2 Marks]
Q.47 For the BJT circuit shown, assume that the of
the transistor is very large and VBE = 0.7 V. The Q.50 The mid-band voltage gain of the amplifier is
mode of operation of the BJT is approximately
(a) –180 (b) –120
10 k
(c) –90 (d) –60
[EC-2008 : 2 Marks]

Q.51 A small signal source vi(t) = A cos20t + B sin106t

10 V
is applied to a transistor amplifier as shown
2V
1k below. The transistor has = 150 and hie = 3 k .
Which expression best approximates vo(t)?
 GATE Previous Years Solved Paper 91

12 V
Q.53 In the silicon BJT circuit shown below, assume
that the emitter area of transistor Q1 is half that
of transistor Q2.
3k
100 k
V o(t )
10 nF R = 9.3 k Io
Vi(t)
10 nF
Q1 Q2
20 k
900 k 10 µF
( 1 = 700) ( 2 = 715)

–10 V
(a) vo(t) = –1500 (A cos20t + B sin106t) The value of current Io is approximately
(b) vo(t) = –150 (A cos20t + B sin106t)
(a) 0.5 mA (b) 2 mA
(c) vo(t) = –1500 B sin106t
(c) 9.3 mA (d) 15 mA
(d) vo(t) = –150 B sin106t
[EC-2010 : 1 Mark]
[EC-2009 : 2 Marks]
Common Data for Questions (54 and 55):
Q.52 The amplifier circuit shown below uses a silicon Consider the common emitter amplifier shown below
transistor. The capacitors CC and CE can be with the following circuit parameters:
assumed to be short at signal frequency and the
= 100, gm = 0.3861 A/V, ro = , r = 259 ,
effect of output resistance ro can be ignored. If
Rs = 1 k , RB = 93 k , RC = 250 , RL = 1 k ,
CE is disconnected from the circuit, which one
C1 = and C2 = 4.7 µF
of the following statements is true?
V CC = 9 V +10 V

RC
RB
RC = 2.7 k C1
RB = 800 k C2
Vo
CC +
= 100 Rs
Vi Vo RL
CC
+ –
Vs Vs
RE = 0.3 k CE –
RI Ro

Q.54 The resistance seen by the source Vs is

(a) The input resistance Ri increases and the
(a) 250 (b) 1258
magnitude of voltage gain Av decreases.
(c) 93 k (d)
(b) The input resistance Ri decreases and the
[EC-2010 : 2 Marks]
magnitude of voltage gain Av decreases.
(c) Both input resistance Ri and the magnitude Q.55 The lower cut-off frequency due to C2 is
of voltage gain Av decreases. (a) 33.9 Hz (b) 27.1 Hz
(d) Both input resistance Ri and the magnitude (c) 13.6 Hz (d) 16.9 Hz
of voltage gain Av increases. [EC-2010 : 2 Marks]
[EC-2010 : 1 Mark]
 92 Electronics Engineering Analog Electronics

Q.56 In the circuit shown below, capacitors C1 and

ib B C
C 2 are very large and shorts at the input
frequency. v i is a small input. The gain
r ro
magnitude vo / vi at 10 M rad/sec is

5V
E

10 µH 2k 1 nF
(a) 250 (b) 27.5
(c) 25 (d) 22.5
C2 [EC-2012 : 1 Mark]
Q1
+ Q.59 The voltage gain A v of the circuit shown
2.7 V
vo 2k below is
–
2k C1 13.7 Volts
vi

12 k

C
(a) maximum (b) minimum vo
10 k
C
(c) unity (d) zero = 100
[EC-2011 : 1 Mark] 10 k
vi
Q.57 For the BJT Q1 in the circuit shown below, = ,
VBEon = 0.7 V, VCEsat = 0.7 V. The switch is
initially closed. At time t = 0, the switch is
opened. The time t at which Q1 leaves the active (a) Av 200 (b) Av 100
region is (c) Av 20 (d) Av 10
5V [EC-2012 : 2 Marks]

0.5 mA Q.60 In the circuit shown below, the silicon npn

transistor Q has a very high value of . The
required value of R2 in k to produce IC = 1 mA is
Q1 5 µF
–5 V VCC = 3 V
t=0

4.3 k IC
R1 = 60 k
–10 V
Q
(a) 10 ms (b) 25 ms
(c) 50 ms (d) 100 ms R2
RE = 500
[EC-2011 : 2 Marks]

Q.58 The current ib through the base of a silicon npn

(a) 20 (b) 30
transistor is 1 + 0.1 cos(10000 t) mA. At 300 K,
the r in the small signal model of the transistor (c) 40 (d) 50
is [EC-2013 : 2 Marks]
 GATE Previous Years Solved Paper 93

Q.61 A good current buffer has Q.64 In the circuit shown, the pnp transistor has
(a) low input impedance and low output VBE = 0.7 V and = 50. Assume that
impedance.
RB = 100 k . For Vo to be 5 V, the value of RC
(b) low input impedance and high output
(in k ) ________ .
impedance.
(c) high input impedance and low output
impedance. RC
(d) high input impedance and high output
impedance. Vo

[EC-2014 : 1 Mark]

Q.62 For the amplifier shown in the figure, the BJT

RB
parameters are VBE = 0.7 V, = 200 and thermal VEE = 10 V
voltage, VT = 25 mV. The voltage gain (vo/vi) of
the amplifier is _______ .

12 V
[EC-2014 : 1 Mark]

Q.65 In the circuit shown, the silicon BJT has = 50.

RC 5k
33 k R1 Assume VBE = 0.7 V and VCE(sat) = 0.2 V. Which
vo one of the following statements is correct?
1 µF
1 µF
vi 10 V

11 k R2 Rs 10 RC

50 k
1k RE C 1 mF 5V
RB

[EC-2014 : 2 Marks]
(a) For RC = 1 k , the BJT operates in the
Q.63 A cascade connection of two voltage amplifiers
saturation region.
A1 and A3 is shown in the figure. The open-loop
(b) For RC = 3 k , the BJT operates in the
gain A vo , input resistance R in and output
saturation region.
resistance Ro for A1 and A2 are as follows:
(c) For RC = 20 k , the BJT operates in the
A1 : Avo = 10, Rin = 10 k , Ro = 1 k
cut-off region.
A2 : Avo = 5, Rin = 5 k , Ro = 200 k
(d) For RC = 20 k , the BJT operates in the linear
The approximate overall voltage gain vout/vin
region.
is
[EC-2014 : 2 Marks]

+ + Q.66 If the emitter resistance in a common-emitter

voltage amplifier is not by passed, it will
Vin A1 A2 1k RL Vo
(a) reduce both the voltage gain and the input
– – impedance.
(b) reduce the voltage gain and the input
[EC-2014 : 1 Mark] impedance.
 94 Electronics Engineering Analog Electronics

(c) increase the voltage gain and reduce the Q.69 An increase in the base recombination of a BJT
input impedance. increase
(d) increase both the voltage gain and the input (a) the common-emitter dc current gain .
impedance. (b) the breakdown voltage BVCEO.
[EC-2014 : 1 Mark] (c) the unity gain cut-off frequency fT.
Q.67 Consider the common-collector amplifier in the (d) the transconductance gm.
figure (bias circuitry ensures that the transistor [EC-2014 : 1 Mark]
operates in forward active region, but has been Q.70 A BJT in a common base configuration is used
omitted for simplicity). Let IC be the collector to amplify a signal received by a 50 antenna.
current, VBE be the base-emitter voltage and VT Assume kT/q = 25 mV. The value of the collector
be the thermal voltage. Also, gm and ro are the bias current (in mA) required to match the input
small signal transconductance and output impedance of the amplifier to the impedance of
resistance of the transistor, respectively. Which the antenna is ______ .
one of the following conditions ensures a nearly
[EC-2014 : 2 Marks]
constant small signal voltage gain for a wide
range of values of RE ? Q.71 In the circuit shown, I1 = 80 mA and I2 = 4 mA.
Transistors T1 and T2 are identical. Assume that
the thermal voltage VT is 26 mV at 27°C. At 50°C,
the value of voltage V12 = V1 – V2 (in mV) is
Vin
Vs
Vo

RE I2 I1

– +
V2 V 12 V1

(a) gm RE << 1 (b) IC RE >> VT

(c) gm ro >> 1 (d) VBE >> VT T2 T1
[EC-2014 : 2 Marks]

Q.68 For the common collector amplifier shown in

the figure, the BJT has high , negligible VCE(sat),
[EC-2015 : 2 Marks]
and VBE = 0.7 V. The maximum undistorted
peak-to-peak output voltage vo (in Volts) is Q.72 In the ac equivalent circuit shown, the two BJTs
_________ . are biased in active region and have identical
V CC = +12 V
parameters with >> 1. The open circuit small
signal voltage gain is approximately _______ .

R1 5k

1 µF
vi
Vo
1 µF
vo
R2 10 k
Vi
RE 1k

[EC-2014 : 2 Marks] [EC-2015 : 2 Marks]

 GATE Previous Years Solved Paper 95

Q.73 In the circuit shown in the figure, the BJT has a

VCC = 2.5 V
current gain ( ) of 50. For an emitter base voltage
VEB = 600 mV, the emitter collector voltage VEC
(in Volts) is ______ .
1 = 100
3V
Q1 Q2
10 k
2 = 50

60 k V C2
500 1V
1k

[EC-2015 : 1 Mark]

Q.74 The Ebers-Moll model of a BJT is valid

[EC-2016 : 1 Mark]
(a) only in a active mode.
(b) only in active and saturation modes. Q.77 In the figure shown, the npn transistor acts as a
switch.
(c) only in active and cut-off modes.
(d) in active, saturation and cut-off modes. 5V
Vin(t)
[EC-2016 : 1 Mark] 4.8 k
2V
Q.75 Resistor R 1 in the circuit below has been
12 k
adjusted so that I 1 = 1 mA. The bipolar
+
transistors Q1 and Q2 are perfectly matched and
Vin(t )
have very high current gain, so their base T –
currents are negligible. The supply voltage VCC 0 t(sec)
is 6 V. The thermal voltage kT/q is 26 mV.
For the input Vin(t) as shown in the figure, the
VCC
transistor switches between the cut-off and
saturation regions of operation, when T is large.
R1 I2 Assume collector-to-emitter voltage at
saturation VCE(sat) = 0.2 V and base-to-emitter
voltage VBE = 0.7 V. The minimum value of the
Q1 Q2
common-base current gain ( ) of the transistor
for the switching should be ______ .
I1 R2
[EC-2017 : 2 Marks]

Q.78 For the dc analysis of the common-emitter

amplifier shown, neglect the base current and
The value of R2 (in ) for which I2 = 100 µA is assume that the emitter and collector currents
_______ . are equal. Given that, VT = 25 mV, VBE = 0.7 V,
[EC-2016 : 1 Mark] and the BJT output resistance ro is practically
infinite. Under these conditions, the mid-band
Q.76 Consider the circuit shown in the figure.
Assuming VBE1 = VEB2 = 0.7 volt , the value of voltage gain magnitude, Av = vo / vi V/V, is
the dc voltage VC2 (in Volt) is ______ . _________ .
 96 Electronics Engineering Analog Electronics

VCC = 12 V 5V

RC 2k
1k
73 k R1 C2
vo
C1 +
10 µ F
Q1
10 µF
RL 8k Vo vs
Vi 47 k R2
RE 2k CE
100 µF –
Q2

RB2
[EC-2017 : 2 Marks]

Q.79 Consider the circuit shown in the figure. –5 V

Assume base-to-emitter voltage VBE = 0.8 V and
[EC-2017 : 2 Marks]
common-base current gain ( ) of the transistor
is unity. Q.81 For the BJT in the amplifier shown below.
VBE = 0.7 V, kT/q = 26 mV. Assume the BJT
+18 V output resistance (ro) is very high and the base
current is negligible. The capacitors are also
assumed to be short circuited at signal
4k frequencies gain vo/vi of the amplifier is
44 k
VCC = 10 V

RC 10 k
16 k 2k C1
vo
1 µF
RL 10 k
vi
The value of the collector-to-emitter voltage VCE
(in Volt) is ______ .
20 k RE CE 100 µF
[EC-2017 : 1 Mark]
VEE = –10 V
Q.80 In the circuit shown, transistor Q1 and Q2 are
biased at a collector current of 2.6 mA. (a) –178.85 (b) –256.42
Assuming, that transistor current gains are (c) –128.21 (d) –89.42
sufficiently large to assume collector current [EC-2020 : 2 Marks]
equal to emitter current and thermal voltage of
26 mV, the magnitude of voltage gain Vo/Vs in Q.82 In the voltage regulator shown below, Vt is the
the mid-band frequency range is ______ (upto unregulated at 15 V. Assume, VBE = 0.7 V and
second decimal place). the base current is negligible for both the BJTs. If
the regulated output Vo is 9 V, the value of R2 is
_______ .
 GATE Previous Years Solved Paper 97

(a) Collector emitter terminals shorted

V1 = 15 V V0 = 9 V
(b) Emitter to ground connection open
(c) 10 k resistor open
R3 = 1 k
R1 = 1 k (d) Collector base terminals shorted
[EE-1994 : 1 Mark]

Q.3 One of the applications of current mirror is

(a) output current limiting
R2 (b) obtaining a very high current gain
Vz = 3.3 V
(c) current feedback
(d) temperature stabilized biasing
[EC-2020 : 2 Marks] [EE-1998 : 1 Mark]

Q.4 A NPN Si transistor is meant for low-current

ELECTRICAL EN GINEERIN G
audio amplification. Match its following
(GATE Previous Years Solved Papers) characteristics against their values:
Characteristics Values
SECTIO N - A
(a) VEBmax (P) 0.7 V
Q.1 Figure shown below, shows a common emitter (b) VCBmax (Q) 0.2 V
amplifier. The quiescent collector voltage of the (c) VCEmax (R) 6 V
circuit is approximately (S) 50 V

20 V
[EE-1998 : 2 Marks]
10 k
10 k Q.5 The enhancement type n-channel MOSFET is
represented by symbol
= 100
(a) (b)
5k
10 k

(b) (d)
20
(a) V (b) 10 V [EE-1999 : 1 Mark]
3
(c) 14 V (d) 20 V Q.6 In the circuit of figure, the value of the base
[EE-1991 : 1 Mark] current IB will be

Q.2 In the transistor circuit shown in figure. 5V

Collector to ground voltage is +20 V. Which of
5k
the following is the probable cause of error?
20 V
= 80
10 k +
IB 0.7 V
47 k 3k
– RE
+10 V
10 V
 98 Electronics Engineering Analog Electronics

(a) 0 µA (b) 18.2 µA

3.3 3.3
(c) 26.7 µA (d) 40 µA (a) mA (b) mA
3.3 (3.3 + 0.33)
[EE-2000 : 2 Marks]
3.3 3.3
Q.7 An n-channel JFET having a pinch-off voltage (c) mA (d) mA
33 (33 + 3.3)
(Vp) of –5 V shows a transconductance (gm) of
1 mA/V when the applied Gate to source voltage [EE-2003 : 1 Mark]
(VGS) is –3 V. Its maximum transconductance
Q.10 For the n-channel enhancement MOSFET shown
(in mA/V), is in figure, the threshold voltage Vth = 2 V. The
(a) 1.5 (b) 2.0 radian current ID of the MOSFET is 4 mA when
(c) 2.5 (d) 3.0 the drain resistance RD is 1 k . If the value of RD
[EE-2001 : 2 Marks] is increased to 4 k , drain current ID will become

Q.8 The variation of drain current with Gate-to- 10 V

source voltage (ID – VGS characteristic) of a
MOSFET is shown in figure. The MOSFET is ID RD

ID

VGS
0
(a) 2.8 mA (b) 2.0 mA
(a) an n-channel depletion mode device (c) 1.4 mA (d) 1.0 mA
(b) an n-channel enhancement mode device [EE-2003 : 2 Marks]
(c) an p-channel depletion mode device Q.11 Two perfectly matched silicon transistors are
(d) an p-channel enhancement mode device connected as shown in figure. The value of the
[EE-2003 : 1 Mark] current I is

Q.9 In the circuit of figure, assume that the transistor +3 V

has hFE = 99 and VBE = 0.7 V. The value of 1k I

collector current I C of the transistor is
approximately
= 1000 = 1000
3.3 k
+0.7 V

IC

33 k
12 V –5 V

4V (a) 0 mA (b) 2.3 mA

3.3 k
(c) 4.3 mA (d) 7.3 mA
[EE-2004 : 1 Mark]
 GATE Previous Years Solved Paper 99

Q.12 The transconductance g m of the transistor Q.15 The common emitter amplifier shown in the
shown in figure is 10 mS. The value of the input figure is biased using a 1 mA ideal current
resistance RIN is source. The approximate base current value is
V CC = 5 V
V CC
RC = 1 k
RC
10 k C Vo
Vo
C = 100
Vs = 50
+
Vin
1 mA
10 k –
1k C

(a) 0 µA (b) 10 µA
(a) 10.0 k (b) 8.3 k (c) 100 µA (d) 1000 µA
(c) 5.0 k (d) 2.5 k [EE-2005 : 2 Marks]
[EE-2004 : 2 Marks] Statement for Common Data Questions (16 and 17):
Q.13 The value of R for which the PMOS transistor in Assume that the threshold voltage of the n-channel
figure will be biased in linear region is MOSFET shown in figure is +0.75 V. The output
+4 V characteristics of the MOSFET are also shown.

VDD = 25 V
VT = –1 V

R = 10 k
R 1 mA

Vout

(a) 220 (b) 470 +

(c) 680 (d) 1200 Vin = 2 mV
[EE-2004 : 2 Marks] –

Q.14 Assume that the n-channel MOSFET shown in 2V

the figure is ideal, and that its threshold voltage
is +1.0 V the voltage Vab between nodes a and b is
1k 1k IDS = 4 (mA)
a
VGS = 4 V
4

D VGS = 3 V
G 3
10 V 2k Vab
S
VGS = 2 V
2V 2
VGS = 1 V
b 1

(a) 5 V (b) 2 V
(c) 1 V (d) 0 V 0 VDS (V)
[EE-2005 : 1 Mark]
 100 Electronics Engineering Analog Electronics

Q.16 The transconductance of the MOSFET is Q.20 Two perfectly matched silicon transistor are
(a) 0.75 mS (b) 1 mS connected as shown in the figure. Assuming
(c) 2 mS (d) 10 mS the of the transistors to be very high and the
forward voltage drop in diodes to be 0.7 V, the
[EE-2005 : 2 Marks]
value of current I is
Q.17 The voltage gain of the amplifier is +5 V
(a) +5 (b) –7.5 1k
I
(c) +10 (d) –10
[EE-2005 : 2 Marks]
Q1 Q2
Q.18 Consider the circuit shown in figure. If the of
the transistor is 30 and ICBO is 20 nA and the
–5 V
input voltage is +5 V, the transistor would be
(a) 0 mA (b) 3.6 mA
operating in
(c) 4.3 mA (d) 5.7 mA
+12 V
[EE-2008 : 2 Marks]
2.2 k
Q.21 The transistor circuit shown uses a silicon
15 k transistor with VBE = 0.7 V, IC IE and a dc
Vi Q
current gain of 100. The value of Vo is
100 k +10 V

–12 V
50 k
(a) saturation region 10 k
(b) active region
(c) breakdown region
(d) cut-off region
Vo
[EE-2006 : 2 Marks]
100
Q.19 The common emitter forward current gain of the
transistor shown is F = 100.
+10 V
(a) 4.65 V (b) 5 V
1k (c) 6.3 V (d) 7.23 V
[EE-2010 : 2 Marks]

Q.22 The voltage gain Av of the circuit shown below

is
270 k
13.7 V
1k
10 V
12 k

The transistor is operating in C

10 k Vo
(a) saturation region
C
(b) cut-off region = 100
10 k
(c) reverse active region Vi
(d) forward active region
[EE-2007 : 1 Mark]
 GATE Previous Years Solved Paper 101

(a) Av 200 (b) Av 100 Q.26 When a bipolar junction transistor is operating
in the saturation mode, which one of the
(c) Av 20 (d) Av 10
following statements is true about the state of
[EE-2012 : 2 Marks]
its collector-base (CB) and the base-emitter (BE)
Q.23 The transistor in the given circuit should always junctions?
be in active region. (a) The CB junctions is forward biased and the
(Take, VCE(sat) = 0.2 V, VBE = 0.7 V) BE junction is reverse biased.
The maximum value of Rc (in ) which can be (b) The CB junctions is reverse biased and the
used, is _______ . BE junction is forward biased.
(c) Both the CB and BE junctions are forward
RC biased.
(d) Both the CB and BE junctions are reverse
Rs = 2 k +
= 100 5V biased.
–
+ [EE-2015 : 1 Mark]
5V
–
Q.27 A transistor circuit is given below. The Zener
diode breakdown voltage is 5.3 V as shown
[EE-2014 : 2 Marks]
below. Take base to emitter voltage drop to be
Q.24 In the given circuit, the silicon transistor has 0.6 V. The value of the current gain is _____ .
= 75 and a collector voltage VC = 9 V. Then the
ratio of RB and RC is 10 V

15 V
220
RC 4.7 k
RB
Vc
0.5 mA

5.3 V
470

[EE-2015 : 1 Mark]

Q.25 In the following circuit, the transistor is in active [EE-2016 : 1 Mark]

mode and VC = 2 V. To get VC = 4 V, we replace
Q.28 The circuit shown in the figure uses matched
RC with RC . Then the ratio RC / RC is _____ .
transistors with a thermal voltage VT = 25 mV.
+10 V The base currents of the transistors are
negligible. The value of the resistance R in k
RC that is required to provide 1 mA bias current for
RB
Vc the differential amplifier block shown is ____ .
(Give the answer up to one decimal place).

[EE-2015 : 1 Mark]
 102 Electronics Engineering Analog Electronics

10 k
+12 V a

+
Differential 10 k
15 V 1k
amplifier
– + RTh
10.7 V
1 µA
1 mA –
b

[EE-2018 : 2 Marks]

Q.31 The enhancement type MOSFET in the circuit

R below operates according to the square law.
µnCox = 100 µA/V2, the threshold voltage (VT) is
500 mV. Ignore channel length modulation. The
–12 V output voltage Vout is
VDD = 2 V
[EE-2017 : 2 Marks]
ID = 5 µA
Q.29 For the circuit shown in the figure below, it is

V Vo
given that, VCE = CC . The transistor has = 29
2 W 10 µm
=
and VBE = 0.7 V when the B-E junction is forward L 1 µm

biased.

VCC = 10 V
(a) 2 V (b) 500 mV
(c) 100 mV (d) 600 mV
4R
RB [EE-2019 : 2 Marks]

Q.32 Given, Vgs is the gate-source voltage, Vds is the

C
B drain source voltage and VTh is the threshold
= 29
voltage of an enhancement type NMOS
E transistor, the conditions for transistor to be
R biased in saturation are
(a) Vgs > Vth; Vds Vgs – Vth
(b) Vgs < Vth; Vds Vgs – Vth
(c) Vgs > Vth; Vds Vgs – Vth
For this circuit, the value of RB/R is
(d) Vgs < Vth; Vds Vgs – Vth
(a) 43 (b) 92
[EE-2019 : 1 Mark]
(c) 121 (d) 129
[EE-2017 : 2 Marks] Q.33 A common source amplifier with a drain
resistance, RD = 4.7 k , is powered using a 10 V
Q.30 In the circuit shown in the figure, the bipolar power supply. Assuming that the trans-
junction transistor (BJT) has a current gain conductance, gm is 520 µA/V, the voltage gain
= 100. The base-emitter voltage drop is a of the amplifier is closest to
constant, VBE = 0.7 V. The value of the Thevenin (a) 1.22 (b) –1.22
equivalent resistance RTh (in ) as shown in (c) 2.44 (d) –2.44
the figure is ______ (upto 2 decimal places). [EE-2020 : 1 Mark]
 GATE Previous Years Solved Paper 103

SECTIO N -B VCC

Q.1 In the transistor amplifier shown in figure, the RC

R1
ratio of small signal voltage gain, when the Vo
CC
emitter resistor is by passed by the capacitor
‘Ce’ to when it is not by passed. + C1
(Assuming of simplified approximate R2
Vi
h-parameter model for transistor) is CE
RE
–
VCC

Rc
R1 (a) increases (b) decreases
Vo
Cc (c) is unaffected (d) drops to zero
Vi [EE-2001 : 1 Mark]
C1
Q.3 The magnitude of the mid-band voltage gain of
R2
the circuit shown in figure is (assuming hfe of
Re Ce the transistor to be 100)
+VCC

1k
(a) 1 (b) h fe C
Vo
(1 + h fe ) Re (1 + h fe ) Re 10 k
(c) (d) 1 + hfe = 100
hie hie C

[EE-1996 : 1 Mark]
Vi
1k C
Q.2 In the single stage transistor amplifier circuit
shown in figure, the capacitor CE is removed
then the ac small signal mid-band voltage gain
of the amplifier (a) 1 (b) 10
(c) 20 (d) 100
[EE-2014 : 1 Mark]
104 Electronics Engineering Analog Electronics

Electronics & Electrical Engineering

GATE Previous Years Solved Paper

A n swe rs & Expl a n a t i o n s

Answers
EC BJT Analysis

1. (b) 2. (c) 3. (d) 4. (d) 5. (d) 6. (a) 7. (b) 8. (a, b)

9. (5) 10. (1) 11. (c) 12. (c) 13. (d) 14. (Large) 15. (1) 16. (3.75)

17. (c) 18. (a-2, b-5, c-4) 19. (b) 20. (a) 21. (d) 22. (c) 23. (b)

24. (d) 25. (b) 26. (c) 27. (a) 28. (a) 29. (c) 30. (d) 31. (a)

32. (c) 33. (b) 34. (d) 35. (b) 36. (a) 37. (a) 38. (a) 39. (c)

40. (b) 41. (c) 42. (d) 43. (b) 44. (c) 45. (b) 46. (a) 47. (b)

48. (b) 49. (a) 50. (d) 51. (d) 52. (a) 53. (b) 54. (b) 55. (b)

56. (a) 57. (c) 58. (c) 59. (d) 60. (c) 61. (b) 62. (–233.6) 63. (34.72)

64. (1.07) 65. (b) 66. (b) 67. (b) 68. (9.4) 69. (b) 70. (0.50) 71. (83.15)

72. (–1) 73. (2.04) 74. (d) 75. (598.68) 76. (0.5) 77. (0.902) 78. (128) 79. (6)

80. (50) 81. (d) 82. (800)

Solutions
EC BJT Analysis

1. (b) 3. (d)
Cascade amplifier is the common-emitter C
followed by common base configuration. IC

2. (c)
B
Ic IB
gm =
VT
So, if Ic then gm , gm Ic
E
So, if the quiescent collector current Ic increases
then the transconductance gm also increases. So, overall of the composite transistor,
IC
= = 1+ 2+ 1 2
IB
= 10200
 GATE Previous Years Solved Paper 105

4. (d) 6. (a)
In the BJT self bias circuit or potential divider
circuit provides the maximum bias stability.

7. (b)
RE
>> 1 ,
Vin = V gs RB

VCC
IC
gm = RC
Vgs
RTh
IC = IE = IE
1+ +
Vbe –
VTh
IE Re
1+ IE
gm = =
Vgs (1 + ) Vgs
ID = IE
I Simplified self bias circuit using Thevenin
gm = × D = gm theorem.
(1 + ) Vgs 1 +
Thevenin open-circuit voltage,
99
= × 2 mA/V VCC R1
1 + 99 VTh =
R1 + R2
gm = 1.98 mA/V
Thevenin internal resistance,
5. (d) R1 R2
RTh = R1 R2 = = RB
R1 + R2
Apply KVL to input mesh,
10 k 58 k 1/hoe 5k VTh = IBR + Vbe + IERE
Put, IE = IB + IC
VTh = IBRB + Vbe + (IB + IC) RE
Differentiate w.r.t. IC, keeping and Vbe constant,
Z01 = 20 k Zo
IB
Output admittance, 0 = ( RB + RE ) + RE + 0
IC
h fe hre
Y 0 = hoe IB RE
hie + Rs =
IC RB + RE
3 100 × 0
= 0.05 × 10 1+
2 × 10 3 + 10 × 10 3 S= Ib
Y 0 = 0.05 × 10–3 1
Ic
1 1
Z 01 = = = 20 k 1+
Y0 0.05 × 10 3 S=
Output impedance, RE
1+
RB + RE
Z 0 = Z01 5k
>> 1
20 × 5 RE
= 20 k 5k = =4k >> 1
20 + 5 RB + RE
106 Electronics Engineering Analog Electronics

Given that is very large.

S= So, Ib = 0
RE
RB + RE 1.65
So, V1.65 = 10 ×
1.65 × 1.85 + 6.5
R
S = 1+ B = 1.65 V
RE
Apply KVL at input mesh,
For better stability,
V1.65 = Vbe + IeRe
S 1
= 0.65 × Ie + 1 k
RB RE = 1.65
So, << 1; >> 1
RE RB Ie = 1 mA
Q is very large.
8. (a, b)
So, Ic = Ie
In common base (CB) amplifiers input
I = Ic
impedance (Zf ) is low and current gain ( ) is
= 1 mA
also low,
Ic 11. (c)
=
Ie The overall bandwidth of an n-stage turned
In common collector (CC) amplifiers output amplifier is
impedance (Zo ) is low and current gain ( ) is BW = B 2 1/ n 1
high,
Ie 12. (c)
= = 1+
Ib IB
+
9. Sol. Vi
– 100 k 200 k
Given that, b is very large. hie hfeIB

So, IC = IE
So, the current through 1 k resistance, +
I = 5 mA Vo
470 –
VDC = 10 – IR
= 10 – 5 × 103 × 1 × 103
VDC = 5 V
Vo I B (1 + h fe ) RE
AV = = 1
10. Sol. Vi I B [ hie + (1 + h fe )] RE

I 13. (d)
6.5 k 2k
DB
f =
WB2

10 V Thus, if WB will decrease f will increase.

1.85 k
14. Sol.
+
+ In order to reduce the harmonic distortion in an
Vbe
1.65 k V1.65 – amplifier is dynamic range has to be large.
1k Ie
–
 GATE Previous Years Solved Paper 107

15. Sol. 19. (b)

For common-emitter configuration: Increase the voltage gain and decrease the input
impedance.
VT
Input resistance = Ri = The by-pass capacitor C across RE will act as
IB
short-circuit for ac signal. So, the by-pass
25 × 10 3 capacitor C will increase the voltage gain and
= =1k
25 × 10 6 decrease the input impedance.
16. Sol. 20. (a)
+12 V A common-emitter stage followed by common
1k base stage.

22. (c)
Loop-1
1k Upper 3-dB frequency,
10 k
0.35
B.W. = f H =
tr

23. (b)
1k
Loop-2
A22 + A32 + ....
IC cannot be 5.32 mA because IC = 5.32 mA will A1
make VCE negative which implies transistor is The total harmonic distortion is,
in saturation.
A22 + A32 + ....
Through KVL, T.H.D. =
A1
12IB + 2IC = 11.2 (Loop-1)
10IB – IC = 0.6 (Loop-2) 25. (b)
Upon solving, IC 3.75 mA
1 1 1 1
= + +
17. (c) B 1 2 3

ic ic2 Cascading of amplifier results in decrease of

gm = = higher cut-off frequency and increase in lower
Vbe Vbe1 + Vbe2
cut-off frequency.
ic2
= gm2 So, fH and fL
Vbe2 B.W. = fH – fL
So, B.W.
18. Sol.
a-2, b-5, c-4 26. (c)
(a) Cascade amplifier: The pass transistor in a series voltage regulator
(2) It provides a wide band amplifier in common collector configuration, the voltage
(b) Differential amplifier: gain is almost equal to 1.

(5) Provides high common mode voltage 27. (a)

rejection
io
(c) Darlington pair common collector amplifier: gm = , io I E2 = IC1
vi
(4) Has very high input impedance and very
high current gain IC1 = I B1 , IE2 = IC1
108 Electronics Engineering Analog Electronics

io I B1 , Vi = I B1 r 32. (c)

I B1 IC h fe = gm r
io
= = gm1 = 1 (as IC = I B )
vi I B1 r vi 1 1 33. (b)
fL = 20 Hz
28. (a)
fH = 1 kHz for single stage
Common mode gain, For cascaded stage,
VC = ACVi (Vi1 = Vi2 = Vi ) fL 20
fL = =
If Re is infinite then because of symmetry of 1/ n 1 /3
2 1 2 1
figure, VC becomes zero, = 39.2 Hz
ie1 = ie2 = 0 1/ n
fL = f H 2 1 = 0.5 k
ib2 << ic2
37. (a)
So, ic2 ie2
VCE = VCC – ICR2
3 = 6 – 1.5 mA × R2
30. (d)
1.5 mA × R2 = 3
15 V R2 = 2k
RC IC 1.5 mA
IB = = = 0.01 mA
150
RTh
When, = 200
10/3 IC = IB
5V VTh (as R1 is same IB remains same)
430 = 0.01 mA × 200
IC = 2 mA
VCE = VCC – ICR2
R2VCC 5
VTh = = × 15 = 5 V = 6 – 2 mA × 2 k
R1 + R2 15
VCE = 2 V
Since, is large,
38. (a)
IB 0, RTh = 5 10
VCE = VCC – ICRC
V 0.7 0.2 = 3 – IC × 1 k
IC = Th
RE IC = 2.8 mA
VTh 0.7 5 0.7 IC 2.8 mA
= = = , IB = C
=
RE 0.430 k IB 50
4.3 = 0.056 mA = 56 µA
= = 10 mA
0.430 k
39. (c)
31. (a) 5V

gm 2.2 k
Ai =
gb e + j (C e + Cc ) 4/5 k
where, Ce and Cc are the transistor capacitances
so, at high frequencies the current gain of 1V
300
bipolar transistor drops due to the transistor
capacitors.
 GATE Previous Years Solved Paper 109

R2 1 44. (c)
VTh = × VCC = × 5 = 1 V
R1 + R2 5 Drawing DC equivalent circuit, the capacitor is
4 treated as open-circuit.
RTh = R1 R2 = k
5 12 V
1 0.7 RC
IC = 1 mA 1k
0.3 k
Rf IE
(Q is large IB 0)
VCE = VCC – ICRC – IERE 53 k +
(IE = IC as IB 0)
IC VCE
VCE = 5 – 2.2 × 1 – 0.3 × 1 IB
VCE = 2.5 V –

41. (c)
When two terminals of a transistor are shorted Applying KVL in base-emitter loop.
it acts as diode, Applying KVL in base-emitter loop,
12 – IERC – IB Rf – 0.7 = 0
VD
VT IE
I = Io e 1 12 – 0.7 = IE I k + 53 k
( + 1)
11.3 11.3
0.7 IE = =
3 53 1.87 k
= 10 13
e 1 × 26 × 10 1 1+ k
61
= 6.046 mA = 6 mA
= 49 mA VCE = VCC – IERC
= 12 – 6 mA × 1 k
42. (d) = 6V
Only common-mode gain depends on RE and
differential mode gain is independent of RE. 45. (b)
When increases by 10%, new = 66
43. (b)
11.3
IE = IC + IB IE = = 6.31 mA
53
= IB + IB = ( + 1) IB 1+ k
67
KVL in input loop gives,
VCE = VCC – IE × RC
VCC – VBE = IBRB + IERE
= 12 – 6.31 mA × 1 k
= IBRB + ( + 1) IBRE
= 5.7
VCC VBE % change in,
IB =
RB + ( + 1) RE
6 5.7
VCE = × 100 = 5%
20 0.7 6
=
430 k + 51 × 1 k
46. (a)
IB = 40 µA
Given circuit is a voltage shunt feedback
IC = IB = 50 × 40 µA
amplifier.
= 2000 µA = 2 mA
So, the approximate voltage gain is,
VC = VCC – ICRC
= 20 – 2 mA × 2 k Rf 53 k
Avf = = = 10
VC = 16 V Rs 5.3 k
110 Electronics Engineering Analog Electronics

47. (b) 49. (a)

Given, is large. So, IB = 0 and IE = IC The given circuit can be redesigned as shown
Assuming BJT is in active. below.
Applying KVL in base emitter loop, VCC = 9 V
2 – 0.7 = 1 k × IE
3k
IE = 1.3 mA
10 0.2 RTh
Now, ICsat =
1 k + 10 k

9.8 VTh
= 0.9 mA IE 2.3
11 k

As, ICactive > ICsat

So, BJT is in saturation. 10
VTh = ×9 = 3 V
10 + 20
48. (b)
10 × 20
RTh = = 6.67 k
IPC1 10 + 20
IPE Since is large, IB can be ignored,
3 (0.7)
P n P IE = = 1 mA
2.3 k
InE
50. (d)
Mid-band voltage gain,
RC RL
AVm =
re
+ – + –
RL (3 3)
VEB VCB AVm = = = 60
re 0.026
I PC1
Transport factor = = 51. (d)
I PE
Current in emitter is both due to holes and The best approx answer for output voltage Vo
electrons. is,
Neglect current due to electrons, Vo = Av vi
h fe Rc
I PC1
I × vi
= = PE = × hie
I PE IE
–150 (A cos20t + B sin106t)
I PE Since the coupling capacitor is large,
= = emitter efficiency
IE Vo –150 B sin106t
50 52. (a)
= = = 0.9853
51 × 0.995
By disconnecting emitter bypass capacitor CE:
50 (i) Input impedance increases by a factor of
= =
1+ 51 (1 + RE).
(ii) Magnitude of voltage gain Av decreases by
the same factor.
 GATE Previous Years Solved Paper 111

53. (b) 55. (b)

The given circuit is a current mirror circuit in Lower cut-off frequency due to C2,
which the output current is a mirror image of 1
fL =
the input current if both the transistors are 2 ( RC + RL ) C 2
identical. 1
=
2 (250 + 1000) × 4.7 × 10 6
Ii R = 9.3 k = 27.1 Hz
Io

56. (a)
Q1 Q2
Whenever we use a bypass capacitor in parallel
( 1 = 700) ( 2 = 715) RE in a BJT biased with “common emitter with
RE” then it always increases voltage gain. As
compare to “CE with RE without capacitor”.
–10 V Hence only answer (a) is possible,

To calculate Ii, 1 1
and =
=
9.3Ii + 0.7 = 0 – (10) = 10 LC 10 × 10 6 × 10 9
Ii = 1 mA = 10 M rad/sec
Since the emitter area of transistor Q1 is half and gain is maximum at resonance frequency.
that of transistor Q2.
57. (c)
I
So, Ii = o In active region,
2
–5 – 0.7 – 4.3IE = –10
Therefore, Io = 2 mA
10 5.7 4.3
IE = = = 1 mA
54. (b) 4.3 4.3
Equivalent model of the given circuit is shown IC = IE = I + 0.5 mA = 1 mA
below: I = 0.5 mA
C2 5V
B Ib C
0.5 mA

Rs I
VC
RB hie +
Ib RC RL
+ Q1 0.7 Vsat
+ 5 µF
Vs –5 V t=0
–
– 0.7 V –
active
E

–10 V
100 In saturation region:
h ie = = = 259
gm 0.3861 VC – 0.7 – 4.3 × 1 = –10
The resistance seen by the source Vs, VC = –5 V
Rin = Rs + ( RB hie ) q = CVC
= –5 × 10–6 × 5 V
93000 × 259 = –25 × 10–6
= 1000 +
(93000 + 259) and q = it, I (0 – t) = –25 × 10–6
Rin = 1000 + 258 = 1258 25 × 10 6
t= = 50 msec
0.5 × 10 3
112 Electronics Engineering Analog Electronics

58. (c) 100

Rm = = 0.245
We know that, 1 + 407.1
r = ( + 1) re
Ri = r Rm
V
r = ( + 1) T
Ie = 2.63 0.245 = 0.224
VT Vo Vo Ri
r = ( + 1) = ×
( + 1) I b Vi Vi Rs + Ri
VT 0.224
r = = 407.14 ×
Ib 10 + 0.224
Where Ib is dc current through base so Ib = 1 mA. = –8.92
VT = 25 mV at room temperature.
Av 10
25 × 10 3
So, r = = 25
1 × 10 3 60. (c)
Given that, is very large.
59. (d)
So, IC = IE = 1 mA
13.7 Volts VE = IERE
12 k = 1 × 10–3 × 500 = 0.5 V
VBE = 0.7 V
C
100 k
vo VR2 = VBE + VE
C
= 100 = 0.7 + 0.5 = 1.2 V
10 k
It is a self bias circuit.
vi V1 R2
So, VR2 = VCC ×
R1 + R2

KVL : R2
1.2 = 3 ×
–13.7 + 12 × 101IB × 100IB + VBE = 0 60 + R2
1312IB = 1 72 + 1.2 R2 = 3 R 2
IB 0.01 mA 1.8 R2 = 72
IC = IB = 1 mA R 2 = 40 k
IC
gm = = 38 m 62. Sol.
VT
100 12 V
r = = = 2.63 k 12 V
gm 38 m
Apply Miller’s theorem to 100 k resistor, 5k 5k
33 k
100
Rm = 8.25 k
1 Av
100
Rn = 100 k 11 k 3V
1 1.01 1.01
1
Av
V0
= gm RL = 38 × (12 100) By applying KVL in input loop, we get,
V1
3 = 8.25 k IB + 0.7 + 1.10 k IE
= –407.14
 GATE Previous Years Solved Paper 113

8.25 k 64. Sol.

2.3 = IE + 1.01 k
201 Applying KVL in input loop, we get,
= IE × 1.051 k 10 = 0.7 + IBRB
IE = 2.2 mA 9.3
IB = = 0.093 mA
AC equivalent model of amplifier is given as, 100 k
ib Hence, IC = IB = 4.65 mA
+ + Vo 0 5
where, IC = =
Vi re = 2.27 k ib Vo RC RC
– – 5
R1 R2 5k
RC = = 1.07 k
4.65
0.01 k
65. (b)

10 V
where, re is given by
VT 25 mV
re = = = 11.36 RL
I E 2.2 mA
V BE = 0.7 V
Vo = –5 ib ...(i) 50 k
5V V CEsat = 0.2 V
Vi = 2.27 k ib + 0.01 k (ib + ib) RB = 50
S
...(ii)
From equations (i) and (ii), we get
Vo 5 k × 200 Assume the transistor is in active region,
= = 233.6
Vi 4.28 k

63. Sol.
50 k
R 01 R 02 5V
+
+ IBactive
+ 0.7 V –
+
Vin R in1 + AV V2 Rin2 + AV V RL Vo
– 01 – 02 in

–
–
– 5 0.7
IBactive = = 86 µA
50 k
Vo RL
= ...(i) ICactive = IBactive
AVo2 × V2 RL + Ro2
= 50 × 86 µA = 4.3 mA
AVo1 × Vin Rin 2 Assume, Re = 1 k
where, V2 = ...(ii)
Rin 2 + Ro1 10 V

From equations (i) and (ii), we get,

1k 4.3 mA
Vo RL Rin 2
= AVo2 × AVo1 × ×
Vi RL + Ro2 Rin 2 + Ro1 OFF
VC = 5.7 V
Vo 1k 5k 50 k
= 5 × 10 × × 5V
Vi 1 k + 0.2 k 5k +1k
VB = 0.7 V
Vo
= 34.72
Vi
It is in saturation.
114 Electronics Engineering Analog Electronics

Assume, Rc = 3 k 68. Sol.

10 V V CC = +12 V

3k 4.3 mA

ON R1 5k
VC = –2.9 V
50 k 1 µF
5V vi
1 µF
VB = 0.7 V vo
R2 10 k
RE 1k
It is in active.

66. (b)
DC analysis,
For unbypassed RE,
VCC × R2 12 × 10 k
R i = re + (1 + ) RE (VB)q = = =8V
R1 + R2 15 k
AI RL
and Av = (VE)Q = VB – 0.7 = 8 – 0.7 = 7.3 V
Ri
(VCE)Q = (VC)Q – (VE)Q
67. (b) = 12 – 7.3 = 4.7 V
AC equivalent circuit for given common
collector amplifier is, 4.7 V

(VCE )Q
+ VCE = Vo
re ib 4.7 V

Vin
Vo Vo(p – p) = 2 × 4.7 = 9.4 V

RE 70. Sol.
– The input impedance of CB-amplifier is,
Z i = re
Vin = reib + (1 + ) ibRE ...(i) So, according to given condition,
Vo = (1 + ) RE ib re = 50
Vo (1 + ) RE VT
Then, = = 50
Vin re + (1 + ) RE
IC
25 mV
Vo RE RE IC = = 0.50 mA
= = 50
Vin re + RE re + RE
The condition for small signal voltage gain to 71. Sol.
be nearly constant is, VBE2
R E >> re
I2 = I s e VT
V
R E >> T VBE2 = V2
IC
VBE1
ICRE >> VT
I1 = I s e VT
 GATE Previous Years Solved Paper 115

VBE1 = V1 76. Sol.

V1 V2
2.5 V
I1 VT
= e
I2
Since, VT at 27° is 26 mV then VT at 50° is +
Loop-1
VCE 1
27.99 mV. +
0.7 V –
Thus, V12 = V1 – V2 – + 0.7 V
= 83.15 mV – IB2

10 k
72. Sol.
V C2
1V
Both the transistors are biased at the same 1k IC2
collector current thus their transconductance
will be same, the small signal equivalent circuit
is,
Vout Q1 : VCB = 0
+
We know,

V gm1Vi 1/gm2
VCB1 + VBE1 = VCE1
VCE1 = VBE1 = 0.7 V
–
KVL to loop 1,
–2.5 + VCE + 0.7 + IB × 10 k +1V=0
1 2
gm1 = gm2 2.5 1.4 1
IB = = 0.01 mA
Thus, Vo = –Vi
2 10 k
So, gain equal to –1. IC = 2 I B2 = 0.5 mA
2

73. Sol. VC 2 = IC2 × 1 k

VEB = 0.7 V
= 0.5 × 10–3 × 1 × 103
IB = 0.0383 mA
= 0.5 V
IC = 1.913 mA
VEC = 3 – ICRC 77. Sol.
= 3 – (1.916 × 0.5) +5 V
= 2.04 V
4.8 k
74. (d)
Ebers-Moll model is valid for all the region of 12 k
2V
operation.

75. Sol.

VT I 2 0.7
R2 = ln 1 IB = = 0.10833 mA
I2 I2 12
3 3 5 0.2
26 × 10 1 × 10 IC(sat) = = 1 mA
= 6
ln 6 4.8
100 × 10 100 × 10
IC (sat)
= 598.67 IB IB(min) =
116 Electronics Engineering Analog Electronics

1 mA +18 V
IB
RC 4k
1
0.10833 IC
and min = 9.23 RTh +
VTh VCE
min IB +
= = 0.902 VBE – –
min 1 + min
RE 2k
78. Sol.
IE
12 V

RC 2k 16
VTh = × 18 V = 4.8 V
16 + 44
IC
IERE = VTh – VBE – IBRTh
RTh
IB = 0 A (Q = 1))
VTh
IB = 0 + So, IERE = 4.8 – 0.8 = 4 V
VBE –
4
RE 2k IE = mA = 2 mA
2
IC = IE = 2 mA (Q = 1)
VCE = VCC – ICRC – IERE
By taking the Thevenin’s equivalent between = 18 – (2 × 4) – (2 × 2)
base and ground nodes, the given circuit can be = 6V
reduced as follows for DC analysis:
80. Sol.
12 × 47
VTh = = 4.7 V In AC equivalent circuit, Q2 becomes diode-
73 + 47
connected transistor because collector and base
Neglecting base current (IB = 0),
get shorted.
V VBE 4.7 0.7
IE = IC = Th = E
RE 2
IC = 2 mA
Q2 1/gm
IC 2
gm = = = 80 m
VT 25
Voltage gain,
Computer AC equivalent circuit is as shown
Av = gm ( RC RL )
below.
= 80(2 8) = 128

Av = 128 1k
Q1
79. Sol.
By taking the Thevenin’s equivalent between Vs
1/gm
base and ground nodes, the given circuit can be
reduced as follows:
 GATE Previous Years Solved Paper 117

It is a CE amplifier with unbypassed RE,

I EQ 0.465
gm RL gm = = A/V
Av = VT 26
1 + gm RE
IC 2.6 Vout
where, gm = = = 100 m = gm ( Re RL )
VT 26 Vin

RL = 11 k
0.465
= × 5000 = 89.423
1 26
RE =
gm
82. Sol.
100 × 1
Av = = 50
1+1 R2
9× =4
Av = 50 R2 + 1 k
9R 2 = 4R2 + 4 k
81. (d) 5R 2 = 4 k
10 0.7 4000
IEQ = = 0.465 mA R2 = = 800
20 5

Answers
EE BJT Analysis (Section-A)

1. (c) 2. (b) 3. (d) 5. (a) 6. (b) 7. (c) 8. (c) 9. (b)

10. (c) 11. (c) 12. (d) 13. (d) 14. (d) 15. (b) 16. (b) 17. (d)

18. (b) 19. (d) 20. (b) 21. (a) 22. (d) 23. (22.32) 24. (105.13) 25. (0.75)

26. (c) 27. (19) 28. (172.7) 29. (d) 30. (90.09) 31. (d) 32. (c) 33. (d)

Solutions
EE BJT Analysis (Section-A)

1. (c) 5
VTh = × 20 V = 6.67 V
20 V 15

10 × 5
10 k RTh = = 3.33
10 + 5
Vc
VTh – Ib RTh – 0.7 – ( + 1) Ib × 10 k = 0
RTh
5.97 = Ib (3.33 + 101 × 10) k
Ib = 5.891 µA
VTh Ic = Ib = 0.589 mA
10 k
Vc = 20 – 10 × Ic
= 14.11 V 14 V
118 Electronics Engineering Analog Electronics

2. (b) 4 – 33 × Ib – 0.7 – 3.3 × 100 Ib = 0 (Ic = Ib)

20 – 10 k × IC = 20 4 0.7
Ib =
IC = 0 which gives, (33 + 330)
IE = IC = IB = 0
3.3 × 100 3.3
That is only possible when emitter connection Ic = = mA
33 + 330 (0.33 + 3.3)
is open. In other cases there will be base current.
10. (c)
4. Sol.
ID = K(VGS – Vth)2
(a) (P)
4 = K(6 – 2)2
(b) (R)
1
(c) (Q) K= mA/V 2
4
6. (b) VGS = 10 – 4 × 1 = 6 V
0 – 0.7 – Ib ( + 1) × 6.3 = –10 V when RD is increased to 4 k ,
10 0.7 VGS = 10 – 4ID
Ib = = 18.452 µA
81 × 6.3 1
ID = (10 4 I D 2)2
4
7. (c)
2
4ID = 16 ID + 64 64 ID
2 IDSS VGS
gm = 1 2
Vp Vp 16 ID + 68 I D + 64 =0
ID = 2.84 mA, 1.4 mA
2 IDSS 3
1 mA/V = 1 For MOSFET to be on, VGS must be greater than
5 5
Vth and this is possible only if,
2 3 ID = 1.4 mA
= × 1 IDSS
5 5 If, ID = 2.84 mA
2 then VGS become –ve and less than V th so
5
IDSS = mA
2 transistor will be off for this value which is not
2 I DSS 2 × 25 possible since VDG = 0 – Vth.
(gm)max = =
VP 4 × ( 5) 11. (c)
= 2.5 mA/V Both transistor are perfectly matched, hence
8. (c) VBE2 = VBE1

This is the characteristics of a p-channel Ic 1

= exp [(VBE1 – VBE2)/VT] = 1
depletion mode device. Ic 2
Also, ‘ ’ is same,
9. (b)
3V
Using KVL in base-emitter loop, IR
1k I = IC2
3.3 k

2IB

33 k = 1000 = 1000
12 V

4V
3.3 k
–5 V
 GATE Previous Years Solved Paper 119

+5 0.7 16. (b)

IR = = 4.3 mA
1k IDS (4 3) mA
gm = = = 1 mS
writing KCL at node B, VGS (4 3) V
Ic + 2Ib – IR = 0
Ic = Ib 17. (d)

+
Ic = IR IR
+2
Vin
(Because is very large) gmVGS rd R Vo
Hence, Ic1 = Ic2 = IR = 4.3 mA

12. (d) –
h fe
Input resistance = = Since, rd >> R
gm gm All current will pass through R,
50 Vout = –gmVGS R
= =5k
10 × 10 3 = –1 × 10–3 × 2 × 10–3 × 10 × 10–3
But overall input resistance seen from source is = –20 mV
RIN = 10 10 5 = 2.5 k Vout 20 mV
Voltage gain = = = 10
Vin 2 mV
13. (d)
18. (b)
Here, VS = +4 V
VG = 0V Assume BJT is in active region and we neglect
VT = –1 V ICBO,
Therefore, VSG = 4V 12 V
VSD = VS – VD 2.2 k
= 4 – I aR
Now for linear region of operation, 13 k
VSD < (VSG + VT)
4 – Ia R < (4 – 1) 2.78 V
Ia R > 1
–3
10 × R > 1
R > 1000 12 × 15 5 × 100
Vth = + = 2.78 V
115 5
14. (d)
Rth = (15 100)
MOSFET is N-channel. Gate through source is
so connected that MOSFET will be in enhance 15 × 100
= = 13 k
mode and so conductivity of the channel will 115
be increased very much and effectively ‘ ’ Ic = Ib
terminal act as short circuited. So Vab = 0 V. 2.78 0.7
But, Ib = = 0.16 mA
13
15. (b)
Ic = 4.8 mA
Ic 12 0.2
= But, Ic(sat) = = 5.36 mA
Ib 2.2 k
3
1 × 10 As, Ic(sat) > Ic(active)
Ib = = 10 µA
100 BJT is in active region.
120 Electronics Engineering Analog Electronics

19. (d) 21. (a)

We assumed BJT is in active region, applying KVL :
KVL in base-emitter circuit, 10 = 10 kIb + 0.7 + (100) (Ib) 100
10 – 0.7 = 1 k × Ic + 270 × Ib 9.3
Ib = = 0.465 mA
(Assuming IC = IE) 20 k
= Ib (270 + 100 k ) V0 = 100 × 0.465 × 100
9.3 = 4.65 V
Ib = mA
370
22. (d)
93
Ic = mA
37 13.7 V
10 0.2
Ic(sat) = = 4.9 mA
2k 12 k

Ic(sat) > Ic(active)

C
BJT is in active region. Vo
10 k
C
20. (b) = 100
Since both transistor are perfectly matched. 10 k
Vi
So, VBE1 = VBE2

1k IR +5 V
P
IC Equivalent A.C. model will be taking,
IC h ie = 1 k
h fe = = 100
i 10 k ib

Q1 Q2
IB IB
Vi 100
k Vin hie hiei b 12 k
1 Av
–5 V

100
100 k as Av
1
1
Av
Ic 1 V VBE2
= exp BE1 = e0 = 1
Ic 2 VT h fe ib × (100 12) k
Vo
AV = =
Since for both are same, therefore, Vin hie × ib
Ib1 = Ib2 = Ib
100 × 10.71 k
Applying KVL to loop as shown, AV = = 1071.42
1k
0 0.7 0.7 ( 5)
IR = = 3.6 mA Vi = hie ib + 104 i
1k
= 103 ib + ib[104 + (1072.42) × 100]
By KCL, IR = Ic + 2Ib
Ic Vo h fe ib × 10.7142 × 103
= Ic + 2 AVS = =
Vi ib [10 3 + 10 4 + 10 2 × 1072.42]
= –9.06
Ic = × IR
+2
AVS = 9.06 10
IR (Because is very large)
 GATE Previous Years Solved Paper 121

23. Sol. 25. Sol.

In input loop: Case-I: VC = 2 V
5 0.7 4.3 10 2
Ib = = = 2.15 mA iC = ...(i)
2k 2k RC
So, Ic = × Ib 10 – iBRB – 0.7 = 0
= 100 × 2.15 mA = 0.215 A 10 0.7
iB = ...(ii)
Now KVL in output loop, RB
VCE = 5 – 0.215 RC +10 V
For active region,
VCE > 0.2 V
RC
0.215 RC < 5 – 0.2 RB
4.8 Vc
RCmax = 22.32
0.215

24. Sol.
Consider the circuit shown in figure,
15 V
Case-II :
When, VC = 4 V
IE = IB + IC
RC RC
RC
10 4
RB IB iC = ...(iii)
RC
VC(9 V) From equation (iii) and (i),
IC
10 4 10 2
=
RC RC
+
0.7 V RC 6 3
– = = = 0.75
RC 8 4

VC = 9 V 27. Sol.
15 9 10 V
so, = IE
RC
6 220
= IE I1 4.7 k
RC
IB
9 0.7 VB
and = IB
RB
VE
8.3
so, = IB 5.3 V I2 = 0.5 mA
RB IE 470

IE 6 × RB
so, =
IB RC × 8.3
RB × 6 VB = 5.3 V
( + 1) = VE = VB – 0.6 = 4.7 V
RC × 8.3
VE
RB IE = = 10 mA
= 105.13 470
RC
122 Electronics Engineering Analog Electronics

10 5.3 5 = 30IB × 4R + 30 × IB × R
I1 = = 1 mA
4.7 k 5 = 150IB × IB × R ...(ii)
IB = I1 – I2 = 0.5 mA Using equation (i) and (ii),
IBRB = 9.3 – 5 = 4.2
IE
= + 1 = 20 and simultaneously putting value of IBR from
IB
equation (ii) in equation (i),
= 19
R
9.3 = I B R 150 + B
28. Sol. R
5 R
+12 V 9.3 = 150 + B
150 R
RB
279 = 150 +
Ra R
I0 = 1 µ A
RB
IR = 1 mA
= 129
R

Q1 Q2 30. Sol.

VBE1 VBE2 +15 V

R I0
10 k

–12 V

VBE1 = VBE2 + I0R 10 k

I0R = VBE1 – VBE2 1k

10.7 V
IR I0
= Vi ln VT ln
I3 I3 Rth
where, Is Reverse saturation current
To calculate Rth d.c. voltage should be short-
IR 1 mA circuited,
VT ln 0.025 ln
I0 1 µA
R= =
I0 1 µA
10 k
3
0.025 ln (10 )
= = 172.7 k
1 µA

29. (d)
In input loop, 10 k
1k
10 = (1 + ) Ib × 4R + IB × RB + 0.7
+ (1 + ) IB × R
Rth
10 = 30IB × 4R + IB × RB + 0.7
+ 30 × IB × R 10 k
9.3 = 150 × IB × R + IB × RB ...(i) Rth = 1 k
1+
Output loop,
= 1k 99.0099
10 = (1 + ) × IB × 4R + 5 V
+ (1 + ) × IB × R Rth = 90.09
 GATE Previous Years Solved Paper 123

31. (d) VGS = 0.6 V

V0 = 600 mV
2V
32. (c)
ID = 5 µA
For NMOS transistor to be in saturation the
Vo condition will be
Vgs > Vth
+
VDS
and Vds Vgs – Vth
+
VGS –
– 33. (d)
Given data:
As, VDS = VGS RD = 4.7 k , gm = 520 µA/V
MOSFET is in saturation, Voltage gain of CS amplifier
= –gm RD
1 W
ID = µnC ox (VGS VT )2 = –520 µAV × 4.7 k
2 L
= –2.44
1 6
5 × 10–6 = × 100 × 10 × 10(VGS 0.5)2
2

Answers
EE BJT Analysis (Section-B)

1. (d) 2. (b) 3. (d)

Solutions
EE BJT Analysis (Section-B)

1. (d) 3. (d)
When Ce is unbypassed, AC model,
h fe Rc Vo
AV 1 = 10 k
hie
Vi hfeIB 10 k
When Ce is bypassed,
h fe Rc
AV2 =
hie + (1 + h fe ) Re Zi = 10 k

Z i = 10 k
AV 1 hie + (1 + h fe ) Re 1 + h fe
= = 1+ Re Mid-band voltage gain,
AV 2 hie hie
A1 RL
Av =
2. (b) Zi
h fe RL
AV 1 1 + h fe Av =
= 1+ Re Zi
AV 2 hie
100 × 10 k
AV 1 = = 100
>1 10 k
AV 2
AV2 < AV1 Av = 100
 41 FET and MOSFET Analysis

ELECTRO NICS EN GINEERIN G Which of the following is correct?

(a) Only statement 1 is true.
(GATE Previous Years Solved Papers)
(b) Only statement 2 is true.
Q.1 Two identical FETs, each characterized by the
(c) Both the statements are true.
parameters gm and rd are connected in parallel.
(d) Both the statements are false.
The composite FET is then characterized by the
parameters. [EC-2002 : 2 Marks]

gm gm r Q.4 For an n-channel MOSFET and its transfer

(a) and 2rd (b) and d
2 2 2 curve shown in the figure, the threshold voltage
r is
(c) 2 gm and d (d) 2gm and 2rd
2 VD = 5 V
[EC-1998 : 1 Mark] D
ID
Q.2 In the MOSFET amplifier of the figure is the
characteristics

VG = 3 V
signal output V1 and V2 obey the relationship
Transfer

RD
VGS S
1V VS = 1 V
+

V1
(a) 1 V and the device is in active region.
+
+ (b) –1 V and the device is in saturation region.
V2 –
Vi –
RD/2 (c) 1 V and the device is in saturation region.
–
(d) –1 V and the device is in active region.
[EC-2005 : 2 Marks]
V V2
(a) V1 = 2 (b) V1 =
2 2 Q.5 In the CMOS inverter circuit shown, if the
(c) V1 = 2V2 (d) V1 = –2V2 transconductance parameters of the NMOS and
[EC-1998 : 1 Mark] PMOS transistors are:

Q.3 Consider the following statements in Wn W

Kn = K p = µnC ox = µ pC ox P = 40 µA/V 2
connection with the CMOS inverter in the figure, Ln LP
where both the MOSFETs are of enhancement and their threshold voltages are
type and both have a threshold voltage of 2 V. VTH n = VTH p = 1 V, the current I is
Statement-1 : T1 conducts when Vi 2 V.
5V
Statement-2 : T1 is always in saturation when
Vo = 0 V.
PMOS
+5V

T2 I
2.5 V
Vi Vo
NMOS
T1
 GATE Previous Years Solved Paper 125

(a) 0 A (b) 25 µA The current Ix is related to Ibias as

(c) 45 µA (d) 90 µA (a) Ix = Ibias + Is
[EC-2007 : 2 Marks] (b) Ix = Ibias
(c) Ix = Ibias – Is
Q.6 Two identical NMOS transistors M1 and M2 are
connected as shown below. Vbias is chosen so Vout
(d) I x = I bias VDD
that both transistors are in saturation. The RE

Iout [EC-2008 : 2 Marks]

equivalent gm of the pair is defined to be
Vi
Statement for Linked Answer Question (8 and 9):
at constant Vout. Consider the CMOS circuit shown, where the gate
Iout voltage VG of the n-MOSFET is increased from zero,
Vout while the gate voltage of the p-MOSFET is kept constant
at 3 V. Assume that, for both transistors, the magnitude
Vbias M2
of the threshold voltage is 1 V and the product of the
transconductance parameter and the (W/L) ratio, i.e.
the quantity µCox(W/L), is 1 mA, V–2.
Vi M1 5V

3V
The equivalent gm of the pair is
Vo
(a) the sum of individual gm’s of the transistors.
(b) the product of individual g m ’s of the VG
transistors.
(c) nearly equal to the gm of M1.
(d) nearly equal to the gm/go of M2.
[EC-2008 : 2 Marks] Q.8 For small increase in VG beyond 1 V, which of
the following gives the correct description of the
Q.7 For the circuit shown in the following figure, region of operation of each MOSFET?
transistors M1 and M2 are identical NMOS (a) Both the MOSFETs are in saturation region.
transistors. Assume that M2 is in saturation and
(b) Both the MOSFETs are in triode region.
the output is unloaded.
(c) n-MOSFET is in triode and p-MOSFET is in
VDD saturation region.
(d) n-MOSFET is in saturation and p-MOSFET
RE is in triode region.
Ibias
V out [EC-2009 : 2 Marks]

Va Ix Q.9 Estimate the output voltage Vo for VG = 1.5 V.

1 1
M1 M2 (a) 4 V (b) 4 + V
2 2
Is
3 3
(c) 4 V (d) 4 + V
2 2
[EC-2009 : 2 Marks]
 126 Electronics Engineering Analog Electronics

Q.10 In the circuit shown below, for the MOS VB

transistors, µnC ox = 100 mA/V 2 and the ID
threshold voltage VT = 1 V. The voltage Vx at the
source of the upper transistor is
M
6V

5V W/L = 4 (a) 12.5 (b) 25

Vx (c) 50 (d) 100

[EC-2013 : 2 Marks]
W/L = 1
Q.13 In a MOSFET operating in the saturation region,
the channel length modulation effect causes
(a) an increase in the gate-source capacitance.
(a) 1 V (b) 2 V (b) a decrease in the transconductance.
(c) 3 V (d) 3.67 V (c) a decrease in the unity-gain cut-off
[EC-2011 : 2 Marks] frequency.
(d) a decrease in the output resistance.
Q.11 In the CMOS circuit shown, electron and hole
[EC-2013 : 2 Marks]
mobilities are equal, and M1 and M2 are equally
sized. The device M1 is in the linear region if Q.14 For the n-channel MOSFET transistor shown in
figure the threshold voltage VTh is 0.8 V. Neglect
5V
channel length modulation effects. When the
M1 drain voltage VD = 1.6 V, the drain current ID
VTp = 1 V was found to be 0.5 mA. If VD is adjusted to be
2 V by changing the values of R and VDD, the
Vin
new value of ID (in mA) is
VTn = 1 V VDD
M2 R

(a) Vin < 1.875 V G

(b) 1.875 V < Vin < 3.125 V S
(c) Vin > 3.125 V
(d) 0 < Vin < 5 V [EC-2012 : 2 Marks] (a) 0.625 (b) 0.75
Q.12 The small signal resistance (i.e., dVB/dID) in kW (c) 1.125 (d) 1.5
offered by the n-channel MOSFET ‘M’ shown in [EC-2014 : 2 Marks]
the figure below, at a bias point of VB = 2 V is
Q.15 For the MOSFET shown in the figure, the
(device data for M, device transconductance
threshold voltage Vt = 2 V and
parameter kN = µnCOX ( W / L ) = 40 μA /V 2 ,
threshold voltage VTN = 1 V, and neglect body 1 W
K= µC = 0.1 mA/V 2 . The value of ID
effect and channel length modulation effects) 2 L
(in mA) is _______ .
 GATE Previous Years Solved Paper 127

VDD = +12 V
Q.18 What is the voltage Vout in the following circuit?

VDD
R1 10 k

R2 10 k ID
10 k

Vout

V SS = –5 V

[EC-2014 : 2 Marks]

Q.16 For the MOSFET M 1 shown in the figure, (a) 0 V

assume W/L = 2, VDD = 2.0 V, µnCox = 100 mA/V2 ( VT of PMOS + VT of NMOS)
and VTh = 0.5 V. The transistor M1 switches from (b)
2
saturation region to linear region when Vin
(in Volts) is _______ . (c) Switching threshold of inverter
(d) VDD
VDD
[EC-2016 : 1 Mark]
R = 10 k

Vout Q.19 In the circuit shown in the figure, transistor M1

is in saturation and has transconductance
Vin M1
gm = 0.01 Siemens. Ignoring internal parasitic
capacitances and assuming the channel length
modulation to be zero, the small signal input
[EC-2014 : 2 Marks]
pole frequency (in kHz) is _______ .
Q.17 In the circuit shown, both the enhancement
VDD
mode NMOS transistor have the following
characteristics: kn = µnCox(W/L) = 1 mA/V2, 1k
VTN = 1 V. Assume that the channel length
Vo
modulation parameter is zero and body is
shorted to source. The minimum supply voltage 50 pF
VDD (in Volts) needed to ensure that transistor Vin M1
M1 operates in saturation mode of operation is 5k
________ .
VDD

[EC-2016 : 2 Marks]
M2
Q.20 In the circuit shown in the figure, the channel
length modulation of all transistor is non-zero
( 0). Also, all transistor operate in saturation
2V M1 and have negligible body effect. The ac small
signal voltage gain (Vo/Vin) of the circuit is

[EC-2015 : 2 Marks]
 128 Electronics Engineering Analog Electronics

Q.22 An n-channel enhancement mode MOSFET is

VDD
biased at VGS > VTh and VDS > (VGS – VTh), where
VGS is the gate-to-source voltage. VDS is the
drain-to-source voltage and VTh is the threshold
M3 M2
voltage. Considering channel length
VG modulation effect to be significant, the MOSFET
behaves as a
Vo
(a) voltage source with zero output impedance.
Vin M1 (b) voltage source with non-zero output
impedance.
(c) current source with finite output
impedance.
(a) gm1 ( r01 r02 r03 ) (d) current source with infinite output
impedance.
1 [EC-2017 : 1 Mark]
(b) gm1 r01 r03
gm 3
Q.23 Assuming that transistors M 1 and M 2 are
identical and have a threshold voltage to 1 V,
1 the state of transistors M 1 and M 2 are
(c) gm1 r01 r02 r03
gm2 respectively
3V
1
(d) gm1 r01 r03 r02
gm 3 2.5 V M2

[EC-2016 : 2 Marks]

Q.21 For the circuit shown, assume that the NMOS 2V M1

transistor is in saturation. Its threshold voltage
Vtn = 1 V and its transconductance parameter

W (a) saturation, saturation

µnC ox = 1 mA/V 2 . Neglect channel
L (b) linear, linear
(c) linear, saturation
length modulation and body bias effects. Under
these conditions, the drain current ID (in mA), is (d) saturation, linear
_________ . [EC-2017 : 2 Marks]

VDD = 8 V Q.24 Two identical NMOS transistors M1 and M2 are

RD 1k connected as shown below. The circuit is used
R1 3M as an amplifier with the input connected
ID
between G and S terminals and the output taken
between D and S terminals, Vbias and VD are so
adjusted that both transistors are in saturation.
R2 5M The transconductance of this combination is
RS 1k
iD
defined as gm = while the output
vGS
[EC-2017 : 2 Marks]
 GATE Previous Years Solved Paper 129

The voltage (in volts, accurate to two identical

v
resistance is ro = DS , where iD is the current places at Vx is) _______ .
iD
[EC-2018 : 2 Marks]
flowing into the drain of M2. Let gm1, gm2 be the
transconductances and r01, r02 be the output Q.26 A CMOS inverter, designed to have a mid-point
resistance of transistors M1 and M2, respectively. voltage V1 equal to half of Vdd, as shown in the
figure has the following parameters:
VD
D Vdd = 3 V
µnCox = 100 mA/V2; Vtn = 0.7 V for nMOS
Vbias M2
µpCox = 40 mA/V2, Vtp = 0.9 V for pMOS

The ratio of (W/L)n to (W/L)p is equal to ____

G M1 (rounded off to three decimal places).

Vout
S

Which of the following statements about Vdd

estimates for gm and r0 is correct?
(a) gm gm1 gm2 r02 and r0 r01 + r02
Vdd/2
(b) gm gm1 + gm2 and r0 r01 + r02
(c) gm gm1 and r0 r01 gm2 r02
(d) gm gm1 and r0 r02
Vin
[EC-2018 : 1 Mark] V Vdd
V1 = dd
2
Q.25 In the circuit shown below, the (W/L) value for
M 2 is twice that for M 1 . The two nMOS [EC-2019 : 2 Marks]
transistors are otherwise identical. The
threshold voltage VT for both transistors is 1.0 V. Q.27 In the circuit shown, the threshold voltages of
Note that VGS for M2 must be > 1.0 V.
the pMOS Vtp and nMOS (Vtn) transistors are
3.3 V both equal to 1 V. All the transistors have the
2.0 V M2 same output resistance rds of 6 M . The other
parameters are listed below:
Vx
W
µnCox = 60 µA/V2; =5
M1 L nMOS

W
µpCox = 30 µA/V2; = 10
L pMOS
Current through the nMOS transistors can be
µn and µp are the carrier mobilities, and Cox is
modeled as:
the oxide capacitance per unit area. Ignoring
W 1 2 the effect of the channel length modulation and
IDS = µC ox (VGS VT )VDS VDS
L 2 body bias, the gain of the circuit is _____
for VDS VGS – VT (rounded off to 1 decimal place).

W (VGS VT )2
I DS = µC ox for VDS VGS – VT
L 2
 130 Electronics Engineering Analog Electronics

Vdd = 4 V (a) 10 V and –13 V (b) 13 V and –7 V

(c) 10 V and –10 V (d) 3 V and –3 V
[EC-2020 : 2 Marks]

Q.30 Using the incremental low frequency small-

signal model of the MOS device, the Norton
Vout equivalent resistance of the following circuit is
V DD

Vin R

gm, rds

[EC-2019 : 2 Marks]

Q.28 In the circuit shown, V1 = 0 and V2 = Vdd. The

1
other relevant parameters are mentioned in the (a) rds + R + gm rds R (b) rds + +R
figure. Ignoring the effect of channel length gm
modulation and the body effect, the value of Iout rds + R
(c) rds + R (d)
is _______ mA (rounded off to 1 decimal place). 1 + gm rds
Vdd [EC-2020 : 2 Marks]

Q.31 For the transistor M1 in the circuit shown in the

W/L = 10 W/L = 10 W/L = 40 figure, µnCox = 100 µA/V2 and (W/L) = 10, where
µn is the mobility of electron Cox is the oxide
Iout
Vdd capacitance per unit area. W is the width and L
V1 W/L = 5 W/L = 5 V2 is the length.
1 mA VDD = 3 V

RD = 20 k
W /L = 2 W /L = 3
Vout

M1
VGS

[EC-2019 : 2 Marks]

Q.29 An enhancement MOSFET of threshold voltage The channel length modulation coefficient is
3 V is being used in the sample and hold circuit ignored. If the gate-to-source voltage VGS is 1 V
given below. Assume that the substrate of the to keep the transistor at the edge of saturation,
MOS device is connected to –10 V. If the input then the threshold voltage of the transistor
voltage Vi lies between ± 10 V. The minimum (Rounded off to one decimal place) is _____ V.
and the maximum values of VG required for
[EC-2021 : 2 Marks]
proper sampling and holding respectively, are
Q.32 In the circuit shown in the figure, the transistors
Vi Vo
M1 and M2 are operating in saturation. The
channel length modulation coefficients of both
transistors are non-zero. The transconductance
VG of the MOSFETs M1 and M2 are r01 and r02,
respectively.
 GATE Previous Years Solved Paper 131

(a) equal to 0 V (b) more than 2 V

VDD
(c) less than 2 V (d) equal to 2 V
[EC-2022]
Vin M2
Q.34 The ideal long channel nMOSFET and
Vout
pMOSFET devices shown in the circuits have
M1 threshold voltages of 1 V and –1 V, respectively.
The MOSFET substrates are connected to their
respective sources. Ignore leakage currents and
Ignoring the body effect, the ac small signal assume that the capacitors are initially
discharged. For the applied voltages as shown,
voltage gain ( Vout / Vin ) of the circuit is
the steady-state voltages are _______ .

1 5V
(a) gm1 r01 r02
gm 2

(b) –gm2 (r01 r02)

5V V1
1 nMOSFET
(c) gm 1 r01 r02 1 µF
gm 1

1
(d) gm 2 r02
gm1 –5 V

[EC-2021 : 1 Mark]

Q.33 Consider the CMOS circuit shown in the figure 5V V2

(substrates are connected to their respective pMOSFET 1 µF
sources). The gate width (W) to gate length (L)
ratios (W/L) of the transistors are as shown.
Both the transistors have the same gate oxide
(a) V1 = 5 V, V2 = 5 V
capacitance per unit area. For the pMOSFET,
(b) V1 = 5 V, V2 = 4 V
the threshold voltage is –1 V and the mobility
of holes is 40 cm2/V-s. For the nMOSFET, the (c) V1 = 4 V, V2 = 5 V
threshold voltage is 1 V and the mobility of (d) V1 = 4 V, V2 = –5 V [EC-2022]
electrons is 300 cm2/V-s. The steady-state Q.35 Select the correct statement(s) regarding CMOS
output voltage Vo is ______ . implementation of NOT gates:
(a) Noise Margin High (NMH) is always equal
4V
to the Nose Margin Low (NML), irrespective
of the sizing of transistors.
pMOSFET W (b) Dynamic power consumption during
=5
L
switching is zero.
Vo (c) For a logical high input under steady-state,
the nMOSFET is in the linear regime of
W operation.
=1
nMOSFET L
(d) Mobility of electrons never influences the
switching speed of the NOT gate.
[EC-2022]
 132 Electronics Engineering Analog Electronics

Q.36 Consider an ideal long channel nMOSFET acts as a linear amplifier. vi is the small signal
(enhancement mode) with gate length 10 µm ac input voltage. vA and vB represent the small
and width 100 µm. The product of electron signal voltages at the nodes ‘A’ and ‘B’,
mobility (µn) and oxide capacitance per unit area respectively. The value of v A/v B is ______
(Cox) is µnCox = 1 mA/V2. The threshold voltage (Rounded off to one decimal place).
of the transistor is 1 V. For a gate-to-source VDD
voltage, VGS = [2 – sin(2t)] V and drain-to-source
voltage VDS = 1 V (substrate connected to the 4k
source), the maximum value of the drain-to-
A
source current is _______ .
(a) 40 mA (b) 20 mA
(c) 15 mA (d) 5 mA Vi B
[EC-2022]
2k
VGG
Q.37 Consider the circuit shown with an ideal long
channel nMOSFET (enhancement mode,
substrate is connected to the source). The [EC-2022]
transistor is appropriately biased in the
saturation region with VGG and VDD such that it

Electronics & Electrical Engineering

GATE Previous Years Solved Paper

A n swe rs & Expl a n a t i o n s

Answers
EC FET and MOSFET Analysis

1. (c) 2. (c) 3. (a) 4. (c) 5. (c) 6. (c) 7. (b) 8. (d)

9. (d) 10. (c) 11. (a) 12. (b) 13. (d) 14. (c) 15. (0.9) 16. (1.5)

17. (3) 18. (c) 19. (57.87) 20. (c) 21. (2) 22. (c) 23. (c) 24. (c)

25. (0.422) 26. (0.225) 27. (–900) 28. (6) 29. (b) 30. (d) 31. (0.5) 32. (c)
33. (c) 34. (c) 35. (c) 36. (c) 37. (–2)
 GATE Previous Years Solved Paper 133

Solutions
EC FET and MOSFET Analysis

1. (c) 6. (c)
r I D1
2gm and d gm1 =
2 Vi
ID1 = ID2
rd I D2 I D1
µV gs I out
gm = = =
Vi Vi Vi
rd gm = gm1
µV gs

7. (b)
rd/2 µV gs It is a current mirror circuit,

r IG1 = IG2 = 0
So, rd = d
2 Ix = Is
µ = µ = gm rd
Ibias = Is + IG1 + IG2
rd
= gm = gm rd
2 = Is + 0 + 0
gm = 2g m Ix = Ibias

2. (c) 8. (d)
V1 = 2V2 When VG is little higher than 1 V.
V1 = IDRD • For n-MOSFET:
IS = ID VGSn = VG = 1+ V (1+ Little higher than 1)
R I R V VGSn – VTn = 0+ V (0+ Little higher than 0)
V2 = Is D = D D = 1
2 2 2 • For p-MOSFET:
So, V1 = 2V2
VSGP = VDD – 3 V = 2 V
3. (a) VSGP VTP = 1 V
Statement-2 is false because VDS will be less than
VGS = –VT, if Vo = 0. (VGSn – VTn) < (VSGP VTP )
So, n-MOSFET will be in saturation region
4. (c)
and p-MOSFET will be in triode region.
From the graph its clear that,
VTh = 1 V 9. (d)
VGS = 3 – 1 = 2 V When VG = 1.5 V:
VDS = 5 – 1 = 4 V
• For n-MOSFET:
Since, VDS VGS – VT
VGSn = VG = 1.5 V
So, MOSFET is saturation region.
VGSn – VTn = 0.5 V
5. (c) • For p-MOSFET:
VGS for each MOS is 2.5 V. VSGP = VDD – 3 V = 2 V
VT = 1 volt, device parameter K = 40 mA/V2
VSGP VTP = 2 V 1 V = 1 V
K
So, ID = (VGS VT )2
2 (VGSn VTn ) < (VSGP VTP )
= 20(2.5 – 1)2 = 45 µA
134 Electronics Engineering Analog Electronics

So, n-MOSFET will be in saturation region and Hence both MOS will be in saturation,
p-MOSFET will be in triode region. W
ID1 = µnC ox (VGS VT )2
To determine Vo : L
IDSn = ISDP
ID1 = µnCox(4) (4 – Vx)2
2
Kn(VGSn – VTn)2 = K p [2 (VSGP VTP ) VSDP VSDP ]
Similarly, ID2 = µnCox(1) (Vx – 1)2
Given that, Kn = K p
So, (0.5) = 2(1 V) (VDD – Vo) – (VDD – Vo)2
2
But, ID1 = ID2
0.25 = 2(5 – Vo) – (5 – Vo)2
µnCox(4) (4 – Vx)2 = µnCox(1) (Vx – 1)2
0.25 = 10 2 Vo 25 + 10 Vo Vo2 On solving, Vx = 3 Volt

Vo2 8Vo + 15.25 = 0 11. (a)

For PMOS, VSG = VS – VG = 5 – Vin
8 ± 64 4(15.25)
Vo = For PMOS to be ON,
2
VSG > VTP
3
= 4+ = 4.866 V or 3.134 V 5 – Vin > 1
2
Vin < 4
Check for valid Vo :
So, Vin must be less than 4 V for MOS to be in
• We know that, n-MOSFET is in saturation
linear regions so option (c) and (d) are rejected.
region and p-MOSFET is in triode region.
Now we know that for small Vin output is high
So, Vo VGSn – VTn
and PMOS is in linear region and NMOS is in
Both the possibilities of Vo satisfies this
cut-off region. Similarly for high Vin PMOS is in
and [VSDP = (5 – Vo)] > [VGSP VTP = 1 V] cut-off and NMOS is in linear region and for Vin
in between both are in saturation.
• For Vo = 4.866 V
So, PMOS will be in linear region for
[VSDP = 0.314 V] < [VSGP VTP = 1 V] Vin < 1.875 V.
• For Vo = 3.134 V
12. (b)
[VSDP = 0.866 V] > [VSGP VTP = 1 V] ID
gm =
VGS
3
So, the valid value of Vo is 4.866 V or 4 + V. VB = VG
2
VS = 0
10. (c) VGS = VG – VS
For upper MOS, = VG – 0 = VG = VB
VDS = 6 – Vx VB 1
=
VGS – VT = 5 – Vx – 1 ID gm
= 4 – Vx VD = VG
Upper MOS will be in saturation because, VD – VS = VG – VS
VDS > VGS – VT VDS = VGS
For lower MOS, VDS > VGS – VT
VDS = Vx So, the given MOSFET is in saturation region,
VGS – VT = Vx – 1
W
So, VDS > VGS – VT gm = µnCOX (VGS VT )
L
 GATE Previous Years Solved Paper 135

gm = 40 × 10–6 × (2 – 1) So, for minimum VDD,

= 4 × 10–5 S VDS1 = VGS1 VTN
VB 1 1
= = VDS1 = 2 – 1 = 1 V
ID gm 4 × 10 5
VD1 = 1 V
100 × 10 3
= = 25 k
4 and ID1 = K (VGS VTN )2
1

14. (d) 1 mA
ID1 = × (2 1)2 = 1 mA
We know that, V2
ID = Kn(VGS – VT)2 [Q VDS > VGS – VT] Now, transistor M2,
0.5 mA VDS = 0 V
So, Kn = = 0.78 mA/V So, it will work into saturation region and same
(1.6 0.8)2
current will flow,
Therefore, for VD = 2 V
ID = 0.78(2 – 0.8)2 = 1.123 mA ID2 = ID = K (VGS VTN )2
1 2

15. Sol. 1 mA = 1 mA/V2 × (VDD – 1 – 1)2

( VS2 = VD1 )
ID1 = ID2 = Kn (VGS Vt )2 VDD = 3 V

1 W 19. Sol.
= µnC ox (VGS Vt )2
2 L With respect to A.C.
= 0.1(5 – 2)2 = 0.9 mA

16. Sol.
50 pF 1k
For saturation, Vo
ID = Kn(VGS – Vt)2 C
µnC ox W 5k
ID = (VGS Vt )2 Vin
2 L
1
ID = × 100 × 10 6 × 2 (Vo )2
2 Taking Miller’s equivalent and assume, ro =
6
ID = 100 × 10 Vo2 ...(i) 5k

Now, KVL in outer loop we get, R +

VDD = ID × 10 k + Vo ...(ii) Vin C(1 – Av) VSS C 1
1
1k
gmVgs Av
From equations (i) and (ii), we get
–
6 3
2 = 100 × 10 × 10 × 10 Vo2 + Vo

Vo2 + Vo 2 =0
Av = –gmRD
Vo = 1 V
= –0.01 × 103 = –10
VDS = VGS – Vt
Small signal input pole frequency,
Vin = 1.5 V
1
= 3 12
17. Sol. 2 × 5 × 10 × 50 × 10 (1 + 10)
Lower transistor (M1) to work in saturation, = 57.87 kHz
VDS1 = VGS1 VTN
136 Electronics Engineering Analog Electronics

20. (c) 22. (c)

VDD The small signal equivalent circuit of MOSFET
in saturation is as given below.
G D
+
M3 M2
Vgs gm3Vgs3 r0

Vo –
Vin M1
S
So, when the channel length modulation effect
is significant, the MOSFET can be modelled as
S3
Vgs 3 = 0 G3 a current source with finite output impedance.
G3
+ 23. (c)
D2
gm3Vgs3 r03 Vgs2 gm2Vgs2 r02
– 3V

D3
G1 D1 +
V01
Vin 2.5 V M2 V DS2
+
+ –
Vgs1 gm1Vgs1 r01 VGS2 –
–
+
2V M1 V DS1 = Vx
+ –
VGS1 –
Node equation at P1 :
Vo Vo Vo
gm1Vgs1 + + + gm2 Vgs2 = 0 VGS1 = 2 V
r01 r03 r02

1 1 1 VGS2 = 2.5 – Vx
Vo + + gm2 + = gm1Vin
r01 r02 r03 VDS1 = Vx

Vo 1 VDS2 = 3 – Vx
Av = = gm1 r01 r02 r03
Vin gm2 Assume both MOSFETs in saturation and equate
their currents,
21. Sol.
I DS1 = I DS2
8× 5
VGS = 1 × ID = 5 ID
8 kn k
(2 1)2 = n (2.5 Vx 1)2
(Here ID is numerically in mA) 2 2
ID = 5 – VGS ...(i) After solving, Vx = 0.5 V, 2.5 V
µnC ox W Vx cannot be 2.5 V.
ID = (VGS VT )2
2 L Because this will make M2 OFF.
1 2 Hence Vx may be 0.5 V.
5 – VGS = (VGS 1)
2 M1 is in linear region.
10 – 2VGS = 2
VGS + 1 2 VGS M2 is in saturation region.
2 = 9 VGS = 3 V To verify further,
VGS
ID = 5 – 3 = 2 mA
I DS1 = I DS2
 GATE Previous Years Solved Paper 137

Vx2 k 25. Sol.

kn (2 1)Vx = n (2.5 Vx 1)2
2 2 µ nC ox W
Let, Kn =
2 L
VGS2 = 2.5 V Vx must be greater than VTh = 1 V
Given that,
After solving, Vx = 0.588 V, 1.91 V W W
Hence correct value of Vx = 0.588 V = 2
L 2 L 1
This verifies above conclusion i.e.
So, Kn2 = 2Kn1
M1 Linear region
M2 Saturation region For M1 :
VGS1 VT = 2 – 1 = 1 V
24. (c)
For M2 :
iD
D VGS2 VT = 2 – Vx – 1
= 1 V – Vx < 1 V
M2
VDS2 = (3.3 – Vx) > (VGS VT )
2
iD1 = iD So, M1 will be in linear region and M2 will be in
saturation region,
G M1
+
Vgs
ID1 = ID2
–
S 2
Kn1 [2(VGS1 VT )VDS1 VDS ] = Kn2 (VGS2 VT )2
1

Kn1 [2 (2 1)Vx Vx2 ] = 2Kn1 (2 Vx 1)2

ID i iD
gm = = D = 1 = gm1
Vin v gs v gs 2Vx Vx2 = 2 (1 + Vx2 2 Vx )
To calculate ro : 2
= 2Vx 4Vx + 2

+ + Ix 3Vx2 6Vx + 2 = 0
V gm1V 2 r02
2
2
–
Vx2 2Vx + =0
Ix 3
0A
Vx Vx 8
+
4
+
Vx = 1 ± 3 = 1± 1 V
V 1=0V gm2V ro1 Ixr01
1 4 3
–
– – VGS2 = (2 – Vx) VT
(1 – Vx) 0

V = –Ix r01 1
2 So, valid value, Vx = 1 = 0.4226 V
3
(Vx I x r01 )
Ix = gm2 v 2 + 26. Sol.
r02
Vx IDn = IDp and both will be in saturation.
r0 = = r01 + r02 + r01 r02 gm2 VDD
Ix If, Vin = = 1.5 V = VGSN = VSGP
2
r01 r02 gm2
1 W
(µnC ox ) [VGSN VTN ]2
2 L n
138 Electronics Engineering Analog Electronics

1 W
= (µ pC ox ) [VGSP + VTP ]2 1
2 L p R3 = rds
gm
6 W
100 × 10 [1.5 0.7]2 M3 M2
L n

W 1
= 40 × 10 6 [1.5 0.9]2 R4 =
gm
rds
L p

W M4
2
L n 40 (0.6)
= × = 0.225
W 100 (0.8)2
L p
G2 D2
27. Sol. +
M3 and M4 are identical PMOS transistor and
they have equal current. R4 R3 Vgs rds2

Hence their VSG should be equal.

–
Vdd = 4 V
Vgs = 0 S2

M1 is common source amplifier.

Vout
M1 M2 = Av = gm1 × ( rds2 rds1 )
Vin
= –300 M × 3 M
Vout
= –900

M4 M1 Vin 28. Sol.

V dd

M7 I5 M5 M6 I6
V
VSG3 = VSG4 = DD = 2 V
2 I3
Vdd
µ pC ox W
ISD = (VGS VT )2 V1 = 0
M3 I4 M4 V2 = VDD
2 L p I1 = 1 mA

30 I2
=× 10(2 1)2 = 150 µA
2 W/L = 2 M1 M2 W /L = 3
Now, by using current mirror property all
transistor should have equal current,
IDSN = ISDP = 150 µA
For M1 : I2 ( W / L )2 3
= =
I1 ( W / L )1 2
W
gm1 = 2µnC ox × IDS 3
L × I1 = 1.5 mA
I2 =
2
= 2 × 60 × 5 × 150 = 300 µ M3 is OFF because, V1 = 0 I3 = 0
M2, M3 and M4 from active load for M1. This active
M4 is ON because, V2 = VDD
load in equivalent to resistance rds2 i.e. 6 M . I5 = I4 = I2 = 1.5 mA
 GATE Previous Years Solved Paper 139

I6 ( W / L )6 40 VDD = 3 V
= = =4
I5 ( W / L )5 10
ID RD = 20 k
I6 = 4I5 = 4 × 1.5 = 6 mA
Iout = I6 = 6 mA Vout
+
29. (b) M1 VDS
VGS –

Vi Vo
10 V
Edge of saturation,
VDS = VGS – VT
VG VDS = 1 – VT
–10 V
1 W
ID = µnC ox (VGS VT )2
For holding MOSFET should be OFF, 2 L
Vi min –10 V Applying KVL, we can write,
VG – Vi min < 3 VDS = VDD – IDRD
VG < 3 – 10 V –7 V 1
(1 – VT) = 3 × 100 µ × 10(1 VT )2 (20 k)
For sampling, 2
VG – Vimax > 3 1 – VT = 3 – 10(1 – VT)2
VG > 3 + Vimax
= 3 10 10 VT2 + 20 VT
VG > 13
10 VT2 21VT + 8 = 0
30. (d)

G D VT2 2.1VT + 0.8 = 0

+ (VT – 1.6) (VT – 0.5) = 0
V gm v rds VT = 1.6 V and VT = 0.5 V
Ix
To turn-on the transistor VGS > VT
–
Ix So, VT = 0.5 V
S R

32. (c)
Vx
Step-1 : AC model of the given circuit
(All DC sources = 0)

D2
V = –Vx V out
Vin M2 M1
Vx = (Ix – gmVx) rds + IxR
Vx (1 + gm rds) = (rds + R) Ix
S2 Req
V R + rds
RN = x =
VDD = 0
I x 1 + gm rds
Consider the circuit w.r.t M1,
31. (0.5)
µnCox = 100 µA/V2
M1
W
= 10
L Req
= 0
VGS = 1V 1
Req = r01 ...(1)
VT = ? gm1
140 Electronics Engineering Analog Electronics

Step-2: Small signal model of the given circuit, µnC ox W

× (VGSN VTN )2
2 L N
G2 D2
+ + µ pC ox W
= × (VSGP VTP )2
2 L P
Vin Vgs2 gm2Vgs2 r02 Req Vout 300 × 1 (Vo – 1)2 = 40 × 5(4 – Vo – 1)2
2
– – 3(Vo2 + 1 2Vo ) = 2(9 + Vo 6Vo )
S2 S2
Vo2 + 6Vo 15 = 0

6 ± 36 + 4 × 15 6 ± 96
Vo = =
G2 D2 Io 2 2
+ + Vo = 1.898 V, –7.89 V
Vo cannot be negative because Vo should lie
Vin Vgs2 gm2Vgs2 RL Vout
between 0 and 4 V.
Vo = 1.898 V
– –
S2 S2 34. (c)
5V

where, RL = r02 Req ...(2)

Vout = IoRL = –gm2 Vgm2 RL ...(3)

5V V1
Vout nMOSFET
= –gm2 RL ...(4) 1 µF
Vgs 2
But, Vgs2 = Vin
Vout nMOSFET will provide
= Av = gm 2 [ r02 Req ] V1 = 5 – VT = 4 V
Vin
–5 V
1
= gm2 r02 r01
gm1

5V V2
33. (c)
pMOSFET
Both MOSFETs are in saturation because drain 1 µF
is shorted to gate,
4V
pMOSFET will provide
V2 = 5 V
W
=5
L
35. (c)
Vo (a) NML = VIL – VOL
NMH = VOH – VIH
W
=1
L when, VTN = VTP
and Kn = K p
VDD
IDSN = ISDP VIT =
2
 GATE Previous Years Solved Paper 141

and NML = NMH

Kp ID = µnC ox
W
L {
VGS Vt )VDS
1 2
2
VDS }
when, > 1, VIL , VIH
Kn W 2 1
IDmax = µnCox L (VGS max Vt )VDS 2 VDS
NMH and NML
Kp 2 1
when, > 1, VIL , VIH = 1 mA/V × 10 (3 1)1 ×1
2
Kn
= 10[1.5] = 15 mA
NMH and NML
i.e., NML and NMH depends on transistor 37. (–2)
sizing and they are equal for certain
Consider Va as an output then the small signal
condition only.
model is,
(b) Dynamic power consumption during
switching is non-zero due to capacitive
loading of next stage. 4k RD

(c) For : Va
VDD VTP Vin VDD PMOS cut-off
(Logic high input) NMOS Linear
(d) Switching speed depends on charging and Vi
discharging of load capacitor for pull up 2k RS
and pull down of output voltage
respectively. (CS in bypass amplifier)
Fast charging and discharging of capacitor
depends on mobility of charge carrier, Va gm RD
Voltage gain, = ...(1)
charging = RPMOS CL
Vi 1 + gm Rs
(to bring output at logic high) Consider Vb as an output, then the small signal
discharging = RNMOS CL model,
(to bring output at logic low)
and also propagation delay,
4k RD
PLH + PHL
p =
2
CL VDD
where, TPLH =
W
µ pC ox (VGS VTP )2 Vi Vb
L
CL VDD 2k RS
TPHL =
W
µ pC ox (VGS VTN )2
L (CD amplifier)
Using average charge model.
Vb gm Rs
Hence, (c) is only correct statement. Voltage gain, = ...(2)
Vi 1 + gm Rs
36. (c) On dividing equation (1) and (2),
VGS = [2 – sin2t] Volt 1V
Va /Vi RD
VGS min = 2–1=1V =
Vb /Vi Rs
VGS max = 2 – (–1) = 3 V
Va 4k
VDS = 1V = = 2
–1 V Vb 2k
VDS < VGS – Vt (Linear)
 5 Frequency Response
Amplifiers
ELECTRO NICS EN GINEERIN G The input impedance of the feedback amplifier
with the feedback impedance Z connected as
(GATE Previous Years Solved Papers)
shown will be
Q.1 In a multi-stage RC-coupled amplifier the Z
coupling capacitor
(a) limits the low frequency response.
+ +
(b) limits the high frequency response.
Vi Vo
(c) does not effect the frequency response. N
– –
(d) blocks the d.c. components without effecting
the frequency response.
[EC-1993 : 1 Mark]
1
Q.2 An RC-coupled amplifier is assumed to have a (a) Z 1 (b) Z(1 – K)
K
single-pole frequency transfer function. The
maximum lower cut-off frequency allowed for Z Z
(c) (d)
the amplifier to pass 50 Hz. Square wave with K 1 1 K
no more than 10% tilt is ______ . [EC-1996 : 2 Marks]
[EC-1995 : 1 Mark]
Q.6 The fT of a BJT is related to its gm, C and Cµ as
Q.3 An amplifier has an open-loop gain of 100 and follows:
its lower and upper cut-off frequency of 100 Hz C + Cµ 2 (C + Cµ )
and 100 kHz respectively, a feedback network (a) fT = (b) fT =
gm gm
with a feedback factor of 0.99 is connected to
the amplifier. The new lower and upper cut-off gm gm
(c) fT = (d) fT =
frequencies are at ______ and ______ . C + Cµ 2 (C + Cµ )
[EC-1995 : 1 Mark] [EC-1998 : 1 Mark]

Q.4 An npn transistor has a beta cut-off frequency Q.7 An npn transistor (with C = 0.36 pF) has a unity
f of 1 MHz and common emitter short-circuit gain cut-off frequency fT of 400 MHz at a dc bias
low frequency current gain 0 of 200 at unity current IC = 1 mA. The value of its Cµ (in pF) is
gain frequency fT and the alpha cut-off frequency approximately (VT = 26 mV)
f respectively are (a) 15 (b) 30
(a) 200 MHz, 201 MHz (c) 50 (d) 96
(b) 200 MHz, 1999 MHz [EC-1999 : 2 Marks]
(c) 199 MHz, 200 MHz
Q.8 An amplifier is assumed to have a single-pole
(d) 201 MHz, 200 MHz
high-frequency transfer function. The rise time
[EC-1996 : 1 Mark] of its output response to a step function input is
Q.5 In the circuit shown in figure is a finite gain 35 nsec. The upper –3 dB frequency (in MHz)
amplifier with a gain of K, a very large input for the amplifier to a sinusoidal input is
impedance, and a very low output impedance. approximately at
 GATE Previous Years Solved Paper 143

(a) 4.55 (b) 10 (a) 8 (b) 32

(c) 20 (d) 28.6 (c) 50 (d) 200
[EC-1999 : 2 Marks] [EC-2013 : 2 Marks]

Q.9 An npn BJT has gm = 38 mA/V, Cµ = 10–14 F, Q.12 Which one of the following statements is correct
C = 4 × 10–13 F, and DC current gain 0 = 90. For about an ac coupled common-emitter amplifier
this transistor fT and f are: operating in the mid-band region?
(a) fT = 1.64 × 108 Hz and f = 1.47 × 1010 Hz (a) The device parasitic capacitances behave
(b) fT = 1.47 × 1010 Hz and f = 1.64 × 108 Hz like open-circuits, whereas coupling and
(c) fT = 1.33 × 1012 Hz and f = 1.47 × 1010 Hz bypass capacitances behave like short-
(d) fT = 1.47 × 1010 Hz and f = 1.33 × 1012 Hz circuits.

[EC-2001 : 2 Marks] (b) The device parasitic capacitances, coupling

capacitances and bypass capacitances
Q.10 A bipolar transistor is operating in the active behave like open-circuits.
region with a collector current of 1 mA. (c) The device parasitic capacitances, coupling
Assuming that the of the transistor is 100 and capacitances and bypass capacitances
the thermal voltage (V T ) is 25 mV, the behave like short-circuits.
transconductance (gm) and the input resistance
(d) The device parasitic capacitances behave
(r ) of the transistor in the common emitter
like short-circuits, whereas coupling and
configuration, are
bypass capacitances behave like open-
(a) gm = 25 mA/V and r = 15.625 k circuits.
(b) gm = 40 mA/V and r = 4.0 k [EC-2016 : 1 Mark]
(c) gm = 25 mA/V and r = 2.5 k
Q.13 The Miller effect in the context of a common-
(d) gm = 40 mA/V and r = 2.5 k
emitter amplifier explains
[EC-2004 : 2 Marks]
(a) an increase in the low frequency cut-off
Q.11 The ac schematic of an NMOS common-source frequency.
stage is shown in the figure below, where part (b) an increase in the high frequency cut-off
of the biasing circuits has been omitted for frequency.
simplicity. For the n-channel MOSFET ‘M’, the (c) a decrease in the low frequency cut-off
transconductance gm = 1 mA/V, and body effect frequency.
and channel length modulation effect are to be
(d) a decrease in the high frequency cut-off
neglected. The lower cut-off frequency (in Hz)
frequency.
of the circuit is approximately at
[EC-2017 : 1 Mark]

RD = 10 k

C = 1 µF
Vi M
RL = 10 k
144 Electronics Engineering Analog Electronics

Electronics & Electrical Engineering

GATE Previous Years Solved Paper

A n swe rs & Expl a n a t i o n s

Answers
EC Frequency Response Amplifiers

1. (a) 2. (1.59) 3. (10) 4. (a) 5. (d) 6. (d) 7. (a) 8. (b)

9. (b) 10. (d) 11. (a) 12. (a) 13. (d)

Solutions
EC Frequency Response Amplifiers

1. (a) 5. (d)
The low frequency of operation of a multi-stage Miller’s Theorem:
RC coupled amplifier is limited by the coupling Miller’s theorem state that if a series impedance
capacitor. Z is connected between the input and output
terminal of a network, then it can be replaced
2. Sol. with a shunt impedance Z1 in the input side
fL and by a shunt impedance Z2 in the output
%Tilt = × 100%
f section of the network.
f × % Tilt Z
fL =
× 100
I1 I2
50 × 10 + +
= = 1.59 Hz
× 100 Vi Vo
N
3. Sol. – –

1 + A = 1 + 100 × 0.99
= 1 + 99 = 100
+ +
fL 100
fL = = = 1 Hz Vi Z1 Z2 Vo
1+ A 100 N
– –
f H = fH (1 + A )
= 100 × 103 × (100) = 10 MHz
If Vi > V2 then I1 flows:
4. (a)
V1 V2 V1 [1 V2 /V1 ] V1 [1 Av ]
fT = f I1 = = =
Z Z Z
f T = 200 × 1 = 200 MHz V1 Z
f = Z1 =
I1 1 Av
f = = (1 + ) f
1 Z
= (1 + 200) 1 = 201 MHz Z1 =
1 K
 GATE Previous Years Solved Paper 145

6. (d) 38 × 10 3

Unity gain bandwidth product of the C.E. = 13

2 × 10 (0.1 + 4)
transistor,
= 1.47 × 1010 Hz
gm gm
fT = = fT 1.47 × 1010
2 (C + Cµ ) 2 (C e + Cc ) f = =
o 90
7. (a) = 1.64 × 108 Hz ( o = hfe)

1 10. (d)
fT =
2 RC
IC 1 mA
1 IC gm = =
= gm = VT 25 mV
R VT
= 0.04 = 40 mA/V
IC h fe = gm r , hfe =
fT =
2 VT × Cµ
100
r = = 3
= 2.5 k
1 mA gm 40 × 10
Cµ =
2 × 26 mV × 400 × 10 6
11. (a)
= 15 pF
1
8. (b) fL =
2 RC
tr × B.W. = 0.35 1
=
0.35 2 × 3.14 × (10 k + 10 k ) × 1 µF
B.W. = 9
= 10
35 × 10 = 8 Hz

9. (b) 13. (d)

gm Miller effect increases input capacitances and
fT =
2 (Cµ + C ) thereby decreases the higher cut-off frequency.
3
38 × 10
= 14 13
2 × (10 + 4 × 10 )
 6 Feedback Amplifiers

ELECTRO NICS EN GINEERIN G (b) improves the signal to noise ratio at the
output.
(GATE Previous Years Solved Papers)
(c) does not effect the signal to noise ratio at
Q.1 The feedback amplifier shown in figure has the output.

VCC
(d) reduces distortion.
[EC-1993 : 1 Mark]

Q.4 To obtain very high input and output

impedances in a feedback amplifier, the mostly
used is
(a) Voltage-series (b) Current-series
(c) Voltage-shunt (d) Current-shunt
[EC-1995 : 1 Mark]

Q.5 Negative feedback in

1. voltage series configuration
2. current shunt configuration
(a) increase input impedance
(a) current-series feedback with large input
(b) decrease input impedance
impedance and large output impedance.
(c) increase closed loop gain
(b) voltage-series feedback with large input
(d) leads to oscillation
impedance and low output impedance.
[EC-1997 : 2 Marks]
(c) voltage-series feedback with low input
impedance and low output impedance. Q.6 In a shunt-shunt negative feedback amplifier,
(d) current-shunt feedback with low input as compared to the basic amplifier,
impedance and output impedance. (a) both input and output impedance
[EC-1989 : 2 Marks] decreases.
(b) input impedance decreases but output
Q.2 Two non-inverting amplifiers, one having a
impedance increases.
unity gain and the other having a gain of twenty,
are made using identical operational amplifiers. (c) input impedance increases but output
As compared to the unity gain amplifier, the impedance decreases.
amplifier with gain twenty has (d) both input and output impedance increases.
(a) less negative feedback [EC-1998 : 1 Mark]
(b) greater input impedance Q.7 Negative feedback in an amplifier
(c) less bandwidth (a) reduces gain
(d) none of the above [EC-1991 : 2 Marks] (b) increases frequency and phase distortions
Q.3 Negative feedback in amplifiers (c) reduces bandwidth
(a) improves the signal to noise ratio at the (d) increases noise
input. [EC-1999 : 1 Mark]
 GATE Previous Years Solved Paper 147

Q.8 An amplifier has an open-loop gain of 100, an Q.12 The effect of current shunt feedback in an
input impedance of 1 k , and an output amplifier is to
impedance of 100 . A feedback network with (a) increase the input resistance and decrease
a feedback factor of 0.99 is connected to the the output resistance.
amplifier in a voltage series feedback mode. The (b) increase both input and output resistances.
new input and output impedances, (c) decrease both input and output resistances.
respectively, are
(d) decrease the input resistance and increase
(a) 10 and 1 (b) 10 and 10 the output resistance.
(c) 100 k and 1 (d) 100 k and 1 k [EC-2005 : 1 Mark]
[EC-1999 : 2 Marks]
Q.13 The input impedance (Z i ) and the output
Q.9 In a negative feedback amplifier using voltage impedance (Zo) of an ideal transconductance
series (i.e. voltage-sampling, series mixing) (voltage controlled current source) amplifier are
feedback (a) Zi = 0, Zo = 0 (b) Zi = 0, Zo =
(a) Ri decreases and Ro decreases (c) Zi = , Zo = 0 (d) Zi = , Zo =
(b) Ri decreases and Ro increases [EC-2006 : 1 Mark]
(c) Ri increases and Ro decreases
Q.14 In a transconductance amplifier, it is desirable
(d) Ri increases and Ro increases
to have
(Ri and Ro denote the input and output resistance
(a) a large input resistance and a large output
respectively.
resistance.
[EC-2002 : 1 Mark]
(b) a large input resistance and a small output
Q.10 An amplifier without feedback has a voltage resistance.
gain of 50, input resistance of 1 k and output (c) a small input resistance and a large output
resistance of 2.5 k . The input resistance of the resistance.
current-shunt negative feedback amplifier using (d) a small input resistance and a small output
the above amplifier with a feedback factor of resistance.
0.2 is
[EC-2007 : 1 Mark]
1 1
(a) k (b) k Q.15 In a voltage-voltage feedback as shown below,
11 5
which one of the following statements is true if
(c) 5 k (d) 11 k
the gain k is increased?
[EC-2003 : 2 Marks]
+ + +
Q.11 Voltage series feedback (also called series-shunt Vin V1 Ao Vout
– –
feedback) results in –

(a) increase in both input and output

impedances.
(b) decrease in both input and output
impedances. + +
Vf = kVout k
(c) increase in input impedance and decrease – –

in output impedances.
(a) The input impedance increases and output
(d) decrease in input impedance and increase
impedance decreases.
in output impedances.
(b) The input impedance increases and output
[EC-2004 : 1 Mark]
impedance also increases.
 148 Electronics Engineering Analog Electronics

(c) The input impedance decreases and output Q.18 The feedback topology in the amplifier circuit
impedance also decreases. (the base bias circuit is not shown for simplicity)
(d) The input impedance decreases and output in the figure is
impedance increases. VCC
[EC-2013 : 1 Mark]
RC Io
Q.16 In the ac equivalent circuit shown in the figure,
if iin is the input current and RF is very large, the Vo
type of feedback is

RS

RE
RD Vs
RD
Vout

(a) voltage shunt feedback

M2
(b) current series feedback
M1 (c) current shunt feedback
RF (d) voltage series feedback
[EC-2014 : 1 Mark]
small signal iin
input Q.19 A good transconductance amplifier should
have
(a) high input resistance and low output
(a) voltage-voltage feedback
resistance.
(b) voltage-current feedback (b) low input resistance and high output
(c) current-voltage feedback resistance.
(d) current-current feedback (c) high input and output resistances.
[EC-2014 : 1 Mark] (d) low input and output resistances.
Q.17 The desirable characteristics of a [EC-2017 : 1 Mark]
transconductance amplifier are
Q.20 A good trans-impedance amplifier has
(a) high input resistance and high output
(a) low input impedance and high output
resistance. impedance.
(b) high input resistance and low output (b) high input impedance and high output
resistance.
impedance.
(c) low input resistance and high output
(c) high input impedance and low output
resistance. impedance.
(d) low input resistance and low output
(d) low input impedance and low output
resistance.
impedance.
[EC-2014 : 1 Mark] [EC-2018 : 1 Mark]
 GATE Previous Years Solved Paper 149

Electronics & Electrical Engineering

GATE Previous Years Solved Paper

A n swe rs & Expl a n a t i o n s

Answers
EC Feedback Amplifiers

1. (c) 2. (a, c) 3. (b, c) 4. (b) 5. (1-a, 2-b) 6. (a) 7. (a) 8. (c)

9. (c) 10. (a) 11. (c) 12. (d) 13. (d) 14. (a) 15. (a) 16. (b)

17. (a) 18. (b) 19. (c) 20. (d) 21. (800)

Solutions
EC Feedback Amplifiers

1. (c) 5. Sol.
Emitter is output node, it is voltage sampler 1-a, 2-b
voltage shunt feedback. Voltage-series configuration increases the input
impedance,
2. (a, c)
R if = Ri(1 + A ) = Ri(1 + Av )
For identical operational amplifiers, gain- Current-shunt configuration decreases the input
bandwidth product is constant, impedance,
G.B.W. = Constant
Ri Rf
A1 × BW1 = A2 × BW2 R if = =
1+ A 1 + AI
A1 × BW1
BW2 =
A2 6. (a)
1 × BW1 BW2 Shunt-shunt feedback amplifiers has very low
= =
20 20 input and very low output impedance,
So, as compare to the unity gain amplifier with
Ri Ri
gain twenty has less bandwidth. R if = =
1+ A 1 + Rm
3. (b, d) Ro Ro
Rof = =
Negative feedback in amplifiers 1+ A 1 + Rm
(b) improves the signal to noise ratio at the
output. 7. (a)
(d) reduces distortion. A
Af =
1+ A
4. (b)
Current-series feedback amplifiers has very 8. (c)
high input and very high output impedances, A = 100, = 0.99, 1 + A = 100
R if = Ri (1 + A ) = Ri (1 + Gm ) For voltage series, Ri and Ro by 1 + A
Rof = Ro(1 + A ) = Ro (1 + Gm )
150 Electronics Engineering Analog Electronics

We have, R if = Ri (1 + A ) and, the output impedance decreases,

Ro Ro
and Ro = Rof =
1+ A 1 + Ao K
R if = 100 × 1 k = 100 k
16. (b)
100
Rof = =1 Sampling Current
100
Mixing Voltage
9. (c)
18. (b)
Ri increase by factor of 1 + A and Ro decreases
by 1 + A . The feedback topology in the amplifier circuit is
current series because,
10. (a) Sampling Current
In current shunt negative feedback amplifier, Mixing Series
Ri So, current series feedback.
R if =
1+ A
19. (c)
3 3
1 × 10 10 A good transconductance amplifier should
= =
1 + 50 × 0.2 1 + 10 have very high input resistance and very high
1 output resistance.
R if = k
11
20. (d)
15. (a) A good trans-impedance amplifier should have
The given configuration is a voltage-series low input impedance and low output
feedback configuration. impedance.
So, the input impedance increases,
R if = Ri (1 + AoK)
 7 Oscillator Circuits

ELECTRO NICS EN GINEERIN G (a) Precision integrator

(b) Hartley oscillator
(GATE Previous Years Solved Papers)
(c) Butteworth high pass filter
SECTIO N - A (d) Wien-bridge oscillator

Q.1 Match the following: [EC-2000 : 1 Mark]

List-I List-II Q.4 The oscillator circuit shown in the figure is
A. Hartley 1. Low frequency oscillator –VCC
B. Wein-bridge 2. High frequency oscillator
LC
C. Crystal 3. Stable frequency oscillator
4. Relaxation oscillator
5. Negative resistance oscillator L = 10 µH
CC R1
[EC-1994 : 2 Marks] Vo

Q.2 Value of R in the oscillator shown in the given

figure. So chosen that it just oscillates at an C1 = 2 pF C2 = 2 pF
angular frequencies of ‘ ’. The value of ‘ ’ and R2
Re Ce
the required value of R will respectively be
100 k

5k
– (a) Hartley oscillator with foscillation = 79.6 MHz
Vo
+ (b) Colpitts oscillator with foscillation = 50.3 MHz
R (c) Hartley oscillator with foscillation = 159.2 MHz
(d) Colpitts oscillator with foscillation = 159.2 MHz
[EC-2000 : 2 Marks]
0.01 µF 10 mH 1k

Q.5 The circuit in the figure employs positive

feedback and is intended to generate sinusoidal
(a) 105 rad/sec, 2 × 104 oscillation.
(b) 2 × 104 rad/sec, 2 × 104
Vf ( f ) 1
(c) 2 × 104 rad/sec, 105 If at a frequency fo, B( f ) = = 0° then
Vo ( f ) 6
(d) 105 rad/sec, 105 [EC-1996 : 2 Marks]

Q.3 The configuration of the figure is a to sustain oscillation at this frequency.

R1 R2
R1 R2
–
–
Vo + +
+
R
Vo(f )
C + Network
Vf (f ) (f )
–
R C –
 152 Electronics Engineering Analog Electronics

(a) R2 = 5R1 (b) R2 = 6R1 Q.8 The circuit shown in the figure has an ideal
R R op-amp. The oscillation frequency and the
(c) R2 = 1 (d) R2 = 1 condition to sustain the oscillations,
6 5
respectively are
[EC-2002 : 2 Marks]
R1
Q.6 The oscillator circuit shown in the figure has
an ideal inverting amplifier. Its frequency of R2
oscillation (in Hz) is –
Vo
+

C 2R
2C R

C C C

R R R 1
(a) and R1 = R2
CR
1
1 1 (b) and R1 = 4R2
(a) (b) CR
(2 6 RC ) (2 RC )
1
(c) and R1 = R2
1 1 2CR
(c) (d)
( 6 RC ) ( 6 (2 RC )
1
[EC-2003 : 2 Marks] (d) and R1 = 4R2
2CR
Q.7 The value of C required for sinusoidal [EC-2015 : 2 Marks]
oscillations of frequency 1 kHz in the circuit of
Q.9 Consider the oscillator circuit shown in the
the figure is
figure. The function of the network (shown in
1k 2.1 k dotted lines) consisting of the 100 k resistor in
series with the two diodes connected back-to-
back is to
–
Vout 1 nF 158 k
+
C

1k 1 nF 158 k
+VCC
–

1k C +
–VCC
22.1 k

1 100 k
(a) µF (b) 2 µF D1
2
1 10 k D2
(c) µF (d) 2 6 µF
2 6
[EC-2004 : 2 Marks]
 GATE Previous Years Solved Paper 153

(a) introduce amplitude stabilization by

+10 V
preventing the op-amp from saturating and Vi –
Vo
thus producing sinusoidal oscillations of +
fixed amplitude. –10 V

(b) introduce amplitude stabilization by

2k
forcing the op-amp to swing between
positive and negative saturation and thus
0.5 k
producing square wave oscillations of fixed
2k
amplitude.
(c) introduce frequency stabilization by forcing
the circuit to oscillate at a single frequency.
Vo
(d) enable the loop gain to take on a value that
+10 V
produces square wave oscillations.
[EC-2016 : 1 Mark] (a) –8 V –5 V
Vi

SECTIO N -B

Q.1 Consider the following two statements: –10 V

Statement-1 : Astable multivibrator can be used
Vo
for generating square wave.
Statement-1 : Bistable multivibrator can be used +10 V
for storing binary information.
–5 V +8 V
(a) Only statement 1 is correct. (b) Vi

(b) Only statement 2 is correct.

(c) Both the statements 1 and 2 are correct.
–10 V
(d) Both the statements 1 and 2 are incorrect.
[EC-2001 : 1 Mark] Vo
+5 V
Q.2 An ideal sawtooth voltage waveform of
frequency 500 Hz and amplitude 3 V is
–5 V +5 V
generated by charging a capacitor of 2 µF in (c) Vi

every cycle. The charging requires

(a) constant voltage source of 3 V for 1 ms.
(b) constant voltage source of 3 V for 2 ms. –10 V

(c) constant current source of 3 mA for 1 ms. Vo

+10 V
(d) constant current source of 3 mA for 2 ms.
[EC-2003 : 2 Marks]
(d) –5 V +5 V
Q.3 Given the ideal operational amplifier circuit Vi
shown in the figure indicate the correct transfer
characteristics assuming ideal diodes with zero
cut-in voltage. –5 V

[EC-2005 : 2 Marks]
 154 Electronics Engineering Analog Electronics

Q.4 Consider the Schmidt trigger circuit shown Q.6 In the following astable multivibrating circuit,
below: which properties of vo(t) depend on R2?

+15 V R1
10 k

– –
Vi vo(t)
Vo +
+ R3
C

10 k R2 R4
10 k
–15 V

A triangular wave which goes from –12 V to (a) Only the frequency
12 V is applied to the inverting input of the
(b) Only the amplitude
op-amp. Assume that the output of the op-amp
(c) Both the amplitude and the frequency
swings from +15 V to –15 V. The voltage at the
(d) Neither the amplitude nor the frequency
non-inverting input switches between
[EC-2009 : 2 Marks]
(a) –12 V and +12 V (b) –7.5 and +7.5 V
(c) –5 V and +5 V (d) 0 and 5 V Q.7 In the astable multivibrator circuit shown in the
[EC-2008 : 2 Marks] figure, the frequency of oscillation (in kHz) at
the output pin 3 is _______ .
Q.5 An stable multivibrator circuit using IC 555
timer is shown below. Assume that the circuit
is oscillating steadily. VCC

9k 8 4
RA = 2.2 k VCC Res
3k 7
4 8 Disch
(Reset) (Supply)
6 (Threshold) RB = 4.7 k 555 Timer
6 3
10 k (Output) 3 Thresh Out

2 (Trigger) (Gnd)
(Discharge) 1 2
7 Trig

12 k C = 0.022 µF Gnd
1
VC 0.01 µF

[EC-2016 : 1 Mark]
The voltage VC across the capacitor varies
between
(a) 3 V to 5 V (b) 3 V to 6 V
(c) 3.6 V to 6 V (d) 3.6 V to 5 V
[EC-2008 : 2 Marks]
 GATE Previous Years Solved Paper 155

ELECTRICAL EN GINEERIN G List-I

(GATE Previous Years Solved Papers) A. Capacitor C1 is open

B. Capacitor C3 is open
SECTIO N - A C. Capacitor C3 is open
Q.1 In a common emitter amplifier, the unbypassed D. RC2 is shorted
emitter resistance provides List-II
(a) voltage-shunt feedback P. All dc voltages normal, V o increase
(b) current-series feedback marginally.
(c) negative-voltage feedback Q. Collector of TR2 at VCC , Vo = 0
(d) positive-current feedback R. All dc voltages normal, gain of 2nd stage
[EE-1992 : 1 Mark] decrease, Vo decrease
S. All dc voltage normal, Vo = 0
Q.2 A Wein bridge oscillator is shown in figure.
T. All dc voltage normal, overall gain of the
Which of the following statements are true, if ‘f ’
amplifier increases, Vo increase
is the frequency of oscillation?
U. No change
R2 [EE-1994 : 1 Mark]
R
R1 Q.4 A practical RC sinusoidal oscillator is built
C –
using a positive feedback amplifier with a
+ Vo
closed-loop gain slightly less than unity.
(True/False)
R C
[EE-1994 : 1 Mark]

Q.5 An op-amp has an open-loop gain of 105 and

1 an open-loop upper cut-off frequency of 10 Hz.
(a) For R = 1 k , C = µF, f = 1 kHz
2 If this op-amp is connected as an amplifier with
1 a closed-loop gain of 100, then the new upper
(b) For R = 3 k , C = µF, f = 3 kHz
18 cut-off frequency is
(c) The gain of the op-amp stage should be less
(a) 10 Hz (b) 100 Hz
than two for proper operation.
(c) 10 kHz (d) 100 kHz
(d) The gain of op-amp should be three for
proper operation. [EE-2001 : 1 Mark]
[EE-1993 : 1 Mark] Q.6 For the oscillator circuit shown in figure, the
Q.3 Given figure shows a two stage small signal expression for the time period of oscillation can
transistor feedback amplifier. Match the be given by (where = RC).
defective component (listed on the left hand side R
below) with its probable effect on the circuit
(listed on the right hand side). C
VC –
Rc1 Rc2 Vo
R1 R1
+
C5 R
Rs C1 C2
TR1 TR2 Vo

Vs R2 R2 R
Re1 Re2 C3 C4

RF
 156 Electronics Engineering Analog Electronics

(a) ln 3 (b) 2 ln 3 Q.9 The typical frequency response of a two-stage

(c) ln 2 (d) 2 ln 2 direct coupled voltage amplifier is as shown in
[EE-2001 : 2 Marks]

Q.7 The output voltage (Vo) of the schmitt trigger |Gain|

(a)
shown in figure swings between +15 V and
–15 V. Assume that the operational amplifier is Frequency
ideal. The output will change from +15 V to
–15 V when the instantaneous value of the
input since wave is, |Gain|
(b)
100 k
– Frequency
Vi = 10 sin t Vo
+
10 k
|Gain|
(c)
3k
Frequency
2V

(a) 5 V in the positive slope only.

|Gain|
(b) 5 V in the negative slope only. (d)
(c) 5 V in the positive and negative slopes.
Frequency
(d) 3 V in the positive and negative slopes.
[EE-2005 : 2 Marks]
[EE-2002 : 2 Marks]
Q.10 In the feedback network shown below, if the
Q.8 The feedback used in the circuit shown in figure
feedback factor ‘k’ is increased, then
can be classified as,
+ + +
VCC
Vin V1 A0 Vout
– – –
RC =
RF

C C

+ +
Vf = kVout k
RL
– –
RS RB
RE C
(a) the input impedance increases and output
impedance decreases.
(b) the input impedance increases and output
impedance also decreases.
(a) shunt-series feedback
(c) the input impedance decreases and output
(b) shunt-shunt feedback
impedance decreases.
(c) series-shunt feedback
(d) the input impedance decreases and output
(d) series-series feedback
impedance increases.
[EE-2004 : 1 Mark]
[EE-2013 : 1 Mark]
 GATE Previous Years Solved Paper 157

Q.11 In the Wein bridge oscillator circuit shown in Q.13 A hysteresis type TTL inverter is used to realize
figure, the bridge is balanced when an oscillator in the circuit shown in the figure.
10 k
C1
+5 V
R1
+VCC vo
+
0.1 µF
–
–VCC R3

If the lower and upper trigger level voltages are

C1 R2 R4 0.9 V and 1.7 V, the period (in ms), for which
output is LOW, is _______ .
[EE-2014 : 2 Marks]

R3 R1 1 Q.14 A Current Controlled Current Source (CCCS)

(a) = , =
R4 R2 R1C1 R2C 2 has an input impedance of 10 and output
impedance of 100 k . When this CCCS is used
R2 C 2 1
(b) = , = in a negative feedback closed-loop with a loop
R1 C1 R1C1 R2C 2
gain of 9, the closed-loop output impedance is
R3 R1 C 2 1 (a) 10 (b) 100 k
(c) = + , =
R4 R2 C1 R1C1 R2C 2
(c) 1000 k (d) 100
R3 R1 C 2 1 [EE-2019 : 1 Mark]
(d) + = , =
R4 R2 C1 R1C1 R2C2
[EE-2014 : 1 Mark] SECTIO N -B

Q.12 An oscillator circuit using ideal op-amp and Q.1 The circuit of figure shows a 555 Timer IC
diodes is shown in the figure. connected as an astable multivibrator. The
value of the capacitor C is 10 nF. The values of
R
the resistors RA and RB for a frequency of 10 kHz
and a duty cycle of 0.75 for the output voltage
+5 V waveform are
–
Vo VCC
C +
–5 V RA
Th
3k
RB 555
Tr
R1 Timer
1k Vout
C IC
1k

The time duration for +ve part of the cycle is t1

(a) RA = 3.62 k , RB = 3.62 k
t1 t2
(b) RA = 3.62 k , RB = 7.25 k
and for –ve parts at t2. The value of e RC
(c) RA = 7.25 k , RB = 3.62 k
will be _______ . (d) RA = 7.25 k , RB = 7.25 k
[EE-2014 : 2 Marks] [EE-2003 : 2 Marks]
 158 Electronics Engineering Analog Electronics

Q.2 In the Schmitt trigger circuit shown in figure, if Q.4 IC 555 in the figure is configured as an astable
VCE(sat) = 0.1 V, the output logic low level (VOL), multivibrator. It is enabled to oscillate at t = 0 by
is applying a high input to pin 4. The pin
description is 1 and 8-supply, 2-trigger, 4-resel,
+5 V
6-threshold, 7-discharge. The waveform
appearing across the capacitor starting from
t = 0, as observed on a storage CRO is
200
+
Vo

Vi = 0 10 K
8
7

10 K IC 555 3

2, 6
1k I = 1.25 mA

4 1

(a) 1.25 V (b) 1.35 V

(c) 2.50 V (d) 5.00 V
(a) (b)
[EE-2004 : 2 Marks]

Q.3 The input signal Vin shown in the figure is a

1 kHz square wave voltage that alternates
between +7 V and –7 V with a 50% duty cycle.
Both transistors have the same current gain, (c) (d)
which is large. The circuit delivers power to the
load resistor RL. What is the efficiency of this
circuit for the given cicuit? Choose the closest [EE-2007 : 2 Marks]
answer.
Q.5 The following circuit has a source voltage Vs as
+10 V
shown in the graph. The current through the
circuit is also shown.
a b

+
Vs R 10 k
Vin –

RL = 10 15
10
5
V s (volts)

–10 V 0
–5
(a) 46% (b) 55%
–10
(c) 63% (d) 92% –15
[EE-2007 : 2 Marks] 0 100 200 300 400
Time (ms)
 GATE Previous Years Solved Paper 159

15 vo

1
Current (mA)

T1 T1 T1 T1
0.5 (b)
0 t
–0.5
–1 vo
–1.5
0 100 200 300 400
Time (ms) T2 T1 T2 T1 T2
(c)
t
The element connected between a and b could be
(a) a b
vo
(b)
(c) a T2 T1 T2 T1 T2 T2
b (d)
t

[EE-2014 : 2 Marks]
(d)
Q.7 The cross-section of a metal-oxide
[EE-2009 : 1 Mark] semiconductor structure is shown
schematically. Starting from an uncharged
Q.6 Two monoshot multivibrators, one positive edge condition, a bias of +3 V is applied to the gate
triggered (M 1) and another negative edge contact with respect to the body contact. The
triggered (M2), are connected as shown in figure. charge inside the silicon dioxide layer is then
measured to be +Q. The total charge contained
+5 V
within the dashed box shown, upon application
M1 M2 of bias, expressed as multiple of Q (absolute
10 k
Q1 Q2 vo value in Coulombs, rounded off to the nearest
integer), is ______ .
10 µF Q1 Q2
GATE
Silicon Dioxide

The monoshots M1 and M2 when triggered Si

produce pulses of width T1 and T2 respectively,
BODY
where T1 > T2. The steady-state output voltage
Vo of the circuit is DASHED BOX

vo [EE-2020 : 1 Mark]

T1 T2 T1 T2 T1
(a)
t
160 Electronics Engineering Analog Electronics

Electronics & Electrical Engineering

GATE Previous Years Solved Paper

A n swe rs & Expl a n a t i o n s

Answers
EC Oscillator Circuits (Section-A)

2. (a) 3. (d) 4. (b) 5. (a) 6. (a) 7. (a) 8. (d) 9. (a)

Solutions
EC Oscillator Circuits (Section-A)

2. (a) 1 1 1/ R 1/ R
= = = =
1 A 21 1 1 R +1k
+
= R k R×1 k
LC
1 R+1k = 21 × 1 k
= R = 20 k
10 × 10 3 × 0.01 × 10 6
= 2 × 104
= 105 rad/sec
R Vf 4. (b)
+ Figure shown is Colpitts oscillator,

Vo 1k 10 mH 0.01 µF
1
Vf f=
2 LC eq
–
C1C 2 2×2
Ceq = = = 1 pF
Apply nodal analysis, C1 + C 2 4
Vf Vo Vf Vf
+ + + V f Cs = 0 1
R 1k Ls =
2 10 × 10 6 × 10 12
1 1 1 Vo 1 × 10 9
Vf + + Vf j C = = 50.3 MHz
R 1k L R =
2 10
1
For oscillation C =0 5. (a)
L
R2
1 1 Vo
Vf + =
R 1k R R1
–
Vf 1/R 1 Vo
= = +
Vo 1 1 Vo
+
R 1k
Rf 100 k
A = 1+ = 1+ = 21
R1 5k
 GATE Previous Years Solved Paper 161

KCL at node-1, V0 j C 1 2 jR
= + + R2 +1
Vo 0 V Vo V1 R 2 2
C C
+ o =0
R1 R2 For oscillation imaginary part is zero.
1 1 1 C 1 C
+ = i.e., j × 2 2+ × R2 = 0
R1 R2 R2 R C R
R1 + R2 1
=1 + CR = 0
R1 CR
2C2R2 – 1 = 0
R2
R1 1 +
R1 1 2 1
= =6 = 2 2
R1 R C

R2 1 1
C= =
=5 R 2 × 10 3 × 10 3
R1
R 2 = 5R 1 1
= µF
2
6. (a)
Frequency of oscillation for RC phase shift 8. (d)
Frequency of Wein bridge oscillation is
1
oscillator is .
2 6RC 1
o = , but in the question time constant is
RC
7. (a) doubled so, frequency becomes half,
2.1 k 1
o =
2RC
1k 1
– Z1 = 2 R + = 2 (R jR )
+
Vout j C
C
1
1k R×
2j C R2 / j
Z2 = =
V1 1 R jR
R+
2j C
1k C
Z2 1
= =
Z1 + Z2 5
R = 1k
R1
V0 V1 V V 1+ =5 R1 = 4R2
= 1 + 1 R2
XC + R XC R
V0 V1 9. (a)
XC + R
= V1 The given circuit is Wein-bridge oscillator
XC + R XC R
which produced sinusoidal oscillations and the
V0 ( XC + R)2 XC =
j
amplitude of output wave is decided by
= +1
V1 XC R C
feedback through inverting input terminal of
1 2 jR op-amp.
+ R2
V0 2 2
C C
= +1
V1 R
j C
162 Electronics Engineering Analog Electronics

Answers
EC Oscillator Circuits (Section-B)

1. (c) 2. (d) 3. (b) 4. (c) 5. (a) 6. (a) 7. (5.681)

Solutions
EC Oscillator Circuits (Section-B)

2. (d) Vo

1 1 10 V
T= = = 2 ms
f 500 Hz
CdV 6 3
I= = 2 × 10 × 3
Vi
dt 2 × 10 –5 V

= 3 × 10–3
I = 3 mA –10 V

3. (b)
4. (c)
The given circuit is of a Schmitt trigger. The
upper and lower transition voltages can be Let the voltage at the non-inverting input be V1.
obtained as, Applying KCL at non-inverting input end,
Vut = uVsat 15 V1 V0 V1 V1 ( 15)
+ =
When lower diode is ON, 10 10 10
15 – V1 + V0 – V1 = V1 + 15
2k
u = Vo
2.5 k V1 =
3
2 Since, Vo swings from –15 V to +15 V.
Vut = × 10 = 8 V
2.5 Therefore, V1 switches between –5 V and +5 V.
Vlt = – lVsat
5. (a)
when upper diode is ON,
VC varies between 3 V to 5 V.
2k 1
l = = 7. Sol.
4k 2
1
1 f =
= × 10 = 5 V 0.69( RA + 2 RB ) C
2
1
Vut and Vlt are upper and lower transition =
0.69 (2.2 × 10 3 + 2 × 4.7 × 10 3 ) × 0.022 × 10 6
voltage. The transfer characteristics of the circuit
= 5.6818 kHz
is given as below.
 GATE Previous Years Solved Paper 163

Answers
EE Oscillator Circuits (Section-A)

1. (b) 2. (a, b, d) 4. (False) 5. (c) 6. (b) 7. (a) 8. (b) 9. (b)

10. (a) 11. (c) 12. (0.8) 13. (0.63) 14. (c)

Solutions
EE Oscillator Circuits (Section-A)

3. Sol. 10. (a)

A S, B R, C T, D Q The given configuration is a voltage-series
feedback configuration.
4. Sol.
So, the input impedance increases,
False R if = Ri (1 + Aok)
5. (c) and the output impedance decreases,

AOL = 10 5 Ro
Rof =
f = 10 Hz 1 + Ao k
AOL
ACL = 11. (c)
1 + AOL
R3 R C
10 5 = 1+ 2
(1 + AOL) = = 10 3 R4 R2 C1
10 2
1
f 2 = f2(1 + AOL) =
R1 R2C1C 2
= 10 × 103 Hz
= 10 kHz 12. Sol.

6. (b) R

T = 2RC ln 3 = 2 ln 3
–
8. (b) Vo
C +
Equivalent circuit can be drawn with input
voltage comparison and current feedback. It is 3k D1

shunt-shunt feedback.

9. (b)
1k D2
1k
|Gain|

This circuit is astable multivibrator (or) free

For RC coupled amplifier
running oscillator.
When, V0 = Vsat
|Gain| Vsat
1k
VUTP = Vsat × =
1k +3k 4
For direct coupled amplifier
164 Electronics Engineering Analog Electronics

When, V0 = –Vsat From equation (i) and (ii),

Vsat ×
1k Vsat e t1 / RC
VLTP =
1k +1k
= = e( t1 t2 )/ RC
2 e t2 / RC
Vc = Vfinal + (Vinitial – Vfinal) e–t/RC 2 4
= = = 0.8
+V sat 5 /2 5
Charging
VUTP 13. Sol.
Discharging

V0
+5
1.7
VLTP
t1 t2 –V sat

–0.9 V
In time t = t1,
t
Vc = VUTP, Vinitial = VLTP, Vfinal = +Vsat 0V Vc(t)

VUTP = Vsat + (VLTP Vsat ) e t1 / RC

Discharging curve,
Vc(t) = 0 – (0 – 1.7) e–t/RC
Vsat Vsat t1 / RC
= Vsat + Vsat e At t = T2,
4 2
Vc(t) = 0.9 V
1 1 t1 / RC 0.9 = 1.7 e–t/RC
Vsat 1+ = Vsat +1 e
4 2 0.63 = T2
1 1 T2 = 0.63 ms
1 = + 1 e t1 / RC
4 2
14. (c)
3 3 t / RC
= e 1 “CCCS” [Current Controlled Current Source]
4 2
amplifier.
t1 / RC =2 ...(i)
e Given, Z 0 = 100 k
In time, t = t2 Loop gain, A =9
Vc = VLTP, Vinitial = VUTP, Vfinal = –Vsat Z0F = Z0[1 + A ]
t2 / RC [High impedance CS]
VLTP = Vsat + (VUTP + Vsat ) e
= 100 k [1 + 9]
Vsat V t2 / RC = 100 k × 10
= Vsat + sat + Vsat e
2 4 = 1000 k
1 1
1 Vsat = Vsat 1 + e t2 / RC
2 4
1 5 t2 / RC
= e
2 4
5
t2 / RC = ...(ii)
e 2
 GATE Previous Years Solved Paper 165

Answers
EE Oscillator Circuits (Section-B)

1. (c) 2. (b) 3. (d) 4. (a) 5. (a) 6. (c) 7. (0)

Solutions
EE Oscillator Circuits (Section-B)

1. (c) But in this case initial voltage at capacitor is

zero so it starts from zero also charging time
T
Duty cycle = = ON will be larger (normally) than discharging time
T
but it is made equal by using a diode.
TON = T
= 0.75 × 10–4 = 75 µ-sec 5. (a)
Diode acts as a switch. When forward biased it
75 × 10 6
= RA + RB is short-circuited. But when suddenly reverse
0.7 × 10 8
biased, current does not becomes zero instantly,
RA + RB = 10.714 k
initially the same current flow in opposite
TOFF = 0.7 CRB
direction and after some time (turn off time) it
25 × 10 6 will become zero.
RB =
0.7 × 10 8
7. Sol.
R B = 3.57 k , RA = 7.14 k

2. (b)
Vi = 0, then first transistor will be cut-off and GATE + q
current through left resistor will drive the second
SiO2 + q
transistor into saturation. 3V
Then, Vo = VCE,sat + 1.25 + 10–3 × 103 Si – q

= 1.35 V Body – q

3. (d)
It is class-D amplifier, so should be high of
Overall charge in side the box q + q – q – q = 0
class-D amplifier is 90% to 100%.
charge.
4. (a)
An astable multi-vibrator is providing pulses
as given below.