Hardware Description

Language - Verilog
Sequential Circuits
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Outline
 Review
 Module Instantiation
 Ports Connection
 Number Representation
 Assignments
 Operators
 Sequential Circuit
 Introduction
 Counter
 Sequential Verilog Syntax
 Procedural Assignment
 Non-blocking
 Example
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REVIEW

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Module Instantiation

Adder

instance
example

A d d e r _0 A d d e r _1

A d d e r_ tre e
instance name IO interface

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Ports Declaration
 Two port types  Two net types
 Input port  wire
 input a;  wire c;
 Output port  reg
 output b;  reg d;

a ab
b
b bc
co
c
c ac
a
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Ports Connection

in1
adder out
in2

• Connect module ports by name (Recommended!!!!!)

– Usage: .PortName (NetName)
– adder adder_1 ( .out(C) , .in1(A) , .in2(B) );
• Connect module ports by order list
– adder adder_0 ( C , A , B ); // C = A + B
• Not fully connected
– adder adder_2 ( .out(C) , .in1(A) , .in2() );

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Number Representation
 Format: <size>’<base_format><number>
 <size> - decimal specification of number of bits
 <base format> - ' followed by arithmetic base of number
 <number> - value given in base of <base_format>
 Examples:
 6’b010_111 gives 010111
 8’b0110 gives 00000110
 4’bx01 gives xx01
 16’H3AB gives 0000_0011_1010_1011
 24 gives 0…0011000
 5’O36 gives 11_100
 16’Hx gives xxxxxxxxxxxxxxxx
 8’hz gives zzzzzzzz
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Values Assignment
 Assignment: Drive value onto nets and registers
 There are two basic forms of assignment
 continuous assignment, which assigns values to wire type
 procedural assignment, which assigns values to reg type
 Basic form
Assignments Left Hand Side Example
Continuous wire a;
wire
Assignment assign a = 1’b1;
Procedural reg a;
reg
Assignment always@(*) a = 1’b1;

P.S. Left hand side (LHS) = Right hand side (RHS)

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Operators
Operator Sign Example

Concatenation and replications {,} {{8{byte[7]},byte}, {a[1:0],b[0]}

Negation !,~ !2’01 //0 , ~2’b01 // 10

Bitwise ~,&,|,^ 2’b01 | 2’b11 // 2’b11

Arithmetic +,-,*,/,% 3%2 //1

Shift >> , << 3’b011 >> 2 // 3’b000

Relational < , <= , > , >=

Equality == , !=

Conditional ?: assign out = sel ? 1’b1 : 1’b0

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SEQUENTIAL CIRCUIT

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Introduction
 Combinational Circuits (without memory)
A
B F(A,B,C)
F(A,B,C)
C

 Sequential Circuit (with memory)

A
B F F(t+1) = F(A,B,C, D(t))
C

D(t) D(t+1)
MEM

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Edge-triggered D Flip-Flop
Positive (Rising edge) trigger
Negative (Falling edge) trigger
to align with clock edges
DQ Q+ Q+ = D
0 0 0
0 1 0
1 0 1
1 1 1

Figure 11-18 Timing for D Flip-Flop (Falling-Edge Trigger)

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4-bit D Flip-Flop Registers

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Binary Counters using D F/F (1/2)

Present State Next State Flip-Flop Inputs
C B A C+ B+ A+ DC DB DA
0 0 0 0 0 1 0 0 1
0 0 1 0 1 0 0 1 0
0 1 0 0 1 1 0 1 1
0 1 1 1 0 0 1 0 0
1 0 0 1 0 1 1 0 1
1 0 1 1 1 0 1 1 0
1 1 0 1 1 1 1 1 1
1 1 1 0 0 0 0 0 0

State Table As Function of (A,B,C)!

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Binary Counters using D F/F (2/2)

 K-map

DC = AB ⊕C DB= A⊕B DA= A’

 Circuit Implement

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SEQUENTIAL
VERILOG SYNTAX

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Procedural Assignment
 Procedure blocks
 always block
 Only reg type can be LHS in procedure blocks
 It’s syntax. Not relevant to whether it’s a flip-flop or a metal wire!
 RHS is not restricted.
 Variable is updated by procedural assignment
 For combinational circuit
 Pure logic circuit
 Use blocking assignment (=)
 Use always @ (*)
 For sequential circuit
 D-FF circuit
 Use non-blocking assignment (<=)
 Edge trigger of clock or reset signal

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Blocking or Non-Blocking?
 Blocking assignment (=) Combinational!!!!
 Evaluation and assignment are immediate

 Nonblocking assignment (<=) Sequential!!!!!

 All assignment deferred until all right-hand sides have been
evaluated (end of the virtual timestamp)

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3-bits Counter – Gate Level

DFF DFF DFF

XOR XOR XOR

AND

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4-bits Counter – RTL Level

clk reset
state

0
nxt_cnt cnt
MUX DFF
4 4

4 + 1

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Header/Comment

Module instantiation
Input/output declaration

Combinational
Parameter
Continuous
Sensitivity list Assignment
Number Representation
Reg/WIre
Operator
FSM Procedure Block
Procedure Assignment
If statement

Sequential
case statement

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Thanks! Feel free to ask

me any questions!

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