جامعة نينوى
كلية هندسة اإللكترونيات
HDL Programming
-VHDL- 3
Textbook: Volnei A. Pedroni, “Circuit Design with
VHDL”, MIT Press London, England, 2004.
Submitted By: Hussein M. H. Aideen
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VHDL> State Machines
Finite state machines (FSM) constitute a special
modeling technique for sequential logic circuits.
helpful in the design of certain types of systems,
(digital controllers, for example).
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VHDL> State Machines
Types of Machine modeling:
Mealy machine: the output of
the machine depends not only
on the present state but also on
the current input.
Moore machine: the output
depends only on the current
state.
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VHDL> State Machines
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VHDL> State Machines
FSM type definition:
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VHDL> State Machines
FSM Design Styles:
Design Style #1:
The design of the lower section is completely
separated from that of the upper section.
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VHDL> State Machines
Design of the Lower (Sequential) Section:
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VHDL> State Machines
Design of the Upper (Combinational) Section:
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VHDL> State Machines
Design Style #2 (Stored Output):
In Design style #1: Notice that in this case, if it is a Mealy
machine (one whose output is dependent on the current
input), the output might change when the input changes
(asynchronous output).
To make Mealy machines synchronous.
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VHDL> State Machines
State Machine Template for Design Style #2
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VHDL> State Machines
State Machine Template for Design Style #2 – cont.
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VHDL> State Machines
Example: Simple FSM #1
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VHDL> State Machines
Example: Simple FSM #1
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VHDL> State Machines
Example: Simple FSM #1
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VHDL> State Machines
Example: Simple FSM #1
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VHDL> State Machines
Example: Simple FSM #2
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VHDL> State Machines
Example: Simple FSM #2
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VHDL> State Machines
Example: Simple FSM #2
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VHDL> State Machines
Example: String Detector
We want to design a circuit that takes as input a serial
bit stream and outputs a „1‟ whenever the sequence
„„111‟‟ occurs. Overlaps must also be considered, that
is, if . . .0111110 . . . occurs, than the output should
remain active for three consecutive clock cycles.
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VHDL> State Machines
Example: String Detector
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VHDL> State Machines
Example: String Detector
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VHDL> State Machines
Example: String Detector
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VHDL> State Machines
Example: String Detector
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VHDL> State Machines
Example: Traffic Light Controller (TLC)
Three modes of operation: Regular, Test, and
Standby.
Test mode: allows all pre-programmed times to be
overwritten (by a manual switch) with a small value,
such that the system can be easily tested during
maintenance (1 second per state).
Standby mode: the system should activate the yellow
lights in both directions and remain so while the
standby signal is active.
Assume that a 60 Hz clock (obtained from the power
line itself ) is available.
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VHDL> State Machines
Example: Traffic Light Controller (TLC)
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VHDL> State Machines
Example: Traffic Light Controller (TLC)
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VHDL> State Machines
Example: Traffic Light Controller (TLC)
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VHDL> State Machines
Example: Traffic Light Controller (TLC)
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VHDL> State Machines
Example: Traffic Light Controller (TLC)
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VHDL> State Machines
Example: Traffic Light Controller (TLC)
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VHDL> State Machines
Example: Traffic Light Controller (TLC)
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VHDL> State Machines
Example: Traffic Light Controller (TLC)
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VHDL> State Machines
FSM Encoding Style:
To encode the states of a state machine, we can
select one among several available styles.
The default style is binary.
requires the least number of flip-flops.
with n flip-flops (n bits), up to 2^n states can be encoded
requires more logic and is slower than the others.
One-hot encoding style,
which uses one flip-flop per state. Therefore, it demands
the largest number of flip-flops.
with n flip-flops (n bits), only n states can be encoded.
requires the least amount of extra logic and is the
fastest.
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VHDL> State Machines
FSM Encoding Style:
Two-hot encoding scheme:
An style that is inbetween the two styles above.
which presents two bits active per state.
Therefore, with n flip-flops (n bits), up to n(n-1)/2 states
can be encoded.
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