8085 Addressing Modes (way of specifying

operands)
Generally data transfer (memory to CPU register, CPU
register to memory, CPU register to CPU register ),
arithmetic & logical operations are performed between 2
operands.

Register Addressing Mode: Both the operands are CPU

registers. Examples:
MOV B, A (the content of A is copied into the register B),
MOV A, C, SUB C (A = A - C),
ANA B (A = A AND B), ORA C (A = A OR C),
XRA D (A = A XOR D)
INR B, DCR C, INX H, DCX B
Immediate Addressing Mode, One particular operand value is
immediately specified within the instruction itself.( instead of
specifying its address of the operand)
An immediate data is transferred directly to the register.
Eg: - MVI A, 30H (30H is copied into the register A), MVI B, 40H, LXI B
8000H, ADI 08H (A = A + 08H), CPI 67H, All conditional /
unconditional JUMP, CALL instructions
JMP 2090 [Unconditional Jump Instr.]: PC  2090H
JNC 2090H (Jump on “No Carry”, to execute from 2090H)
[Conditional Jump Instr.]:
If CY = 0 then only,: PC  2090H requires 3 M-Cycles (OF, MR, MR)
Otherwise: Nothing [PC as usual holds address of next
Instruction(i.e. following )] requires 2 M -
Cycles. (OF, MR). Entire Instruction may need
not to read by processor. As As Flag gets
detected after “OF”
Direct Addressing Mode, one of the operands is residing in
Main Memory or may represent I/P or O/P device data
content. , & the address of one operand (16 bit memory
address or 8 bit device address) is directly specified in the
instruction itself. Examples:
a) SHLD 2050H (store HL Pair Direct):
(1) L→M[2050H]; (2) H→M[2051H];
b) LHLD 2050H (Load HL Pair Direct):
(1) LM[3070H]; (2) HM[3071H];
c)IN 80H: A  Content of input Device with address 80H
d)OUT 81H: A → Output (O/P) Device with address 81H
e) STA 2380H : A→ M[2380]; f) LDA 2381 : A M[2381]
Indirect Addressing Mode: one of the operands is residing in
Main Memory, & the address of that operand (16 bit memory
address) is indirectly specified in some CPU register or register
pair. The register pair acts as memory pointer.
MOV A, M; ADD M, SUB M, ADC M, SBB M, CMP M, ANA M,XRA M
a) STAX B: A→ M[BC Pair content];
b) LDAX B: A M[BC Pair content]
c) MOV B, M: B  M[HL Pair content]
d) ORA M: A = A + M[HL Pair content]
e) PUSH D: (i) SP = SP – 1; (ii) D → M[SP ];
[SP: Stack Pointer Register] (iii) SP = SP – 1; (iv) E→ M[SP]
f) POP D: (i) E M[SP]; (ii) SP = SP + 1;
(iii) D M[SP]; (iv) SP = SP + 1;
[PUSH D: PUSH DE Pair on Stack Top
POP D: Load DE Pair from Stack Top]
Implied Addressing Mode: - This mode doesn't
require any operand. The operand or operand address
is specified is specified by opcode itself.
Eg: - RAL, RAR, RLC, RRC
STC (Set Carry Flag) ( CY = 1),
CMC (Complement CY) ( CY = NOT(CY) ),
NOP (No operation), HALT
Instruction (I) Cycle: Machine (M) Cycle: T- State:
– Instruction (I) Cycle: The time required to complete the
execution of an instruction.
• In the 8085, an instruction cycle may consist of 1 to 6 M
cycles.
– Machine (M) Cycle: The time required to complete one
operation of accessing memory, I/O, or acknowledging an
external request.
• An 8085 M cycle may consist of 3 to 6 T-states.
• [8085 Machine cycles: 1) Opcode Fetch[4T], 2) Memory
Read[3T], 3) Memory Write[3T], 4) Input device Read[3T], 5)
Output device Write[3T], 6)Interrupt Acknowledge[6T], 7)
Halt]
– T- State: One subdivision of an operation that can be performed
in one CPU clock period.
• An instruction’s execution length is usually measured in a
number of T-states. (clock cycles).
CONTROL / STATUS 8085 Machine Cycle
SIGNALS-
8085 Machine Cycle

(3 T)
(3 T)
(3 T)
(3 T)
(4 or 6 T

(6 T)
• The Processor execute Instructions in 3 phases
• a) Instruction fetch, b) Instruction decode & c) Instruction
execute.
• After fetching the entire Instruction from memory, then
processor executes the instruction.
• 8085 instructions can be of 1 or 2 or 3 byte.
• After fetching the opcode (first byte of a machine
instruction), from memory, it is stored in IR, for subsequent
decoding of opcode by Instruction decoder
• If the instruction is 2 or 3 byte, then 2nd & 3rd bytes are some
times stored in Z & W 8-bit registers respectively, or directly
copied into other 8085 registers or to a temporary register as
ALU operand.
• After fetching & placing the opcode in IR, by the subsequent
Instruction decoder, 8085 determines whether it is 1 or 2 or 3
byte instruction, & accordingly proceed with another 0, 1, 2
Memory read operations to fetch the entire 1 or 2 or 3 byte
Instruction
 Commonly used Machine-Cycles (M-Cycles) of 8085 are:
OF (opcode Fetch) requires 4( 6 ) T states = 1, = 0, =0
MR (Memory Read) requires 3 T states = 1, = 0, =0
MW (Memory write) requires 3 T states = 0, = 1, =0
IOR (I/O device Read) requires 3 T states = 1, = 0, =1
IOW (I/O device Write) requires 3 T states = 0, = 1, =1
T-States corresponds to CPU Clock Cycles
As first Byte of any Instruction is op-code byte, Hence first M-cycle
of any instruction cycle is OF.

Instruction Cycle: = (1) Instruction-Fetch(I-F) +

(2) I-Decode [neglecting I-Decode] +
(3) Actual Instruction Execution(I-Ex)
•4th T state (or clock cycle) of opcode fetch machine cycle is
for “decoding of opcode & if possible execution of 1 byte
instructions”.
•Otherwise “OF” is similar to “MR”, except for that 4th clock cycle.
•Instruction decoding and arithmatic / logical
operations on 2, 8 bit operands requires maximally 1
8085 clock cycle.
•Hence for “decoding of opcode & if possible
execution of 1 byte instructions”, no separate 8085
machine cycle is defined, only one more T state
allocation is sufficient (for most cases)
• For some 1 byte Instructions, opcode fetch machine
cycle is of 6 T, instead 4T
•(3T(for reading the opcode from memory) + 1T (for
“decoding of opcode & if possible execution of 1 byte
instructions”))
•Where 6T-State opcode is required
•For 16 bit addition or subtraction instruction Like, INX Rp, DCX Rp, 16
bit addition /subtraction, using 8 –bit ALU of 8085, such operations
needs to be performed in 3 steps:
•1. First LSB bytes are added
• 2. Then MSB bytes are added
• 3. If any carry generated during LSB byte addition, that needs to be
added with the result
• So , these 1 byte Instruction’s execution requires additional 3 8085
Clock, appart from fetching the opcode from Memory
• So for these instructions “Opcode Fetch” machine cycles requires 6
CPU clock (T state)
• [3T for fetching the opcode from memory + 3T for actual actual
execution of these instructions by 8-bit 8085 ALU]
• For execution of “PUSH” & “POP” 1-btye instruction (for storing /
retrieving data from from Stack memory), requires the decrement/
increment of Stack Pointer (SP)(16-bit register), hence requires 6 T
state opcode.
Instruction M-cycles in Instruction Fetch (I-F) phase

1 byte OF (4(or 6)T)

2 byte OF (4(or 6)T), MR (3T)

3 byte OF (4(or 6)T), MR (3T), MR (3T)

Opcode followed by no. of Hex digits Instruction

0 Example: MOV C, L 1 byte

2 (1 byte) (8 bit) Example: MVI C, 28H 2 byte

4 (2 byte) (16 bit) Example: LXI B, 3828H 3 byte