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RTL Design of UART Protocol

The UART protocol allows for asynchronous serial communication between electronic devices. It works by taking parallel input data and adding start, parity, and stop bits to create a serial data frame for transmission. The receiving UART samples the serial data line and strips out the extra bits to recover the original parallel data. The key signals involved are a clock, enable signals for the transmitter and receiver, data inputs and outputs, and status flags. An RTL implementation of the UART protocol was created using Quartus Prime with simulation and synthesis results confirming correct functionality.

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523 views3 pages

RTL Design of UART Protocol

The UART protocol allows for asynchronous serial communication between electronic devices. It works by taking parallel input data and adding start, parity, and stop bits to create a serial data frame for transmission. The receiving UART samples the serial data line and strips out the extra bits to recover the original parallel data. The key signals involved are a clock, enable signals for the transmitter and receiver, data inputs and outputs, and status flags. An RTL implementation of the UART protocol was created using Quartus Prime with simulation and synthesis results confirming correct functionality.

Uploaded by

Anji medidi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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RTL Design of UART Protocol

UART (Universal Asynchronous Receiver Transmitter) is a fundamental serial communication protocol widely
employed to facilitate data exchange between electronic devices. This versatile communication mechanism
allows devices to transmit and receive data asynchronously, making it a cornerstone in inter-device
communication.
UART (UART Asynchronous Receiver Transmitter) is one of the most used device-to-device communication
protocols.

UART Data Transmission Mechanism

• The transmitting UART receive data in parallel from the data bus.
• The transmitting UART adds the start bit, parity bit, and the stop bits to the data frame.
• The entire packet is sent serially staring from start bit to stop bit from the transmitting UART to the
receiving UART. The receiving UART samples the data line at the preconfigured baud rate.
• The receiving UART discards the start bit, parity bit, and stop bit from the data frame.
• The receiving UART converts the serial data back into parallel and transfer it to the data bus on the
receiving end.

Data Transfer in UART Protocol


UART Interface Signals

clock: Clock signal at 50Mhz, driving the entire UART design.


rxclk_en and txclk_en: Signals indicating the enablement of the receiver and transmitter clocks, respectively, for
synchronization.
din: N - bit input data for the transmitter module.
wr_en: Write enable signal triggering the transmitter to start processing data.
clken: Clock enable signal controlling the timing of transmitter and receiver operations.
tx and tx_busy: Transmitter output signal and busy flag indicating the transmission status.
rx: Input signal for the receiver, representing the received data.
rdy: Output signal indicating the readiness of the receiver to process new data.
rdy_clr: Clear signal for resetting the receiver’s ready state.
dout: N - bit output data from the receiver module.

GitHub Code Repo: https://github.com/asimkhan8107/UART

Tools: Intel Quartus Prime


Schematic: Quartus RTL viewer
Simulator – Questa sim

References: Basics of UART Communication


UART a hardware communication protocol

Simulation Result=>
RTL Schematic =>

Check my previous post : “RTL Design of AXI Stream Protocol”.

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