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DLD Lab Prog

The document contains code for several basic digital logic components including: 1) An AND, OR, and NOT gate that takes two inputs and outputs the results. 2) A multiplexer that takes an input and selector and outputs the input to one of four outputs based on the selector value. 3) A K-map logic circuit that implements a logic function using a, b, c, and d inputs. 4) A BCD to binary decoder that takes a 4-bit selector and outputs a 16-bit binary value. 5) A 3-bit decoder that takes a selector and outputs one of eight outputs.

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1GA22IS138Sanjay K. S.
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56 views8 pages

DLD Lab Prog

The document contains code for several basic digital logic components including: 1) An AND, OR, and NOT gate that takes two inputs and outputs the results. 2) A multiplexer that takes an input and selector and outputs the input to one of four outputs based on the selector value. 3) A K-map logic circuit that implements a logic function using a, b, c, and d inputs. 4) A BCD to binary decoder that takes a 4-bit selector and outputs a 16-bit binary value. 5) A 3-bit decoder that takes a selector and outputs one of eight outputs.

Uploaded by

1GA22IS138Sanjay K. S.
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

BASIC GATES

library ieee;
use ieee.std_logic_1164.all;

entity basicgates is
port (
input_1: in std_logic;
input_2: in std_logic;
and_result: out std_logic
or result: out std_logic;
not_result: out std_logic;
);
end basicgates;

architecture result of basicgates is


signal basicgates: std_logic;
begin
and_gate <= input_1 and input_2;
or gate_ <= input_1 and input_2;
not_gate <= not input_1;
and_result <= and_gate;
end result;

MULTIPLEXER PROGRAM

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity demux is
Port ( i : in std_logic;
sel : in std_logic_vector(1 downto 0);
z : out std_logic_vector(3 downto 0));
end demux;

architecture Behavioral of demux is

begin process(i, sel)


begin if(sel="00")then
z(0)<=i;
elsif(sel="01")then
z(1)<=i;
elsif(sel="10")then
z(2)<=i;
elsif(sel="11")then
z(3)<=i;
end if;
end process;
end Behavioral;
DEMULTIPLEXER PROGRAM
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity demux is
Port ( i : in std_logic;
sel : in std_logic_vector(1 downto 0);
z : out std_logic_vector(3 downto 0));
end demux;

architecture Behavioral of demux is

begin process(i, sel)


begin if(sel="00")then
z(0)<=i;
elsif(sel="01")then
z(1)<=i;
elsif(sel="10")then
z(2)<=i;
elsif(sel="11")then
z(3)<=i;
end if;
end process;

end Behavioral;
K-MAP
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity kmap is
Port ( a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end kmap;

architecture Behavioral of kmap is

begin
y<=((a and not b) or(b and d) or(c and not(d)));

end Behavioral;
BCD PROGRAM
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity bcd is
Port ( sel : in std_logic_vector(3 downto 0);
z : out std_logic_vector(15 downto 0));
end bcd;

architecture Behavioral of bcd is


begin process(sel)
begin if(sel="0000")then
z<="0000000000000001";
elsif(sel="0001")then
z<="0000000000000010";
elsif(sel="0010")then
z<="0000000000000100";
elsif(sel="0011")then
z<="0000000000001000";
elsif(sel="0100")then
z<="0000000000010000";
elsif(sel="0101")then
z<="0000000000100000";
elsif(sel="0110")then
z<="0000000001000000";
elsif(sel="0111")then
z<="0000000010000000";
elsif(sel="1000")then
z<="0000000100000000";
elsif(sel="1001")then
z<="0000001000000000";
elsif(sel="1010")then
z<="0000010000000000";
elsif(sel="1011")then
z<="0000100000000000";
elsif(sel="1100")then
z<="0001000000000000";
elsif(sel="1101")then
z<="0010000000000000";
elsif(sel="1110")then
z<="0100000000000000";
elsif(sel="1111")then
z<="1000000000100000";
end if;
end process;
end Behavioral;
DECODER PROGRAM

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating


---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity decode is
Port ( sel : in std_logic_vector(2 downto 0);
zout : out std_logic_vector(7 downto 0));
end decode;

architecture Behavioral of decode is


begin
process(sel)
begin
if(sel="000")then
zout<="00000001" ;
elsif(sel="001")then
zout<="00000010" ;
elsif(sel="010")then
zout<="00000100" ;
elsif(sel="011")then
zout<="00001000" ;
elsif(sel="100")then
zout<="00010000" ;
elsif(sel="101")then
zout<="00100000" ;
elsif(sel="110")then
zout<="01000000" ;
else
zout<="10000000" ;
end if;
end process;
end Behavioral;

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