The 8051 Microcontroller

Chapter 3
INSTRUCTION SET SUMMARY
ADDRESSING MODE
• The MCS-51® instruction set is optimized for 8-
bit control applications. It provides a variety of
fast, compact addressing modes for accessing the
internal RAM to facilitate operations on small data
structures. The instruction set offers extensive
support for 1-bit variables, allowing direct bit
manipulation in control and logic systems that
require Boolean processing.
• 8051 instructions have 8-bit opcodes
• Possibility of 28 = 256 instructions
• 255 are implemented and 1 is undefined
• Some instructions have one or two additional
bytes for data or addresses
• There are 139 1-byte instructions, 92 2-byte
instructions, and 24 3-byte instructions
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 ADDRESSING MODES
• Register
• Direct
• Indirect
• Immediate
• Relative
• Absolute
• Long
• Indexed

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 Register Addressing
• 8 "working registers," numbered R0 through R7.
• Instructions using register addressing are encoded
using the three least-significant bits of the
instruction opcode to specify a register within this
logical address space
• Function code and operand address can be
combined to form a short (1-byte) instruction.
• 8051 assembly language indicates register
addressing with the symbol Rn where n is from 0
to 7.

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• There are four "banks" of working registers, but only one is
active at a time.
• Register banks occupy the first 32 bytes of on-chip data RAM
(addresses OOH-1FH) with PSW bits 4 and 3 determining the
active bank
• Hardware reset enables bank 0
• Some instructions are specific to a certain register, such as the
accumulator, data pointer, etc., so address bits are not needed.
• Opcode itself indicates the register
• These "register-specific" instructions refer to the accumulator as
"A," the data pointer as "DPTR," the program counter as "PC,"
the carry flag as "C," and the accumulator-B register pair as
"AB."

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 Direct Addressing
• Can access any on-chip variable or hardware register
• Additional byte is appended to the opcode specifying the location to
be used
• Depending on the high-order bit of the direct address, one of two
on-chip memory spaces is selected.
• When bit 7 = 0, the direct address is between 0 and 127 (00H-7FH)
and the 128 low-order on-chip RAM locations are referenced.
• All I/O ports and special function, control, or status registers,
however, are assigned addresses between 128 and 255 (80H-FFH).
• When bit 7 = 1, the corresponding special function register is
accessed.
• It is usually not necessary to know the addresses of these registers:
the assembler allows for and understands the mnemonic
abbreviations ("P0"for Port 0, "TMOD" for timer mode register,
etc.).
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 Indirect Addressing
• R0 and R1 may operate as "pointer" registers-their
contents indicating an address in internal RAM
• The least-significant bit of the instruction opcode
determines which register (R0 or R1) is used as
the pointer.
• Indirect addressing is represented by a commercial
"at" sign (@) preceding R0 or R1

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• Indirect addressing is essential when stepping through
sequential memory locations. For example, the following
instruction sequence clears internal RAM from address
60H to 7FH:

MOV R0, #60H

LOOP: MOV @R0, #0
INC R0
CJNE R0, #80H, LOOP
(continue)
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 Immediate Addressing
• When a source operand is a constant, then the constant can
be incorporated into the instruction as a byte of
"immediate" data.
• Additional instruction byte contains the value
• Immediate operands are preceded by a number sign (#)
• The operand may be a numeric constant, a symbolic
variable, or an arithmetic expression using constants,
symbols, and operators.
• One exception, all instructions using immediate addressing
use an 8-bit data constant for the immediate data. When
initializing the data pointer, a 16-bit constant is required.
• MOV DPTR, #8000 - is a 3-byte instruction that
loads the 16-bit constant 8000H into the data pointer

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 Relative Addressing
• Used only with certain jump instructions
• Relative address (or offset) is an 8-bit signed value, which
is added to the program counter to form the address of the
next instruction executed
• The range for jumping is -128 to +127 locations
• Relative offset is appended to the instruction as an
additional byte
• Prior to the addition, the program counter is incremented to
the address following the jump instruction; thus. the new
address is relative to the next instruction, not the address of
the jump instruction.
• Advantage - providing position-independent code
• Disadvantage - jump destinations are limited in range

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 Absolute Addressing
• Used only with the ACALL and AJMP instructions
• These 2-byte instructions allow branching within the
current 2K page of code memory by providing the 11 least-
significant bits of the destination address in the opcode
(A10-A8) and byte 2 of the instruction (A7-AO).
• The upper five bits of the destination address are the
current upper five bits in the program counter, so the
instruction following the branch instruction and the
destination for the branch instruction must be within the
same 2K page.
• Advantage - short (2-byte) instructions
• Disadvantages - limiting the range for the destination and
providing position dependent code

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 Long Addressing
• Used only with the LCALL and LJMP instructions
• These 3-byte instructions include a full 16-bit
destination address as bytes 2 and 3 of the
instruction.
• Advantage - full 64K code space may be used
• Disadvantage - the instructions are three bytes
long and are position-dependent

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 Indexed Addressing
• Uses a base register (either the program
counter or the data pointer) and an offset
(the accumulator) in forming the effective
address for a JMP or MOVC instruction.
• Jump tables or look-up tables are easily
created using indexed addressing.
• MOVC A, @A+<base-reg> and
• JMP @A+DPTR instructions.

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