Memory Interfacing
Contents
6. 1 Introduction
6.2 Terminology and Operations
6. 3 Memory Structure and its Requirements
6. 4 Basic Concepts in Memory
Interfacing with 8085 . . . . . . . . . . . . . . . . . . Dec.-05, 07, 10, 11, 16,
. . . . . . . . . . . . . . . . . . May-08, 10, 11, 17, • • • • • • Marks 16
6.5 Two Marks Questions with Answers
6. 6 University Questions with Answers (Long Answered Questions)
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Introduction
Memory is an integral part of a microprocessor system, a11d in this chapter, we will
discuss how to interface a memory device with the microprocessor. The memory
interfacing circuit is used to access memory quite frequently to read instruction codes
and data stored in memory. This read/write operations are monitored by control signals.
The microprocessor activates these signals when it wants to read from and write into
memory. In this chapter we will see memory structure and its requirements, concepts in
memory interfacing and interfacing examples.
Terminology and Operations
Memories are made up of registers. Each register in the memory is one storage
location. Each location is identified by an address. T11e number of storage locations can
vary from a few in some memories to l1undreds of thousand in others. Each location can
accommodate one or more bits. Generally, the total ntrmber of bits that a memory can
store is its capacity. Most of the types the capacity is specified in terms of bytes (group
of eight bits).
Each register consists of storage elements (flip-flops or capacitors in semiconductor
memories and magnetic domain in magnetic storage), each of which stores one bit of
data. A storage element is called a cell.
The data stored in a memory by a process called writing and are retrieved from the
memory by a process called reading. Fig. 6.2.1 illustrates in a very simplified way the
concept of write, read, address and storage capacity for a generalized memory.
Storage Cells
,
Addres s Address
0 JI 0
1 1
2 1 0 0 0 .. 1 0 01 2 1 0 0 0 _., Reading Data
Writing Data
3 3
4 4
5 5
6 6
---- ----
n-1 n-1
n n
(a) Write operation (b) Read operation
Fig. 6.2.1
Review Questions
1. What is address ?
2. What is memory capacity ?
Memory Structure and its Requirements
As mentioned earlier, read/write memories consist of an array of registers, in which
each register has unique address. The size of the memory is N x M as shown in
Fig. 6.3.1 (a) where N is the number of registers and M is the word length, in number
of bits.
Input
data
Input buffer
0 'ifiiri:.
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4096 X 8
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Output buffer Output buffer
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Output Output
data data
(a) Logic diagram for RAM (b) Logic diagram for EPROM
Fig. 6.3.1
Example 1 : If memory is haviI1g 1 2 address lines and 8 data lines, then
Number of registers/memory locations = 2 N = 212
= 4096
Word length = M-bit
= 8-bit
Example 2 : If memory has 819 2 memory locations, then it l1as 13 address lines.
The Table 6.3.1 stunmarizes the memory capacity and address lines required for
memory interfacing.
Memory capacity Address lines re quired
1K = 1024 memory locations 10
2K = 2048 memory locations 11
4K = 4096 memory locations 12
8K = 8192 memory locations 13
16 K = 16384 memory locations 14
32 K = 32768 memory locations 15
64 K = 65536 memory locations 16
Table 6.3.1
As shown in the Fig. 6.3.1 (a) memory chip has 12 address lines A0-A11, one chip
select (CS), and two control lines, read (RD) to enable outpt1t buffer and write (WR) to
enable the input buffer. The internal decoder is used to decode the address lines.
Fig. 6.3.l(b) shows the logic diagram of a typical EPROM (Erasable Programmable
Read-Only Memory) with 4096 (4 K) registers. It has 12 address lines A0-A11, one chip
select (CS), one Read control signal. Since EPROM is a read only memory, it does not
require the (WR) signal.
Review Questions
1. Explain the memory structure an"d its requirements.
2. How much address lines are required to interface 4 kbytes of memory ?
Basic Concepts in Memory Interfacing with 8085
AU : Dec.-05, 07, 10, 11, 16, May-08, 10, 11, 17
For interfacing memory devices to microprocessor 8085, following important points
are to be kept in mind.
1. Microprocessor 8085 can access 64 kbytes memory since address bus is 16-bit. But
it is not always necessary to use full 64 kbytes address space. The total memory
size depends upon the application.
2. Generally EPROM (or EPROMs) is used as a program memory and RAM (or
RAMs) as a data memory. When both, EPROM and RAM are used, the total
address space 64 kbytes is sl1ared by them.
3. The capacity of program memory and data memory depends on the application.
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4. It is not always necessary to select 1 EPROM and 1 RAM. We can have multiple
EPROMs and multiple RAMs as per the requirement of application.
For example: We have to implement 32 kbytes of program memory and 4 kbytes
EPROMs are available. In this case, we can connect 8 EPROMs in parallel
(4 kbytes x 8 = 32 kbytes) with different chip select for each EPROM.
5. We can place EPROM/RAM anywhere in full 64 kbytes address space. But
program memory (EPROM) should be located from address OOOOH since reset
address of 8085 microprocessor is OOOOH.
6. It is not always necessary to locate EPROM and RAM in consecutive memory
addresses. For exam ple : If the mapping of EPROM is from OOOOH to OFFFH, it is
not must to locate RAM from 1000H. We can locate it anywhere between 1000H
and FFFFH. Where to locate memory component totally depends on the
application.
Memory Interfacing Requirements
• Select the chip.
• Identify the register.
• Enable the appropriate buffer.
Microprocessor system includes memory devices and 1/0 devices. It is important to
note that microprocessor can communicate (read/write) with only one device at a time,
since the data, address and control buses are common for all the devices. In order to
communicate with memory or 1/0 devices, it is necessary to decode the address from
the microprocessor. Due to this each device (memory or 1/0) can be accessed
independently. The following section describes common address decoding techniques.
Address Decoding Techniques
• Absolute decoding/Full decoding.
• Linear decoding/Partial decoding.
Absolute decoding
In absolute decoding technique, all the higher address lines are decoded to select the
memory chip, and the memory chip is selected only for the specified logic levels on
these high-order address lines; no other logic levels can select the chip. Fig. 6.4.1 shows
the memory interface with absolute decoding. This addressing technique is normally
used in large memory systems.
Memory Map:
Memory ICs A15 A14 A1 A12 All AlO A9 As A7 A6 A5 A4 A3 A2 Al Ao Address
3
Starting address of 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OOOOH
EPROM
End address of 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 03FFH
EPROM
Starting address of 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 2000H
RAM
End address of RAM 0 0 1 0 0 0 1 1 1 1 1 1 1 1 1 1 23FFH
Table 6.4.1
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Linear decoding
In small systems, hardware for the decoding logic can be eliminated by t1sing
individual high-order address lines to select memory chips. This is referred to as linear
decoding. Fig. 6.4.2 shows the addressing of RAM with linear decoding technique. This
teclmique is also called partial decoding. It reduces the cost of decoding circuit, but it
l1as a drawback of multiple addresses (shadow addresses).
Fig. 6.4.2 shows the addressing of RAM with linear decoding technique. A 15 address
line, is directly connected to the chip select signal of EPROM and after inversion it is
connected to the chip select signal of the RAM. Therefore, when the status of A 15 line is
'zero', EPROM gets selected and when the status of A 15 line is 'one' RAM gets selected.
The stah1s of the other address lines is not considered, since those address lines are not
used for generation of chip select signals.
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Fig. 6.4.2 Linear decoding
Memory Map:
Memory ICs A1 A1 A1 A12 A 11 A10 A9 A3 A7 A6 A 5 A4 A3 A2 A1 Ao Address
5 4 3
Startil1g address of EPROM 0 X X X X X 0 0 0 0 0 0 0 0 0 0 OOOOH
End address of EPROM 0 X X X X X 1 1 1 1 1 1 1 1 1 1 03FFH
Startil1g address of RAM 1 X X X X X 0 0 0 0 0 0 0 0 0 0 8000H
End address of .RAM 1 X X X X X 1 1 1 1 1 1 1 1 1 1 83FFH
Table 6.4.2
Sr. No. Full address decoding Partial address decoding
1. All higl1er address lines are decoded to Few 11.igher address lines are decoded to
select the memory or I/0 device. select tl1e memory or I/0 device.
2. More hard ware is req11ired to design Hardware req1lired to design decoding
decoding logic. logic is less and sometimes it can be
- eliminated.
3. Higher cost for decoding circuit. Less cost for decoding circ11it.
4. No multiple addresses. It has a disadvantage of multiple
addresses (shadow addresses).
5. Used in large systems. Used in small systems.
6.4.1 Interfacing Examples
Example 6.4.1 Design memory system for the 8085 microprocessor such that it shoitld
contain 8 kbyte of EPROM (Erasable Programmable Read Only Memory) and 8 kbyte of
RAM ( Read/Write Memory). AU : Dec.-05, Marks 8
Solution : Fig. 6.4.3 shows the desired memory system using IC 2764 (8 K) EPROM
and 6264 (8 K) RAM. Memory requires 13 address lines (A0 -A12) since 2 13 = 8 K. T11e
remaining address lines (A 1 3 - A 15 ) are decoded to generate chip select ( CS ) signals.
IC 74LS138 is used as decoder. When ( A15 - A13 ) address lines are zero, the Y0 output
of decoder goes low and selects tl1e EPROM. This means that A 15 - A 1 3 address lines
must be zero to read data from EPROM. The address lines A12 - A0 select the partic11lar
memory location in the EPROM when A 15 - A 13 lines are zero. Similarly, when address
lines A 15 - A 13 are 001, the Y1 output of decoder goes low and selects the RAM. The
Table 6.4.3 shows the memory map for the designed circuit.
Memory Map:
Memory ICs A15 A14 A13 A12 A11 A10 A9 A3 A 7 A6 A5 A4 A3 A2 Al Ao A ddress
I
Starting address of 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OOOOH
EPROM
End address of EPROM 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 lFFFH
Starting address of 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 2000H
RAM
End address of RAM 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3FFFH
Table 6.4.3 Memory map
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Fig. 6.4.3 Memory system using IC 2764 (8 K) EPROM and 6264 (8 K) RAM
Example 6.4.2 Design a microprocessor system for tl1e 8085 microprocessor such that it
should contain 16 kbyte of EPROM and 4 kbyte of RAM itsing two 8 kbyte EPROMs
(2764) and two 2 kbyte RAMs (6116).
Solution : Fig. 6.4.4 (See on next page) shows the desired memory system using two
(8 K x 8) EPROM and two (2 K x 8) RAMs. EPROM memory is 8 K, so it requires
13 address lines (A 12 - A 0) whereas RAM memory is 2 K, so it requires 11 address lines
(A 10 - A0). The remaining higher address lines (A15 - A13) are used to generate
chip-select (CS) signals. Table 6.4.4 shows the memory map for the designed circt1it.
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