001.

A PLA is similar to a ROM in concept except that ____________ C

A It hasnt capability to read only B It hasnt capability to read or write
operation
C It doesnt provide full decoding to the D It hasnt capability to write only
variables
002. For programmable logic functions, which type of PLD should be used? B
A PLA B PAL
C CPLD D SLD
003. PLA is used to implement ____________ C
A A complex sequential circuit B A simple sequential circuit
C A complex combinational circuit D A simple combinational circuit
004. The inputs in the PLD is given through ____________ D
A NAND gates B OR gates
C NOR gates D AND gates
005. PAL refers to ____________ C
A Programmable Array Loaded B Programmable Logic Array
C Programmable Array Logic D Programmable AND Logic
006. Outputs of the AND gate in PLD is known as ____________ B
A Input lines B Output lines
C Strobe lines D Control lines
007. PLA contains ____________ A
A AND and OR arrays B NAND and OR arrays
C NOT and AND arrays D NOR and OR arrays
008. A _________ has both decoder and OR gates within the IC package. A
A PROM B PLA
C PAL D PLD
009. In a programmable ROM, A
A AND array is fixed, OR array is B AND array is programmable, OR
programmable. array is fixed.
C AND array is fixed, OR array is fixed. D AND array is programmable, OR
array is programmable.
010. In FPGA, vertical and horizontal directions are separated by ____________ B
A A line B A channel
C A strobe D A flip-flop
011. The complex programmable logic device contains several PLD blocks and __________ C
A A language compiler B AND/OR arrays
C Global interconnection matrix D Field-programmable switches
012. The difference between a PAL & a PLA is ____________ B
A PALs and PLAs are the same thing B The PLA has a programmable OR
plane and a programmable AND
plane, while the PAL only has a
programmable AND plane
C The PAL has a programmable OR D The PAL has more possible product
plane and a programmable AND terms than the PLA
plane, while the PLA only has a
programmable AND plane
013. If a PAL has been programmed once ____________ D
A Its logic capacity is lost B Its outputs are only active HIGH
C Its outputs are only active LOW D It cannot be reprogrammed
014. The FPGA refers to ____________ B
A First programmable Gate Array B Field Programmable Gate Array
C First Program Gate Array D Field Program Gate Array
015. A latch is an example of a ___________ C
A Monostable multivibrator B Astable multivibrator
 C Bistable multivibrator D 555 timer
016. Latch is a device with ___________ B
A One stable state B Two stable state
C Three stable state D Infinite stable states
017. The reading speed is extremely high in, B
A PAL B PROM
C PLA D FPGA
018. A _______ implements only those Boolean functions which are in standard SOP form. C
A PAL B PLA
C PROM D ROM
019. In a 64*4 PROM, the number of input and output to the decoder are _____ and ____ . A
A 6 and 64 B 2 and 8
C 4 and 16 D 5 and 32
020. ________ is more expensive and flexible than PAL. A
A PLA B PAL
C PROM D RAM
021. The different types of sequential programmable devices are, C
A PAL B PLA
C CPLD D PPL
022. The NAND latch works when both inputs are ___________ A
A 1 B 0
C Inverted D Dont cares
023. The first step of the analysis procedure of SR latch is to ___________ B
A label inputs B label outputs
C label states D label tables
024. The SR latch consists of ___________ B
A 1 input B 2 inputs
C 3 inputs D 4 inputs
025. Why latches are called memory devices? C
A It has capability to stare 8 bits of data B It has internal memory of 4 bit
C It can store one bit of data D It can store infinite amount of data
026. Two stable states of latches are ___________ C
A Astable & Monostable B Low input & high output
C High output & low output D Low output & high input
027. How many types of latches are ___________ A
A 4 B 3
C 2 D 5
028. The full form of SR is ___________ B
A System rated B Set reset
C Set ready D Set Rated
029. One example of the use of an S-R flip-flop is as ___________ C
A Transition pulse generator B Racer
C Switch debouncer D Astable oscillator
030. The truth table for an S-R flip-flop has how many VALID entries? C
A 1 B 2
C 3 D 4
031. Latches constructed with NOR and NAND gates tend to remain in the latched condition D
due to which configuration feature?
A Low input voltages B Synchronous operation
C Gate impedance D Cross coupling
032. The inputs of SR latch are ___________ C
A x and y B a and b
C s and r D j and k
033. When a high is applied to the Set line of an SR latch, then ___________ A
 A Q output goes high B Q output goes high
C Q output goes low D Both Q and Q go high
034. When both inputs of SR latches are low, the latch ___________ C
A Q output goes high B Q output goes high
C It remains in its previously set or reset D it goes to its next set or reset state
state
035. When both inputs of SR latches are high, the latch goes ___________ C
A Unstable B Stable
C Metastable D Bistable
036. How many types of sequential circuits are? A
A 2 B 3
C 4 D 5
037. The sequential circuit is also called ___________ B
A Flip-flop B Latch
C Strobe D Adder
038. Whose operations are more faster among the following? A
A Combinational circuits B Sequential circuits
C Latches D Flip-flops
039. When both inputs of a J-K flip-flop cycle, the output will ___________ C
A Be invalid B Change
C Not change D Toggle
040. Which of the following is correct for a gated D-type flip-flop? A
A The Q output is either SET or RESET B The output complement follows the
as soon as the D input goes HIGH or input when enabled
LOW
C Only one of the inputs can be HIGH D The output toggles if one of the inputs
at a time is held HIGH
041. A basic S-R flip-flop can be constructed by cross-coupling of which basic logic gates? C
A AND or OR gates B XOR or XNOR gates
C NOR or NAND gates D AND or NOR gates
042. The logic circuits whose outputs at any instant of time depends only on the present B
input but also on the past outputs are called ________________
A Combinational circuits B Sequential circuits
C Latches D Flip-flops
043. What is an ambiguous condition in a NAND based S-R latch? D
A S=0, R=1 B S=1, R=0
C S=1, R=1 D S=0, R=0
044. In a NAND based S-R latch, if S=1 & R=1 then the state of the latch is ____________ A
A No change B Set
C Reset D Forbidden
045. The circuits of NOR based S-R latch classified as asynchronous sequential circuits, C
why?
A Because of inverted outputs B Because of triggering functionality
C Because of cross-coupled connection D Because of inverted outputs &
triggering functionality
046. The basic latch consists of ___________ A
A Two inverters B Two comparators
C Two amplifiers D Two adders
047. In S-R flip-flop, if Q = 0 the output is said to be ___________ B
A Set B Reset
C Previous state D Current state
048. The output of latches will remain in set/reset untill ___________ A
A The trigger pulse is given to change B Any pulse given to go into previous
the state state
 C They dont get any pulse more D The pulse is edge-triggered
049. What is a trigger pulse? A
A A pulse that starts a cycle of B A pulse that reverses the cycle of
operation operation
C A pulse that prevents a cycle of D A pulse that enhances a cycle of
operation operation
050. What is one disadvantage of an S-R flip-flop? D
A It has no Enable input B It has a RACE condition
C It has no clock input D Invalid State
051. One example of the use of an S-R flip-flop is as ____________ C
A Racer B Stable oscillator
C Binary storage register D Transition pulse generator
052. The S-R flip flop consist of ____________ B
A 4 AND gates B Two additional AND gates
C An additional clock input D 3 AND gates
053. A NAND based S-R latch can be converted into S-R latch by placing ____________ D
A A D latch at each of its input B An inverter at each of its input
C It can never be converted D Both a D latch and an inverter at its
input
054. One major difference between a NAND based S-R latch & a NOR based S-R latch is A
____________
A The inputs of NOR latch are 0 but 1 B The inputs of NOR latch are 1 but 0
for NAND latch for NAND latch
C The output of NAND latch becomes D The output of NOR latch is 1 but 0 for
set if S=0 & R=1 and vice versa for NAND latch
NOR latch
055. The difference between a flip-flop & latch is ____________ C
A Both are same B Flip-flop consist of an extra output
C Latches has one input but flip-flop D Latch has two inputs but flip-flop has
has two one
056. How many types of flip-flops are? C
A 2 B 3
C 4 D 5
057. Which circuit is generated from D flip-flop due to addition of an inverter by causing D
reduction in the number of inputs?
A Gated JK-latch B Gated SR-latch
C Gated T-latch D Gated D-latch
058. The characteristic of J-K flip-flop is similar to _____________ A
A S-R flip-flop B D flip-flop
C T flip-flop D Gated T flip-flop
059. The circuit that is primarily responsible for certain flip-flops to be designated as edge- A
triggered is the _____________
A Edge-detection circuit B NOR latch
C NAND latch D Pulse-steering circuit
060. When is a flip-flop said to be transparent? B
A When the Q output is opposite the B When the Q output follows the input
input
C When you can see through the IC D When the Q output is complementary
packaging of the input
061. On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when C
________
A The clock pulse is LOW B The clock pulse is HIGH
C The clock pulse transitions from LOW D The clock pulse transitions from HIGH
to HIGH to LOW
062. What is the hold condition of a flip-flop? B
A Both S and R inputs activated B No active S or R input
C Only S is active D Only R is active
063. If an active-HIGH S-R latch has a 0 on the S input and a 1 on the R input and then the B
R input goes to 0, the latch will be ________
A SET B RESET
C Clear D Invalid
064. What is the significance of the J and K terminals on the J-K flip-flop? C
A There is no known significance in B The J represents jump, which is how
their designations the Q output reacts whenever the
clock goes high and the J input is also
HIGH
C The letters were chosen in honour of D All of the other letters of the alphabet
Jack Kilby, the inventory of the are already in use
integrated circuit
065. On a J-K flip-flop, when is the flip-flop in a hold condition? A
A J = 0, K = 0 B J = 1, K = 0
C J = 0, K = 1 D J = 1, K = 1
066. A J-K flip-flop with J = 1 and K = 1 has a 20 kHz clock input. The Q output is ________ D
A Constantly LOW B Constantly HIGH
C A 20 kHz square wave D A 10 kHz square wave
067. A J-K flip-flop can be obtained from the clocked S-R flip-flop by augmenting A
___________
A Two AND gates B Two NAND gates
C Two NOT gates D Two OR gates
068. How is a J-K flip-flop made to toggle? D
A J = 0, K = 0 B J = 1, K = 0
C J = 0, K = 1 D J = 1, K = 1
069. The phenomenon of interpreting unwanted signals on J and K while Cp (clock pulse) is B
HIGH is called ___________
A Parity error checking B Ones catching
C Digital discrimination D Digital filtering
070. In J-K flip-flop, no change condition appears when ___________ D
A J = 1, K = 1 B J = 1, K = 0
C J = 0, K = 1 D J = 0, K = 0
071. The D flip-flop has _______ input. A
A 1 B 2
C 3 D 4
072. The D flip-flop has ______ output/outputs. A
A 2 B 3
C 4 D 1
073. In D flip-flop, D stands for _____________ B
A Distant B Data
C Desired D Delay
074. Two J-K flip-flops with their J-K inputs tied HIGH are cascaded to be used as counters. A
After four input clock pulses, the binary count is ________
A 00 B 11
C 01 D 10
075. Four J-K flip-flops are cascaded with their J-K inputs tied HIGH. If the input frequency B
(fin) to the first flip-flop is 32 kHz, the output frequency (fout) is ________
A 1 kHz B 2 kHz
C 4 kHz D 16 kHz
076. Determine the output frequency for a frequency division circuit that contains 12 flip- B
flops with an input clock frequency of 20.48 MHz.
 A 10.24 kHz B 5 kHz
C 30.24 kHz D 15 kHz
077. How many flip-flops are in the 7475 IC? C
A 2 B 1
C 4 D 8
078. With regard to a D latch ________ C
A The Q output follows the D input B The Q output is opposite the D input
when EN is LOW when EN is LOW
C The Q output follows the D input D The Q output is HIGH regardless of
when EN is HIGH ENs input state
079. Which of the following is correct for a D latch? B
A The output toggles if one of the inputs B Q output follows the input D when the
is held HIGH enable is HIGH
C Only one of the inputs can be HIGH D The output complement follows the
at a time input when enabled
080. Which of the following is correct for a gated D flip-flop? D
A The output toggles if one of the inputs B Only one of the inputs can be HIGH
is held HIGH at a time
C The output complement follows the D Q output follows the input D when the
input when enabled enable is HIGH
081. A D flip-flop can be constructed from an ______ flip-flop. A
A S-R B J-K
C T D S-K
082. In D flip-flop, if clock input is LOW, the D input ___________ A
A Has no effect B Goes high
C Goes low D Has effect
083. In D flip-flop, if clock input is HIGH & D=1, then output is ___________ A
A 0 B 1
C Forbidden D Toggle
084. Which statement describes the BEST operation of a negative-edge-triggered D flip- A
flop?
A The logic level at the D input is B The Q output is ALWAYS identical to
transferred to Q on NGT of CLK the CLK input if the D input is HIGH
C The Q output is ALWAYS identical to D The Q output is ALWAYS identical to
the D input when CLK = PGT the D input
085. How many types of the counter are there? B
A 2 B 3
C 4 D 5
086. Ripple counters are also called ____________ B
A SSI counters B Asynchronous counters
C Synchronous counters D VLSI counters
087. The characteristic equation of D-flip-flop implies that ___________ D
A The next state is dependent on B The next state is dependent on
previous state present state
C The next state is independent of D The next state is independent of
previous state present state
088. Which of the following describes the operation of a positive edge-triggered D flip-flop? B
A If both inputs are HIGH, the output B The output will follow the input on the
will toggle leading edge of the clock
C When both inputs are LOW, an invalid D The input is toggled into the flip-flop
state exists on the leading edge of the clock and
is passed to the output on the trailing
edge of the clock
089. A D flip-flop utilizing a PGT clock is in the CLEAR state. Which of the following input D
 actions will cause it to change states?
A CLK = NGT, D = 0 B CLK = PGT, D = 0
C CLOCK NGT, D = 1 D CLOCK PGT, D = 1
090. A positive edge-triggered D flip-flop will store a 1 when ________ B
A The D input is HIGH and the clock B The D input is HIGH and the clock
transitions from HIGH to LOW transitions from LOW to HIGH
C The D input is HIGH and the clock is D The D input is HIGH and the clock is
LOW HIGH
091. Why do the D flip-flops receive its designation or nomenclature as Data Flip-flops? C
A Due to its capability to receive data B Due to its capability to store data in
from flip-flop flip-flop
C Due to its capability to transfer the D Due to erasing the data from the flip-
data into flip-flop flop
092. The ________ counter in the Altera library has controls that allow it to count up or B
down, and perform synchronous parallel load and asynchronous cascading.
A 74134 B LPM
C Synchronous D AHDL
093. The minimum number of flip-flops that can be used to construct a modulus-5 counter is A
____________
A 3 B 8
C 5 D 10
094. Which counters are often used whenever pulses are to be counted and the results D
displayed in decimal?
A Synchronous B Bean
C Decade D BCD
095. Synchronous counter is a type of ____________ C
A SSI counters B LSI counters
C MSI counters D VLSI counters
096. Modulus refers to ____________ D
A A method used to fabricate decade B The modulus of elasticity, or the
counter units ability of a circuit to be stretched from
one mode to another
C An input on a counter that is used to D The maximum number of states in a
set the counter state, such as counter sequence
UP/DOWN
097. A sequential circuit design is used to ____________ D
A Count up B Count down
C Decode an end count D Count in a random order
098. In general, when using a scope to troubleshoot digital systems, the instrument should C
be triggered by ____________
A The A channel or channel 1 B The vertical input mode, when using
more than one channel
C The system clock D Line sync, in order to observe
troublesome power line glitches
099. Program counter in a digital computer ____________ D
A Counts the number of programs run B Counts the number of times a
in the machine subroutine
C Counts the number of time the loops D Points the memory address of the
are executed current or the next instruction
100. Fundamental mode is another name for ____________ B
A Level operation B Pulse operation
C Clock operation D Edge operation
101. High speed counter is ____________ C
A Ring counter B Ripple counter
 C Synchronous counter D Asynchronous counter
102. The duty cycle of the most significant bit from a 4-bit (0-9) BCD counter is A
____________
A 20% B 50%
C 10% D 80%
103. Normally, the synchronous counter is designed using ____________ B
A S-R flip-flops B J-K flip-flops
C D flip-flops D T flip-flops
104. MOD-16 counter requires ________ no. of states. C
A 8 B 4
C 16 D 32
105. What is a state diagram? B
A It provides the graphical B It provides exactly the same
representation of states information as the state table
C It is same as the truth table D It is similar to the characteristic
equation
106. Registers capable of shifting in one direction is ___________ B
A Universal shift register B Unidirectional shift register
C Unipolar shift register D Unique shift register
107. A shift register is defined as ___________ B
A The register capable of shifting B The register capable of shifting
information to another register information either to the right or to the
left
C The register capable of shifting D The register capable of shifting
information to the right only information to the left only
108. In D register, D stands for ___________ C
A Delay B Decrement
C Data D Decay
109. A register is defined as ___________ D
A The group of latches for storing one B The group of latches for storing n-bit
bit of information of information
C The group of flip-flops suitable for D The group of flip-flops suitable for
storing one bit of information storing binary information
110. The register is a type of ___________ A
A Sequential circuit B Combinational circuit
C CPU D Latches
111. How many types of registers are? C
A 2 B 3
C 4 D 5
112. The main difference between a register and a counter is ___________ A
A A register has no specific sequence B A counter has no specific sequence
of states of states
C A register has capability to store one D A register counts data
bit of information but counter has n-bit
113. A register capable of shifting in both directions with parallel load capabilities is called A
as,
A Universal shift register B Serial to parallel out shift register.
C Shift register. D Parallel-in parallel out register.
114. A master slave RS flip-flop consists of _________. A
A Master RS flip-flop. B D-flip flop
C Uninverter D Flip-flop.
115. Application of shift register, D
A Frequency. B Time delay.
C Pulse width. D Parallel-in parallel out register.
116. How many methods of shifting of data are available? A
A 2 B 3
C 4 D 5
117. In serial shifting method, data shifting occurs ____________ A
A One bit at a time B simultaneously
C Two bit at a time D Four bit at a time
118. A ______ register is the most basic form of a register which stores binary information. B
A Shift. B Buffer
C Universal. D Control buffer.
119. ________ register consists of 3 positive edge triggered D-flip flops D
A Shift B Universal
C Buffer D Control buffer.
120. In Moore models, the output is the function of only A
A Present state. B Input state.
C Next state. D Mid state.
121. In Mealy models outputs are the functions of both. A
A Present state. B Alternate state.
C Next state. D Mid state.
122. __________ are temporary storage devices. C
A Register B Counter
C Flip-flop D Latch.
123. The D-flip flop has _______input. A
A One . B Two
C Three D Four.
124. The race around condition can be overcome by reducing the ________. B
A Time delay. B Pulse width.
C Propagation delay. D Frequency.
125. The phenomenon of interpreting unwanted signals on J and K while clock pulse is high B
is called______.
A Catching. B Ones catching.
C Matching. D Clear.
126. The process of reducing the number of states is called_______. B
A State deduction. B State reduction.
C State assignment. D State unreduction.
127. The two states that generate exactly the same output and the same next state for C
every possible set of inputs are called,
A Redundant. B Different.
C Equivalent. D Compatible.
128. If an input sequence X takes a machine from state Si to Si, then Si is said to be C
________.
A Precedor of Si B Equalizer of Si.
C Successor of Si. D Constant of Si.
129. The machine in which input changes do not affect the output________. A
A Moore machine B Mealy machine
C Combinational machine. D Sequential machine.
130. The time sequence for flip-flop can be enumerated by A
A State table B Map
C Truth table. D graph
131. Latches developed with NOR and NAND gates tends to say in the latched condition D
because of which configuration feature?
A Low input voltages. B Synchronous operation.
C Gate impedance D Cross coupling
132. The state diagram provides the same information as the. D
A Flip-flops provides B Stable table provides
 C Truth table provides D Latches.
133. The output mealy machine is represented as___________. B
A Z(t)= g{s(ts)} B Z(t)= g{s(t)x(t)}
C Z(t)= g{x(t)} D Z(t)= g{s(t)}
134. Which of the following is a correct statement? A
A Moore machine has no accepting B Mealy machine has accepting states
states
C We can convert Mealy to Moore but D Mealy and Moore machine has
not vice versa accepting states
135. The O/P of Moore machine can be represented in the following format: A
A Op(t)=(Op(t)) B Op(t)=(Op(t)i(t))
C Op(t): yi D Op(t): xi
136. The output alphabet can be represented as: B
A B
C D x
137. Which machine requires more number of states for implementing a function? A
A Mealy machine. B Half adder
C Full adder D Decoder.
138. Moore Machine is an application of: B
A Finite automata without input B Finite automata with output
C Non- Finite automata with output D Non- Finite automata
139. For a give Moore Machine, Given Input=101010, thus the output would be of length: A
A |Input|+1 B |Input|
C |Input-1| D Cannot be predicted
140. The total number of states and transitions required to form a moore machine that will A
produce residue mod 3.
A 3 and 6 B 3 and 5
C 2 and 4 D 2 and 5