Conceptual uP1561 Synchronous Buck Controller with 3A VIT LDO General Description ‘The uP1561 is a high performance synchronous buck controller with 3A source/sink VTT LDO for memory systems power. It also provides the buffered low noise reference, The uP1561 has wide operation ranging from 3.0V to 26V for input power and 0.75V~3.0V for memory output voltage. The synchronous buck of the uP1561 adopts constant- on-time PWM scheme that features easy-to-use, low external component count, fast transient response and uasi- constant frequency operation over the operation range or in current mode to support ceramic output capacitors. The 3A source/sink VTT LDO has fast transient response, requiring only two 10UF of ceramic output capacitors. In addition, the LDO supply input is available externally to significantly reduce the total power losses. The uP1561 supports all the sleep state controls, in S3 state (suspend to RAM) VTT jis at high-Z and in S4/S5 (suspend to disk) VDDQ, VTT and VITREF soft off The uP1561 has complete functions including under voltage protection, over current protection, over voltage protection, power-up sequencing, power OK output, and thermal shutdown. The uP1561 is available in VOFN4x4- 24L and WOFN3x3-20L packages. Applications Desktop PCs, Notebooks, and Workstations Microprocessor and Chipset Supplies DDR3/DDR2 Memory Power Supplies SSTL-2 SSTL-18 and HSTL Bus Termination oOooa for Memory Power Solution Features Synchronous Buck Controller (VDDQ) | Wide Input Voltage Range 3.0V to 26V Fast Load Transient Response © Current Mode Option Supports Ceramic Output Capacitors ® Soft-Off in S4/S5 States Ry cow Current Sensing Technique bosom ™ 4.5V (ODR3), 1.8V (DDR2) Fixed Output or Adjustable Output (0.75V to 3.0V) = POK, OVP, and UVP 3ALDO (VT) | 3ASourcelSink Capability = TWo 10uF Ceramic Output Capacitors © Support High Z in $3 and Sof-Off in $4/S5 |= Thermal Shutdown = +20mV Accuracy 1 Reference Voltage (VTTREF) = +20mV Accuracy = LowNoise +10mA Output Ordering Information Order Number | Package Type Remark uP1561PQAG | VOFN4x4-24L uP156100KF | WOFN3G-20L Note: uPI products are compatible with the current IPC/ JEDEC J-STD-020 requirement. They are halogen-tree, RoHS compliant and 100% matte tin (Sn) plating that are suitable for use in SnPb or Pb-free soldering processes. UPI Semiconductor Corp, hitp:/www.upi-semi.com Rey. C00, File Name: uP1561-DS-C0000- micro Conceptual uP1561 [esscansomane Pin Configuration Move Pees ow vier vees ooe| ‘come Po« vr pon vweooser fF g woooms Typical Application Circuit pt z Varna 24 UPI Semiconductor Corp., p:/wvwupi-semi.com 2 Rev. C00, Filo Namo: uPi561-DS-C0000micfo Conceptual uP1561 Functional Pin Description Pin Name _|Pin Function VTTGND __ | Power Ground for the VTT LDO. Positive Tetminal of VTT LDO Sense Feedback. Connect to plus terminal ofthe VTTLDO output VTTSNS capacitors, cND [Negative Terminal of VTT LDO Sense Feedback. Connect to minus terminel of the VTT LDO output capacitor. Discharge Mode Setting. Mope __|No Discharge: Connect this pin to VCCS. Tracking Discharge: Connect this pin to VDDQ. Non Tracking Discharge: Connect this pin to GND. vitrer | VTT Buffered Reference Output. Bypass this pin with a 0.033uF ceramic capacitor to GND. THs pin is capable of sourcing up to 10mA current for external loads. Trans-conductance Amplifier Output. Connect to VCS to disable GM amplifier and use COMP —_| constant on ime mode. Use this pin in combination with the FB pin to compensate the control loop of the converter. NC Not Internally Connected. VDDQ Reference Input for VTT and VTTREF. Power supply for the VTTREF. Discharge current VDDOSNS | sinking terminal for VDDQ Nonetracking discharge. Output voltage feedback input for VDDQ output if VODOSET pin is connected to VCCS or GND. VDDQ Output Voltage Setting. 1.5V fixed voltage: Connect this pin to GND VPDOSET |4'aV fixed voltage: Connect this pin to VCC5 [Adjustable voltage: Connect this pin to center of two resistors voltage divider from VDDQ to GND. 33 $3 Signal Input. Connect this pin o the computer system's SLP_S3 signals This pin companied with $5 switches the IC's operating state from active (S0, $1/S2) to S3 and S4/S5 sleep states. 35. $5 Signal Input. Connect this pin o the computer system's SLP_SS signals This pin companied with $3 switches the IC's operating state ftom active (S0, S1/S2) to S3 and S4/SS sleep states. Ne Not internally Connected. pox _ |YDD@Power OK Indicator. This pinis an open drain output. When VDDQ output voltage is within the target range, itis set to high state vecs _|5¥ Power Supply Input. This pin provides power for intemal circut. Bypass this pin with a 1uF ceramic capacitor to GND. pvecs [Supply voltage for the MOSFET driver. Connect a 5V power source to the PVCS pin. Make sure that both VCS and PVCCS are bypassed with 1uF MLCC capacitors. cs Over Current Protection Setting: Over current trip voltage setting input for R,..., Current sense if connected to VCCS through the voltage setting resistor cS GND | Ver Current Protection Setting GND: Ovor current trip voltage setting input GND for Roy a current sense. UPI Semiconductor Corp,, Aifp/wwwiupe-sami.com Rey. C00, File Namo: uP1561-DS-CO000micfo Conceptual uP1561 Pin Name PGND Functional Pin Description Pin Function Power Ground of MOSFET Gate Driver LGATE Lower Gate Driver Output for Synchronous Buck. Connect this pin to the gate of lower MOSFET. This pin is monitored by the adaptive shoot through protection circuitry to determine when the lower MOSFET has tumed off. PHASE Switch Node for Synchronous Buck. Connect this pin to the source of the upper MOSFET and the drain of the lower MOSFET. This pin is used as the sink for the UGATE driver. This pin is also moritored by the adaptive shoot- 4.5V, POK = High ofl aia Current Sense Sink Current | ap V..> 4.5V, POK = Low a4[s[elw Tiip Current Temperature Co- | 7. [Rog Sense scheme, On the basis of T,= 4500 ppm efficient ome | 2586" _ 7 [fee Overcurrent Protection Wycosoe*Vpanw.ensse) Vucescs * SMV, Veg Comparator Offset Vocun |> 450 ei( 4; ti™ Current Limit Threshold Setting Range Veo |Wvcoses 30 | = | 300} mv POK Comparator POK in from lower x3 | 95 | o7 | % VDDQ POK Threshold Viveosoe POK hysteresis ~[s]-|% POK Sink Current oun VV eon = 25 | 90 | ~ | ma POK Delay Time Troxem [Delay for POK in 80 | 130 | 200 | us Under Voltage Lockout and Logic Threshold \VCC5 UVLO Threshold Vuwecs_|Wake up 37 | 40] 43 | Vv ‘Vottage Hysteresis ~fos}- |v No discharge a7[- [| - |v Mode Threshold Veco Nonstracking discharge - [= forfv |VDDOSET Threshold v 1.5V output 0.15 [028 | 035] v Votage veoaset 4 BV output as | 40 | 45 |v High-level Input Vottage v,_|S3.85 2z[-|[-|v Low-level Input Voltage v,_|83,85 = | = [os|v Hysteresis Voltage Viger _|$3, 85 - [o2|- |v Logic input Leakage Current | View |S3, $5, MODE af-[afa Input Leakage! Bias Curent | Visonaser | VDDOSET a[- [4 [a UPI Semiconductor Corp., p:/wvwupi-semi.com Rev. C00, File Namo: uP1561-DS-C0000 12- micfo PoUeR INTELLECT Conceptual uP1561 Electrical Characteristics Parameter Symbol Test Conditions Min | Typ | Max Units UVP and OVP VDDQ OVP Tip Threshold vy, [OVP detect 115 | 120 | 125) % Voltage OF __|Hysteresis -|s|- % VDDQ OVP Propagation Delay | Tososs ~ (158) - | Output UVP Trip Threshold Vie (NE Setect ~ {7} - | % Hysteresis - | w)- % Output UVP Propagation Delay | Tyron, - | | - Output UVP Enable Delay Toveen = 3000) - | Thermal Shuntdown ‘Shutdown temperature - [10] - | Thermal Shutdown Threshold Toon Hysteresis a eee UPI Semiconductor Corp, hitp:/www.upi-semi.com Rey. C00, File Namo: uP1561-DS-CO000- micro Conceptual uP1561 Typical Operation Characteristics ‘This page is intentionally left blank and will be updated later. UPI Semiconductor Corp., p:/wvwupi-semi.com 14 Rev. C00, File Namo: uP1561-DS-C0000micfo POWER INTELLECT PCB Layout Considerations High speed switching and relatively large peak currents in a synchronous-rectified buck converter make the PCB layout @ very important part of design. Fast current switching from one device to another in a synchronous- rectified buck converter causes voltage spikes across the interconnecting impedances and parasitic circuit elements. The voltage spikes can degrade efficiency and radiate noise that result in overvoltage stress on devices. Careful component placement layout and printed circuit board design minimizes the voltage spikes induced in the converter. Follow the layout guidelines for optimal performance of uP 1561 | Keep the PCB trace PHASE node as short and wide 2s possible, Adda sunbber circuit between PHASE and PGNDto eliminate the high frequency voltage spike at PHASE node. |= Keep sensitive analog circuits such as VDDOSNS, VTTSNS and CS away from high voltage switching node such PHASE, UGATE and LGATE |= Connect VDDQ output to VTTIN with short and wide trace. If other power source is used as VTTIN, @ bypass input capacitor should be placed as close to VTTIN as possible, Conceptual uP1561 Application Information = Please the output capacitor for VTT should close to the pin with short and wide trace to avoid additional ESR and/or ESL of the trace. = Connect VITSNS to the positive of VTT output capacitors with a separate trace. = VDDQSNS can be connected separately from VTTIN. Remember that this sensing potential is the reference voltage of VTTREF. Avoid any noise generative lines. = Negative node of VTT output capacitor(s) and. \VTTREF capacitor should be tied together by avoiding ‘common impedence to the high current path of the VTT source/sink current | GND (Signal GND) pin node represents the reference potential for VTTREF and VTT outputs. Connect GND to negative nodes of VTT capacitor(s), VTTREF capacitor and VDDQ capacitor(s) with care to avoid additional ESR and/or ESL, GND and PGND (power ground) should be connected together at a single point. ™ Connect CS_GND (RGE) to source of rectifying MOSFET using Kevin connection. Avoid common trace for high-current paths such as the MOSFET to the output capacitors or the PGND to the MOSFET trace. In case of Using external current sense resistor, apply the same care and connect it to the positive side (ground side) of the resistor. UPI Semiconductor Corp, hitp:/www.upi-semi.com Rey. C00, File Name: uP1561-DS-C0000f fi micfo Conceptual uP1561 Package Information VOFN-4x4-24L Package coven 240-20 wee youu [ ee a) gj 3 aa | . i say a [- q E|___) 4 Oy ono k 390! 419+] a ad fe o8-030 Bottom View - Exposed Pad 100007 Pin? mark tam a | = | a idooeeasonostt _ Ba ooh vatbee 1 z58 a3 | oa 1 t = joo005——| ee a4 fo2-o30 Recommended Solder Pad Piten and Dimensions Note 1.Package Outline Unit Description’ BSC: Basic. Represents theoretical exact dimension or dimension target MIN: Minimum dimension specified. MAX: Maximum dimension specified. REF: Reference. Represents dimension for reference use only. This value is not a device specification. TYP. Typical. Provided as a general value. This value is not a device specification. 2.Dimensions in Miillimeters. 3.Drawing not to scale. 4.These dimensions do not include mold flash or protrusions. Mold flash or protrusions shell not exceed 0.15mm. UPI Semiconductor Corp., p:/wvwupi-semi.com 76 Rev. C00, File Namo: uP1561-DS-C0000micro Conceptual uP1561 POWER INTELLECT Package Information WOFN-3x3-20L Package p08 —_4 k 20010] ewaset bo Tat fons-e2s Botiom View- Exposed Pad (0i00—_ | a === co — Pin tmark 0800 2 Recommended Solder Pad Pitch and Dimensions Note 1.Package Outline Unit Description: BSC: Basic. Represents theoretical exact dimension or dimension target MIN: Minimum dimension specified. MAX: Maximum dimension specified. REF: Reference. Represents dimension for reference use only. This value is not a device specification. TYP. Typical. Provided as a general value. This value is not a device specification, 2,Dimensions in Miillimeters. 3.Drawing not to scale. 4.These dimensions do not include mold flash or protrusions. Mold flash or protrusions shell not exceed 0.15mm. UPI Semiconductor Corp, hitp:/www.upi-semi.com 7 Rey. C00, File Name: uP1561-DS-C0000