United States Patent (19) (11) 4,281,388

Friend et al. (45) Jul. 28, 1981

(54) TACHOMETER 4,181,883 1/1980 Beeghly et al. .................. 364/565 X
(75) Inventors: Kenneth D. Friend, Cedar Falls; Primary Examiner-Edward J. Wise
David W. Gadtke, Waterloo, both of 57 ABSTRACT
Iowa; Duane H. Ziegler, Colona, Ill.
(73) Assignee: Deere & Company, Moline, Ill. A tachometer for monitoring several functions on an
implement, such as engine, shaft and ground speeds. A
(21) Appl. No.: 55,834 microprocessor receives a-c input signals which vary in
(22 Filed: Jul. 9, 1979 frequency as the shaft or ground speeds change. A time
window synchronized with a rising edge on the desired
51) Int. Cl................................................. G01P 3/48 input signal is provided during which the number of
52 U.S. C. ...................................... 364/565; 73/488; falling edges are counted. A running total weighted
324/162; 324/166 average of a number of successive counts is used to
58) Field of Search ................ 364/565; 324/161, 166, update a digital readout indicating speed. Each new
324/168, 172, 173, 162; 235/92 FQ; 73/488, count is compared with the previous average and, if a
578 sudden speed change occurs, the processor shifts to a
56 References Cited fast update mode in which the new count is used to
immediately update the readout. Programming
U.S. PATENT DOCUMENTS switches are provided for selecting the proper ground
3,968,434 7/1976 Dixon et al. ..................... 364/565 X speed time window for a given tire size and for provid
4,086,532 4/1978 Aronson et al. . ... 324/66 ing a ground speed indication in either kilometers per
4,166,976 9/1979 Ruhnau et al........................ 324/166 hour or miles per hour.
4,167,699 9/1979 Baker ............... ... 324/171
4,179,656 12/1979 Wagner ............................ 364/565 X 53 Claims, 13 Drawing Figures

r w

ACCUMULATOR

PROGRAM
STATUS WORD
U.S. Patent Jul. 28, 1981 Sheet 1 of 12 4,281,388

- - - - - - -- - - --- - - - -- - -

TO RESET
U.S. Patent Jul. 28, 1981 Sheet 2 of 12 4,281,388

- - -/- -------
24O 94

76
 U.S. Patent Jul. 28, 1981 Sheet 4 of 12 4,281,388

V
w

PROGRAM
MEMORY

PROGRAM
STATUS WORD

78 8O
U.S. Patent Jul. 28, 1981 Sheet 5 of 12 4,281,388

POWER
ON 4OO

BLANK THE DISPLAY

CLEAR THE AVERAGE VALUE REGISTER-402

CLEAR THE TIMER/COUNTER REGISTER 493
TURN OFF ENGINE SPEED MONITOR BY 494
SENDING A PULSE ON THE PROG PIN
A/G 4a
INTIALIZE OUTPUT REGISTER POINTER. 405
R2 AND DIGIT SELECT REGISTER R2
TO MOST SIGNIFICANT DIGIT
LOAD FUNCTION SELECT REGISTER 4O6
R7, WITH ENGINE SPEED CODE
SIGNIFY PROGRAM NOT CURRENTLY 497

LOAD THE FOUR DISPLAY REGISTERS

WITH ONES (i.E. ALL SEGMENTS OFF).
CLEAR THE MSB IN THE DISPLAY
REGISTER CORRESPONDING TO THE
FUNCTION SELECTED
INPUT THE FOUR REAR PROGRAMMING 409
SWITCHES (I.E. GROUND SPEED

OAD RAM LOCATIONS 4IO

3OH - (HIGH BYTE)
29 - (LOW BYTE)
WITH INITIAL WINDOW VALUE COR
RESPONDING TO THE SELECTED
PROGRAMMING SWITCHES 4.

CLEAR 9-BIT COUNTER REGISTER CARRY-R5), CLEAR TIMEOUT

REGISTERS RAM 28H-27H), LOAD LAST SAMPLE REGISTER R6
WITH ONES, SIGNIFY WINDOW NOT STARTED (CLR F2), LOAD
WINDOW REGISTERS R3 (HIGH BYTE) AND R4 (LOW BYTE) WITH
VALUE CORRESPONDING TO FUNCTION SELECTED,
(A)
U.S. Patent Jul. 28, 1981 Sheet 6 of 12 4,281,388

508)
SAVE THE ACCUMULATOR
IN REGISTER R2 OF E. TIMER/COUNTER
BLANK THE DISPLAY; INTERRUPT:
IGNIFY PROGRAM NOT IN UPDATE
S
REGISTER BANK ONE
SELECT DIGIT TO BE RE DETERMINE AND STORE FUNCTION
FRESHED (l. E. OUTPUT R2) SELECT INFORMATION IN REGISTER
OUTPUT 7-SEGMENT CODE R7
Ef
R
THAT DIGIT (POINTER CHOOSE INITIAL DGIT SELECT ON
BASIS OF FUNCTION SELECTED.
SET TIMER COUNTER, USED
TO INTERRUPT FROM UP LOAD THE FOUR DISPLAY REGISTERS
WITH ONES (ALL SEGMENTS OFF).
CLEAR THE MSB IN HE DISPLAY
ADJUST RO AND R2 SO REGISTER CORRESPONDING TO THE
THAT NEXT DIGIT WILL BE FUNCTION SELECTED,
52)
TURN OFF ENGINE SPEED MONOR
BY SENDING A PULSE ON THE
INPUT FUNCTION SELECT
SWITCHES (I.E. 4 FRONT PROG PN
PANEL SWITCHES) 5132
JAM THE START ROUTINE ADDRESS
ONTO THE STACK WHEN A RER
NSTRUCTION IS EXECUTED PRO
NEW FUNCTION GRAM JUMPS TO START,
BEEN SELECTED
LOAD SUBROUTINE: THIS INTAZES
NO 55 ALL REGISTERS USED IN SAR
ROUTINE. (SEE DETAILED DESCRIP
DM DISPLAY FOR NIGHT TION IN RESET)
OPERATION (I.E. T=O)
56
WAS RETURN
PROGRAM YES
INTERRUPTED FROM FROM
UPDATE
57
INTERRUPT)
NO
SAMPLE INPUT LINE OF 58
FUNCTION SELECTED
A76, 6A
U.S. Patent Jul. 28, 1981 Sheet 7 of 12 4,281,388

(B)
INC TIME OUT REGISTER
HAS
WINDOW 522
STARTED (I.E. FO=
TIME OUT
REGISTER REACHED
TERMINAL VALUE
523
INPUT SAMPLE
A RISING EDGE CYCLE DELAY

START WINDOW

3 CYCLE DELAY

INPUT SAMPLE
FALLING EDGE
7- CYCLE DELAY

INCREMENT 9-BIT PULSE

COUNTER REGISTER
(CARRY-R5)

DECREMENT 2-BYTE WIN

DOW REGISTER (R3-R4)
528
S
WINDOW FINISHED JYP
(R3 R4=O) UPDATE

A/6, 46.
U.S. Patent Jul. 28, 1981 Sheet 8 of 12 4,281,388

(D)
CLEAR 9-BIT REGISTER 524

UPDATE Y 690

SIGNIFY PROGRAMINUPDATE sol

ENABLE TIMER COUNTER
INTERRUPT

STORE NEW DATA VALUE

N Xn REGISTER, 6O2
RAM 35 H (LOW BYTE)
34H (HIGH BYTE)
PLACE LAST AVERAGE VALUE 6O3
RAM 33H (LOW. BYTE)
32H (HIGH BYTE)
INTO R3 - ACCUMULATOR

TWO'S COMPLEMENT OF 6O4

R3 - ACCUMULATOR

ADD NEW DATA VALUE Xn

TO TWO'S COMPLEMENT OF
AST AVERAGE An
(Xn-An- )

A/6, 4a/
U.S. Patent Jul. 28, 1981 Sheet 9 of 12 4,281,388
(E)
S
NEW DATA

LOAD IMMEDIATE UPDATE

COUNTER RAM 26H WITH
THE NUMBER OF IMMEDIATE
UPDATES DESRED

6
6 IMMEDIATE
UPDATES OCCUR
RED SINCE AST SIGN
FICANTLY DIFFERANT
STORE NEW DATA COUNT
VALUE
VALUE Xn (34H-35H); IN THE
AVERAGE VALUE REGISTER
An (32H-33 H). YES
SUBRACT LAST AVERAGE
MULTIPLY THE NEW DATA FROM LAST TOTAL VALUE
COUNT VALUE Xn BY 4 - Thi - An
(I.E. SHIFT R3-ACC LEFT
2 PLACES) ADD NEW DATA VALUE TO THE
ABOVE RESULT Tn- -An- +Xn
STORE THIS VALUE 4Xn IN
THE TO AL REGISTERS
THIS FORMS NEW TOTAL
Tn (36H-37H). VALUE, STORE THIS IN Tn.
REGS. Th=Tn-i-An- + Xn
DVDE THIS VALUE BY 4 TO
FORM NEW AVERAGE
(Tn-I - Anri + Xh) /4

DETERMINE CORRECT ROUND-OFF, IF

REMANDER IS O.5 ROUND TO LAST
AVERAGE, OTHERWISE ROUND IN THE
CONVENTIONAL MANNER.
STORE THE NEW AVERAGE
VALUE. An=Tn-i-An- + Xn
4.

A/G, 4e
 U.S. Patent Jul. 28, 1981 Sheet 10 of 12 4,281,388

(E) 68 -
CONVERT BINARY TO BCD, INPUT 4 FRONT PANEL
THEN BCD TO 7- SEGMENT FUNCTION SELECT SWITCHES
736
OAD RESULT IN DISPLAY
HAS
REGISTERS YES A NEW
69 FUNCTION BEEN
ESPDM
s--a- 7OO
SSUESTED 737
NO
IS
ENGINE SPEED YES
FUNCTION
NSELECTED
SHOULD THE
DSABLE TIMER COUNTER NO DISPLAY BE DIMMED
p
OAO AST SAMPLE REGIS YES
TURN OFF DISPLAY DIGIT
LOAD WINDOW REGISTER R3
SELECT DRIVE TRANSISTERS
R4 WITH INITIAL WINDOW
HAS
YES WINDOW
CEAR PULSE COUNTER
REGISTER R5, AND TIMEOUT STARED
REGISTER R4 OF BANK 1. NO

SiGNFY WINDOW NOT SME; ENGINE SPEED

STARTED (I.E. CLEAR RI)
BLANK THE DISPLAY
G)

OUTPUT 7-SEGMENT CODE A76, 4f

SELECT NEXT DIGIT TO BE
REFRESHED R2. SELECT
NEXT OUTPUT REGISTER RO
(H)
(ID
OD
(REFER TO
FIG. 4 h)
U.S. Patent Jul. 28, 1981 Sheet 11 of 12 4,281,388

()
G)
IS
NO THIS A
RISING EDS f/G. 66
HAS
YES INPUT TIMED
OUT START WINDOW
8 CYCLE DELAY
3 CYCLE DELAY

() SAMPLE
SIGNAL
ENGINE SPEED -

NO IS THIS

2 CYCLE DELAY
72O
INCREMENT PULSE COUNTER
72
DECREMENT WINDOW
REGISTER R3-R4 -
S 722
YES - WINDOW COMPLETE d
E. R3-R4=O)1
 U.S. Patent Jul. 28, 1981 Sheet 12 of 12 4,281,388
(K) A:
CD 702 7232
LOAD THE ACCUMULATOR (VTOL) LOAD THE COUNT VALUE
WITH THE LOW BYTE OF R5 INTO THE :
THE AVERAGE VALUE ACCUMULATOR
(REFERTO 7O3
FIG. 4f) IS IS
THIS THIS 724.
VALUE LESS VALUE LESS
THAN 28 p (I.E. YES1 THAN IO9p (I.E.
ENGINE SPEED LESS ENGINE SPEED LESS -
THAN 28O THAN 28O 1
RPM) RPM)
No
S 725
THIS
VALUE GREATER VALUE GREATER
THAN 24OP (.E. THAN2O (E ENGINE
ENGINE SPEED PEED GREATER THAN ?
GREATER THAN 24OO RPM?) 1

NO -726
TURN OFF TOLERANCE IN TURN OFF TOLERANCE IN
DICATOR. THIS IS ACCOM DICATOR. THIS IS ACCOM
PLISHED BY SENDING A PLISHED BY SENDING A
PULSE ON THE PROG PN PULSE ON THE PROG, PN
TURN ON TOLERANCE IN
DICATOR. THIS IS ACCOM
PLISHED BY SENDING A
PULSE ON THE READ PIN

706- ENABLE TIMER/countER INTERRUPT

7O7. LOAD SUBROUTINE; NTIALZE REG
ISTERS USED IN THE START ROU
A/6, 4/ INE
7O8 DISABLE TIMER COUNTER INTERRUPT
7O9-SIGNIFY UPDATE ROUTINE COMPLETE
JUMP
TO
START
 4,281,388 2
1
still another object to provide such a tachometer which
TACHOMETER has a relatively sensitive input highly immune to noise.
It is a further object of the present invention to pro
BACKGROUND OF THE INVENTION vide a tachometer with a digital output that is relatively
The present invention relates generally to a speed jitter-free and easy to read.
It is yet another object of the invention to provide a
monitor and more specifically to a digital tachometer.
On certain farm implements it is advantageous to be tachometer for selectively monitoring one of a plurality
able to monitor several operating parameters. On a of functions wherein a correct immediate response is
combine, for example, proper ground speed, header provided when a new function is selected.
shaft speed, cleaning fan speed and engine speed are 10 It is still another object of the present invention to
necessary for efficient removal of the crop from the provide a tachometer which provides a ground speed
field. Such problems as malfunctions, misadjustments, indication and can be quickly and easily adjusted for the
clogging and excessive loading can be quickly detected correct reading in either metric or the U.S. equivalent
by monitoring the various speeds. even for varying tire sizes.
Although numerous digital tachometer devices are 5 A digital tachometer utilizes a microprocessor for
available, heretofore none have been completely satis monitoring several functions, such as combine engine
factory. Some require a separate instrument for each RPM, cleaning fan speed, header backshaft speed, and
function and, as a result, are high in cost and require ground speed. Magnetic pickup devices provide a-c
much panel space at the operator's station. input signals with frequencies proportional to the
Accuracy is a problem with many tachometers. Some 20 speeds to be monitored. An input circuit with a filter
respond well during periods when the speed monitored and Schmitt trigger connected to each pickup device
is steady but have a slow response during acceleration converts the signals to square waves which are fed to a
and deceleration. Averaging techniques are often used microprocessor. The microprocessor selectively con
which do not provide a true indication of speed and 25 verts the square wave signals to ground or shaft speed
which can even, in certain situations, give an indication information to be displayed on a digital display. Time
that speed is increasing when in fact the speed has just windows are provided which to prevent jitter are syn
begun to decrease. If the device is made to respond cronized with a rising edge of the square wave signals,
quickly for accurate readings during periods of acceler
ation or deceleration, the display often is difficult to and a counter counts the number of trailing edges dur
read during operation at steady speeds since small 30 ing a window as an indication of the speed. In a first
changes in the reading will cause constant change in the mode, a running total weighted average of the counts is
least significant digit. To prevent constantly changing output to the display with the latest count receiving the
digits at steady speeds, accuracy is often compromised. most weight to provide a truer output response than
Commonly, magnetic transducers detecting passage with a straight average. If a large change in speed oc
of teeth on a rotating member provide an alternating 35 curs abruptly, the processor automatically changes to a
current input to the device which varies in amplitude fast update mode wherein the latest count rather than an
with the angular velocity of the rotating member. At average is output to the display. Operator switches are
low speeds, problems of noise and sensitivity affect provided to select the function to be monitored, but the
accuracy. Jitter often occurs because circuitry is used engine RPM will automatically be displayed on startup.
which counts the number of cycles or pulses occuring Engine RPM is constantly monitored and a signal is
during a given clock period begun at random. This provided to the operator if engine speed drops below a
random counting can result in different counts for con preselected minimum or increases above a preselected
secutive clock periods even if the speed remains con maximum. Programming switches are also provided for
stant. This causes the least significant digit to change choosing a proper ground speed window for various
constantly, which is annoying to the operator. 45
tire sizes and also for selecting either km/h or mph
Ground speed measurements are usually derived readings without need for a trimming potentiometer or
from the rotational speed of a drive shaft and are af. internal circuit changes. The processor automatically
fected by the size of the tires provided on the imple dims the display by changing the duty cycle of the
ment. If the tire size is changed, the ground speed indi
cated will be inaccurate. To correct for such changes, 50 display drivers when ambient light falls below a prese
lected level.
or alternatively to set the device to read in different
units such as kilometers per hour rather than miles per theThese and other objects, advantages and features of
present invention will become apparent to one
hour, often requires an adjustment of a trimming poten
tiometer while a signal generator connected to the ta skilled in the art from a reading of the following de
tailed description of a preferred embodiment of the
chometer input simulates a signal for a given speed. 55 invention when taken in conjunction with the accompa
SUMMARY OF THE INVENTION nying drawings.
It is, therefore, an object of the present invention to DESCRIPTION OF THE DRAWINGS
provide a digital tachometer which eliminates the afore
mentioned problems. 60 FIGS. 1a, 1b, and 1c together are a detailed schematic
It is another object of the present invention to pro diagram of the device of the present invention.
vide an improved tachometer which monitors several FIG. 2 is a schematical representation of the magnetic
fucntions. It is a further object to provide such a ta transducer for providing an a-c signal having a fre
chometer which utilizes a single microprocessor. quency proportional to speed.
It is yet another object of the present invention to 65 FIG. 3 is a block diagram of the microprocessor
provide a tachometer which provides accurate readings shown in FIG. 1b.
without jitter both at relatively steady speeds and dur FIGS. 4a-4h together are a detailed flowchart for the
ing periods of rapid acceleration or deceleration. It is microprocessor of FIG. 3.
 3
4,281,388
4.
DESCRIPTION OF THE PREFERRED A 64 byte random access memory (RAM) 86 is con
EMBODIMENT nected by busses 88 and 90 to the accumulator 94. The
RAM 86 includes two banks (BANK 0 and BANK 1) of
Referring now to FIG. 1a, there are shown input working registers R0–R7 and R0'-R7". Data can be
circuits 10, 12, 14 and 16, each connected to an output transferred directly between the accumulator and the
20 of a magnetic pickup 22 (FIG. 2) which senses the working registers over bus 88. The remaining memory
passage of teeth 24 on a rotating member. The pickup 22 is addressed indirectly by an address stored in the R0
provides a sine wave to the corresponding input circuit and R1 registers. The working registers R0–R7 can also
having a frequency proportional to the angular velocity be loaded from a program memory 94 via bus 96. The
of the rotating member. Signals to the input circuits 10, 10. memory 94, a read only memory which is mask pro
12, 14 and 16 can correspond, for example, to the engine grammable, is connected through bus 98 to the accumu
RPM, cleaning fan speed, header backshaft speed, and lator, and through bus 100 to the I/O device.
ground speed, respectively, on a self-propelled com Data can be transferred between the accumulator 84
bine. and a timer/counter 102 on a bus 104. The timer/coun
The input circuits 10-16 are identical, each including 15 ter includes an 8-bit register 106. In the preferred em
a low-pass filter 26 and a limiting circuit 28. The filter bodiment, a 6 Mhz crystal oscillator 108 (FIG. 1b) is
has a resistor 30 connected between a pickup output 20 connected to the XTAL pins of the processor and pro
and a terminal 31. A capacitor 32 is connected between vides a frequency reference for the timer/counter.
the terminal 31 and ground. The value of the resistor An 8-bit program status word (PSW) 110 can be
and capacitor are chosen to provide a filter cut-off fre 20 loaded to and from the accumulator 84 via bus 112. One
quency in the middle of the expected signal range for bit is a working register bank switch bit for determining
the corresponding magnetic pickup. The limiting circuit which of the two banks of R0–R7 registers in the RAM
28 includes a pair of diodes 34 connected between the 90 is to be directly addressable by the accumulator.
terminal 31 and ground to clip the input at a positive 25 Another bit is a carry bit for indicating that a previous
and a negative value of about 0.6 volt. The output from operation has resulted in overflow of the accumulator.
a magnetic pickup increases in amplitude as the angular The carry bit of the PSW and an 8-bit register R5 are
velocity of the corresponding rotating member in utilized together to provide a 9-bit register for counting
the number of pulses occuring during a given clock
creases, but the filter 26 and clipping circuit 28 help to period,
maintain a constant level output at the terminal 32. The 30 F0 and as will be described in detail below. Two flags,
F1, are also provided.
filter 26 also eliminates high frequency noise which may For a detailed description of the construction and
be present on the line 20. operation of the microprocessor 74, see MCS-48 TM
A coupling capacitor 36 connects the terminal 31 Family of Single Chip Microcomputers. User’s Manual
with an input 38 of a Schmitt trigger 40. The input 38 available from Intel Corporation.
and a second input 42 to the Schmitt trigger are con 35 The lines 66-72 are connected to the first port 76 of
nected to a reference voltage line 44 by resistors 46 and the microprocessor 74. Connected between the second
48, respectively, and are biased to about a +2 volt level.
The output 50 of the Schmitt trigger is connected via a part 78 and ground are ground-speed programming
resistor 52 to the input 42 to establish the hysteresis switches 116-122 (FIG. 1b). Each of the switches
116-120 is either opened or closed according to a chart
range of the circuit. The output 50 of the Schmitt trig 40 giving switch position for up to 8 different tire sizes
ger 40 is connected through a pull-up resistor 54 to a which can be used on the ground wheel drive system on
reference voltage line 56 maintained at a potential of the implement
about 4 volts. The resistors are chosen so that a positive ther opened orbeing monitored. The switch 122 is ei
closed, depending on whether ground
pulse of about 300 mV. coupled from the terminal 32 to speed is to be read in miles per hour or kilometers per
the input 38 causes the output 50 to switch to the low 45 hour. The four switches 116-122 thus provide ground
level, while a negative pulse of about 300 mv. is re speed calibration function. Upon powering
quired to cause the output to return to the positive level cuit, a 4-bit word is determined by the switchuppositions
the cir
determined by the reference voltage at 56. By setting and a window time for the ground speed function is
the transition points at +300 mV., up to about 600 mV. selected corresponding to the word. If a switch is
of noise can be tolerated on the line 20 at the lower 50 closed,
frequencies and even higher noise levels at higher fre groundedtheandcorresponding line of the port 78 is
the corresponding bit is determined to be
quencies because of the action of the low-pass filter. a logic “0”. If the switch is open, the bit is a logic “1”.
The reference voltages at points 44 and 56 are deter The program in the memory 94 acts as a map and based
mined by a voltage divider including resistors 58, 60, on the word read into the accumulator 84 from the
and 62 connected between a power supply 64 and 55 programming switches, a window value from a look-up
ground. table in the program memory 94 is read into a 2-byte
The input circuits 10-16 convert the signals from the RAM location (R29-R30). The window values are
transducers 22 to constant amplitude square waves at chosen such that each falling edge on the square wave
the outputs 50. The outputs 50 are connected by lines input for the function selected occurring during a win
66, 68, 70 and 72 to a microprocessor 74 which in the 60 dow corresponding to 10 RPM or 0.1 mph (or 0.1
preferred embodiment is a model 8048 microcomputer km/h).
available from Intel Corporation of Santa Clara, Cali
fornia. The microprocessor includes an input/output offAlso connected to the first port 76 are four normally
momentary switches, including a ground speed
(I/O) device 75 (FIG. 3) with input/output lines switch 130, a header backshaft speed switch 132, a fan
grouped in three ports 76, 78 and 80. Data is transferred 65 speed switch 134 and an engine RPM switch 136 for
over bus 82 between the I/O device and an 8-bit accu selecting which of the four input lines 66-72 are to be
mulator 84, which is the central point for most data monitored. The processor constantly reads the switches
transfers within the processor. 130-136 and stores the corresponding function select
 4,281,388
5 6
information in the working registers R7 of the RAM. A approximately 25% of the time when the ambient light
logic “1” appears at each of the four lines from the level is high. Display drivers 208-214 each include a
switches 130-136 unless a switch is depressed to ground Darlington pair input circuit 216 connected to the sec
a line and produce a logic “0”. If two switches are ond port 78 by one of four lines 218C-218F and to a
depressed at the same time, the display 152 will be drive transistor 220 for supplying current in turn to the
blanked. appropriate display digit during the time the corre
Also connected to an input 140 (T1) of the micro sponding display register is being output. If the Voltage
processor 74 is an output line 142 (FIG. 1a) from a light on terminal T1 (input 140) is high, the line 218 for a
detector circuit 144. This circuit 144 includes a photodi particular digit remains high during the entire 25% of
ode 146 connected between the positive and negative 10 the time the display register for that digit is being out
inputs of an operational amplifier 148. The positive put. If the voltage on T1 is low, the time that the line
input is grounded, and feedback is provided between remains high is decreased to 10% so that each digit is
the output line 142 and the negative input via a resistor dimmed. The working register R2 in the RAM carries a
150. When light above a preselected threshold impinges 4-bit word consisting of one logic “1” and three logic
on the diode 146, current flows from the negative to the 5 "O's which are rotated as the program in the memory is
positive terminal causing the output on line 142 to go to advanced providing a logic “1” on the appropriate line
the high or logic “1” level to supply current through 218. The register R0 points to the particular register in
the resistor 150 to the negative input. If the light de the RAM where the 7-segment code is located for each
creases below the threshold, the output goes to the low digit selected. There are the four registers, R3C-R3F,
or logic “1” level. Preferably, the threshold is selected 20 corresponding to the four lines 218C-218F.
so that the output goes low so the T1 input 140 sees a Only 7 bits of each of the 4 display registers
logic “0” at the level of light present at dusk at the R3C-R3F in the RAM are required to produce the
operator's station. The processor continuously multi desired digit from each 7-segment lamp, and the most
plexes a 4-digit incandescent display 152, operating significant bit (MSB) is used to illuminate one of four
each digit at a conventional 25% duty cycle when T1 is 25 lamps 232-238 which indicate the selected function,
at the high level and alternately at a 10% duty cycle engine RPM, fan speed, header backshaft speed and
when T1 is at the low level. The reduction to a 10% ground speed, respectively. The 8th bit of each display
duty cycle is accomplished by checking the level at pin register is therefore a function select bit for the display.
T1 each time a digit is illustrated and automatically For example, if the operator pushes the header back
turning off the digit 40% of the way through its conven 30 shaft switch 132, a logic “0” is provided in the MSB in
tional illumination time if T1 is low. This feature, de the third display register R3D while logic “1's are
scribed in further detail below, dims the display at night present in the MSB in the other display registers. As the
so it is easier to read. A green filter 154 is placed over first two display registers R3F and R3E are output to
the diode 146 which preferably is located near the 4 the display logic 194, lamps 232 and 234 remain dark
digit display, to prevent infrared light from the display 35 since the high level online 230 during this portion of the
from activating the diode at night, for example, as the cycle causes NAND circuit 240 to remain off. When the
operator moves his hand near the display. third display register R3D is read in turn to control the
Terminal 160 (RESET) of the microprocessor 74 is segments of the digit 204, the low level at the MSB of
connected to a capacitor 162 to assure that all circuitry that register causes the NAND gate circuit 240 to
is reset by an internal reset pulse when power is turned 40
on. A reset circuit 164 is also connected to the terminal
switch on, allowing current from the driver circuit 212
to illuminate the header backshaft indicator lamp 236.
160. A voltage divider including resistors 166 and 168 is Because the ground speed function requires a decimal
connected between a first voltage supply V1 (11.6 point between the digits 202 and 204, a decimal point
volts) and ground. The positive input of an operational lamp 242 is provided and is connected in parallel with
amplifier 170 is connected between the resistors, and the 45 the ground speed lamp 238.
negative input is connected to the reference voltage An engine speed warning light or monitor 250 (FIG.
terminal 44 of the input circuits. Normally, the voltage 1b) is connected between the collector of an NPN tran
at the positive input of the amplifier 170 is higher than sistor 252 and the output 251 of the driver 208. The
at the negative input so the output 172 remains high. If collector is also connected to ground through a resistor
the voltage supply level should drop, the output 172 50 254 to establish a small idle current through the light
goes low, causing the processor circuitry to reset pre 250 when the transistor 252 is biased to the off condi
venting false indications resulting from the voltage tion. The base of the transistor is connected through an
drop. A second operational amplifier 174 has its positive input resistor 256 to a selectively activatable oscillator
input connected to the output 172 and its negative input 260 having a low frequency of oscillation. The time
connected to the terminal 44 so that when the output at 55 constant of RC circuits 262 and 264 connected to
172 is low (for example, when the power is first turned NAND gates 268 and 270 is about one second. The base
on to the microprocessor), the output on a line 176 from is also connected to the line 176 which prevents the
the amplifier will be low. When the voltage at 172 ex transistor 252 from turning on until the supply voltage
ceeds the voltage at the terminal 44, the voltage on line has reached a predetermined level and the microproces
176 goes high. 60 sor 74 has been initialized by the RESET. The control
Seven lines 180-192, are connected between the bus input 272 of the oscillator 260 is connected to the output
port 80 and a segment enable circuit. 193 of standard of a reset flip-flop 280 which includes NAND gates 282
7-segment control logic 194 for the 4-digit display 152. and 284. An input 286 of the gate 282 is connected to the
Four 8-bit display registers R3C-R3F in the RAM 86 program pin (PROG) 288 of the microprocessor, and an
corresponding to four display digits 200-206 are each 65 input 289 of the gate 284 is connected to the read pin
loaded with the 7-segment code for the desired readout. (RD) 290. The inputs 286 and 289 are connected
A conventional multiplexing method is used, with each through pullup resistors 292 and 294 to a positive 5-volt
of the four individual display registers being output supply.
 7
4,281,388
8
A pulse from pin 288 (PROG) which drops the volt to the circuit, and the RESET function described above
age at input 286 to ground causes the output 272 of the initiallizes the processor 74. A “RESET' routine 400 is
flip-flop. 280 to go low, diabling the oscillator 260 by begun, and the display 152 is blanked (step 401) by
holding the output of the NAND gate 270 at the high assuring the four driver input lines 218 are low. The
level. A negative pulse from the pin 290 resets the flip average value (A) register R32-R33 and the timer/-
flop so that the output 272 is high, enabling the oscilla counter register 106 are cleared. A pulse output on the
tor 260. The output of the NAND gate 268 is at ground PROG pin 288 (step 404) to assure that the oscillator
level and the transistor 252 is biased off except when the 260 is disabled so the warning lamp 250 does not flash.
oscillator 260 is enabled at which time the lamp 250 will The output register pointer R0 and the digit select regis
flash at the oscillator frequency. The duty cycle of lamp 10
ter R2 in the first bank (BANK 0) of the RAM, are
250 while the base of the transistor 252 is biased above
the base-emitter turn-on voltage is the same as the duty initialized at 405 so that the bit corresponding to the
for the digit 200 (FIG. c) since the lamp is connected to most significant digit 200 is a “1”. The register R2 se
the output 251 of the driver 208. This assures that the lects which one of the digits 200-206 is to be activated
lamp 250 will be dimmed with the rest of the display 152 15 by determining which one of the lines 218 to the digit
at night. In the preferred embodiment, the processor 74 drivers will be high. The register R0 points to one of
constantly monitors the engine speed as well as the four registers R3C-R3F in the RAM 86 containing the
function selected by the switches 130-136 and outputs a 7-segment code for that particular digit. Then at step
pulse on the RD pin 290 to start the oscillator and cause 406 the register R7, which stores a code that corre
the tolerance indicator 250 to flash if engine speed rises 20 sponds to the desired function selected by the switches
above 2400 RPM or drops below 2180 RPM. 130-136, is loaded with the code corresponding to the
Pins 292, 294 and 296 (EA, Vss and TO) of the micro engine speed function which is displayed initially.
processor are grounded. Pins 300-306 (ss, INT, Vcc and When a different function switch is depressed, a new
Vdd) are connected to the positive 5-volt supply. code will be entered into R7.
The data memory of the RAM 86 includes an average 25 During the “RESET' routine a “0” is entered to the
value (A) register R32-R33, an immediate value (X) flag bit F1 at step 407 signifying that the microprocessor
register R34-R35, and a four times average value (Tn) program has not been interrupted from an “UPDATE'
register R36-R37. Also included is a time-out register routine 600 (FIG. 4d) which is used to calculate the
R27-R28 utilized to insure that, when there are no value to be displayed. The four display registers
pulses coming in, the program will not remain in the 30 R3C-R3F are loaded with ones (408) so the segment
“START routine 500 (FIG. 4b, described below) in enable circuit 193 turns off all 7 segments of the digits.
definitely. The function of the registers will become The MSB in one of the display registers R3C-R3F
apparent from the description of operation of the micro corresponding to the function selected (i.e., the engine
processor 74 in conjunction with the flowchart of FIG. RPM on the digit 200) is blanked so that the NAND
4a-4h. gate 240 is turned on to illuminate the lamp 232 during
35
During each window the microprocessor 74 deter the portion of the cycle the line 218F is high, which is
mines the number of pulses occurring on one of the lines determined by the location of the “1” in R2.
66-72 corresponding to the function selected by count During step 409, the four programming switches
ing the number of falling edges. A weighted average of 116-122 are read and a proper time window is selected
the counts obtained during successive windows is pro from the program memory 94 on the basis of the switch
vided. In the preferred embodiment, the average An is 40 positions. The window is chosen such that each pulse
computed according to the following equation: counted during the window corresponds to 0.1 mph (10
An = 3 (X+3X-1+(i)'X-2+()X-3+... ) (Eqn. 1) RPM when shaft speeds are measured). The window
value is loaded into the window register R29-R30 of
where Xn is the immediate value of the pulse count 45 the RAM 86 during step 410. (Register designations are
taken during the nth window. The latest count X re in a hexidecimal rather than a decimal based system.)
ceives the most weight. Normally the average value An The window value actually determines the number of
stored in the average value register R32-RX is con times the processor will run through the “START
verted to 7-segment code which is stored in the four routine (FIG. 4b) which is a predetermined number of
display registers R3C-R3F and utilized to update the 50 instruction cycles (66) no matter which path is taken
display 152. However, the immediate value Xn is first through the routine and therefore is a well-defined time,
compared with the previous average An-1 and, if Xn is subject only to inaccuracies in the crystal oscillator 108.
significantly different than An-1, indicating rapid accel The 9-bit counter register consisting of the register
eration or deceleration, the immediate value X rather R5 and the carry bit is cleared at step 411 so it is ready
than the new average is utilized to update the display 55 to be incremented each time a falling edge occurs on the
152. In the preferred embodiment, if the immediate selected input during a window. The time-out register
count X differs from the last average An-1 by four or R27-R28, which counts the number of times the pro
more counts (i.e., 40 or more RPM), the program calls gram runs through the "START routine without oc
for updating the display 152 with the immediate value currence of a rising edge on one of the input lines 66-72
X. The program will remain in the immediate update 60 selected, is cleared.
mode for six immediate updates before returning to the A working register R6 is loaded with “1's. During
averaging mode. This feature allows the operator to operation the register R6 stores a “1” or a “0” depending
guickly adjust the selected function speed to the desired on whether the selected input was high or low during the
value without delay and overshoot, while at the same last sample. A change from a '1' to a “O'” indicates a
time providing a very accurate, non-jittering display at 65 falling edge occurred on the input, while a change from
relatively steady operating speeds. a "0" to a "1"indicates occurrence of a rising edge.
Referring to the flow chart (FIG. 4a), the operation Since the window is started on a rising edge of the
of the tachometer is as follows. The power is turned on Square wave from the input circuit, loading R6 with
 4,281,388
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"l's assures that a falling edge and a rising edge occur main off. This is accomplished by choosing the initial
before the window is begun after the "RESET" routine digit (step 510) on the basis of the function selected, and
400. when two functions are selected, no initial digit can be
The flag F0 is cleared during the "RESET' routine determined. The display registers R3C-R3F are loaded
to signify that a window has not started. When the with ones (511) so all segments will be blank initially.
rising edge is detected and the window is begun during The MSB is then cleared in the display register corre
the “START' routine 500, a “1” is stored in FO. sponding to the function selected to cause the proper
Working registers R3 and R4 together form a 2-byte one of the indicators 232-238 to be activated. The en
window register which is loaded with a value corre gine speed monitor 250 is turned off at step 512 by
sponding to the function selected (i.e., engine RPM) 10 disabling the oscillator 260 with a pulse from the PROG
which determines the number of cycles through the pin 288 (FIG. 1b). An immediate response is provided
"START" routine during a window, thereby establish when a new function is selected, and a correct value is
ing the time of a window. quickly shown on the display, eliminating problems of
The "START" routine 500 (FIG. 4b) has two func false readings common with prior art devices when the
tions. The first is the timer/counter interrupt handler. 15 function is changed.
When program operation is in the “UPDATE" routine The block in the flow chart indicated at step 513
600 (FIG. 4d) wherein the data is prepared for readout assures that if the program was interrupted during the
to the display 152, program flow is interrupted periodi "UPDATE' routine and a new function was selected
cally by the timer/counter 102 in order to continuously by the operator, the program will not return to “UP
multiplex the display and examine the function select 20 DATE' during a RETURN instruction but will instead
switches 130-136. The second function of the go to the "START" routine address jammed onto a
'START routine (when entered as a normal routine) is stack location of the RAM 86. Only the RETURN
to set up a window time corresponding to the function instruction (RETR) can reset an interrupt request flip
selected and then count the number of falling edges flop in the microprocessor 74 so that the program does
within this window. 25 not return to the "UPDATE' routine. The instructions
At step 501 the value in the accumulator 84 is stored are fully described in the aforementioned User's Man
in a working register R2 in the second bank (BANK1) ual. When a new function has been selected, all the
so that if the program was interrupted from the "UP registers are initialized (514) in a similar manner as that
DATE' routine (600) to examine the switches 130-130 described above for the “RESET routine 400, and the
and multiplex the display 152, the accumulator value 30 “START routine is begun.
would be saved for when the program returns to the If during the next pass through the “START loop
"UPDATE' routine to finish the calculation or the like (FIG. 4b) no new function is indicated at step 506, the
in progress at the time of the interrupt. pin 140. (T1) is checked (step 515). If T1 is “0”, indicat
The digit select register R2 is then output at step 502 ing low ambient light level at the photodiode 146 (FIG.
to the lines 218C-218F so that the line with the logic 35 1a), the display 152 is dimmed by reducing the duty
"1' level turns on the appropriate one of the digit driv cycle of each of the drivers 208-214 from 25% to 10%.
ers 208-214. At the same time, the pointer register R0 The pin T1 is checked at a point in time approximately
causes the corresponding one of the four display regis 40% through the instruction cycles of the "START
ters R3C-R3F to output the 7-segment code for that loop. If T1 is “0”, the driver for the digit being re
digit. freshed during the loop is turned off during the remain
At step 503 the timer/counter register 106 (FIG. 3) is ing 60% of the instruction cycles. If T1 is "l', the digit
set to a preselected value so that after the program is in driver remains on for the entire time it takes to complete
the "UPDATE' routine 600 the timer/counter 102 the loop, which in the preferred embodiment is 165.0
causes the program to return to the “START' routine microseconds (2.5 microseconds per instruction).
periodically. In other words, the setting of the timer/- 45 If the program was interrupted by the timer/counter
counter assures that scanning of the function select while in the “UPDATE' routine 600, indicated by a
Switches and display occur regularly. “1” in the F1 flag checked at step 516, the program will
After one of the digits 200-206. (FIG.1c) is refreshed, return to finish the “UPDATE' routine 600 (517). If the
the contents of the registers R0 and R2 are adjusted F1 flag contains a “0”, the "START loop continues
(504) so that the next time through the “START rou SO with the square wave from one of the lines 66-72 corre
tine the next digit on the display 152 will be refreshed. sponding to the function selected being sampled at step
This is accomplished by simply rotating the contents of 518. Next, the F0 flag is checked to see if a window has
the registers one location. Therefore, “1” will appear on begun in a previous pass through the "START' loop
the next line 218 and "O's on the other three lines so the (step 519, FIG. 4c). If F1 is a “0” indicating the window
next digit driver for the display 152 will be activated, 55 has not yet started, the register R6 is checked at step 520
and the next display register will output the proper to see if the input sampled a rising edge (i.e., a transis
7-segment code for that digit to the circuit 193. tion from a “0” to a '1' in the R6 register). If there is a
The input function select switches 130-136 are rising edge, the window is begun (521) and a '1' is
scanned each time through the "START" loop at step stored in the FO flag. If no rising edge is detected, the
505, and if a new function has been selected (506), the 60 time out register R27-R28 is incremented (522) and, if
timer/counter interrupt function is disabled (508), a “0” after a preselected number of passes through the
is placed in the flag F1 and the display 152 is blanked. “START" routine no rising edge is detected (523), the
This assures that the information in “UPDATE' relat 9-bit count register (R5--the carry bit) is cleared at step
ing to the previous function selected will not be dis 524 (FIG. 4d). In other words, if no rising edge is de
played. The working register R7 then receives a new 65 tected after a preselected time, the processor assumes
code from the memory 94 corresponding to the func that nothing is happening at the input line selected and
tion selected at step 509. If two or more of the switches clears the 9-bit falling edge counting register so that a
130-136 are depressed, the indicators 232-238 will re zero value is supplied to the immediate value (X) regis
 4,281,388
11 2
ter R34-R35 during the “UPDATE routine 600. When computed by first subtracting the previous average
a rising edge is detected at 520 and the window is begun value A-1 in the register R32-R33 from the value in
(521), the program makes a number of passes through the four times average value (T) register R36-R37 at
the "START" loop, each time incrementing the 9-bit step 612:
register at step 526 if a falling edge is detected on the
square wave input. Each time through the loop the (Tn-1)-(An-1)=3(An-1) Eqn. 2
2-byte window register R3-R4 is decremented at step
527 until the window is finished at 528 (R3-R4=0), at The new data value Xn is added and the result is stored
which time the program jumps (529) to the "UP in the T register at steps 613 and 614:
DATE’ routine 600, 10
Delays 530, 531 and 532 are provided in the various T= (T-1)-(An-1)--X=3(An-1)--Xn Eqn. 3
paths in the “START routine 500 so that regardless of
the path taken, the number of instruction cycles, and The T value is then divided by four, rounded off and
therefore the time elapsed, will be the same for each stored in the average value (A) register R32-R33 at
pass through the loop. In the preferred embodiment 15 steps 615-617:
there are 66 instruction cycles in the "START' loop, An=X-3(An-1) Eqn. 4
and one pass takes 165.0 microseconds. Timing the
windows by counting the number of times through the
“START' loop is more accurate than, for example, Since An-1 = DX 1 + 3(An-2):
performing a timer interrupt since it is possible to inter 20
rupt on either a one- or a two-cycle instruction, provid An = Xn + Xn-1 + 3(An-2) (Eqn. 5)
ing a one-cycle time uncertainty as to the actual length = X -- i(x,-1) + 3/4 (An-2)]
of the window. Syncronizing the start of a window with Carrying this out for n samples or windows, Equation 1
a rising edge of the square wave and counting falling
edges eliminates the jitter in the least significant digit of 25 is obtained. The new data value X is averaged with the
the display 152 that would occur if a window was previous values, but the weight given each previous
begun at random. sample is less than that given a subsequent sample. More
The “UPDATE' routine 600 (FIG. 4d-4f) is entered than just a few of the past data values are used in the
from the “START routine with a new speed value calculation, yielding a smoothly changing, easily read
CX) which is compared with the last average speed 30 able display, while weighting the latest pulse count Xn
value (An-1). If |Xn-An-1s 4, corresponding to a the heaviest provides a more accurate representation of
change of at least 40 RPM, the new value is stored in speed.
the average value (A) register R32-R33. If X-An-l. After the value A is determined at step 608 or 617, it
1 <4, the new average is calculated according to equa is converted to a 7-segment code at step 618 (FIG. 4f)
tion 1 above and is converted from binary to binary 35 using a standard routine well known to those skilled in
coded decimal, and then to 7-segment code which is the art and stored in the display registers R3C-R3F.
stored in the display registers R3C-R3F read during the After the “UPDATE' routine 600 is complete, an
“START' routine 500. engine speed monitor rountine 700, ESPDM (FIG.
Once in the “UPDATE" routine 600, the flag F1 is 4f-h), is initiated to activate the engine speed warning
loaded with a '1' which indicates return to the routine 40 lamp 250 (FIG. b) if engine speed drops below or rises
600 from step 516 of the “START routine is necessary above preselected limits. If engine speed is the function
after a timer/counter interrupt. The timer/counter in selected (701), the accumulator 84 is loaded with the
terrupt is enabled at step 601 so that the function average value An at step 702. The value in the accumu
switches 130-136 will be scanned and the display multi lator is compared with the high and low limit values at
plexed regularly. At step 602 the new data value X, 45 703 and 704 (FIG. 4 h). If engine speed is within the
which is the binary representation of the number of range of the values, control is returned to the
falling edges counted during a window in the 9-bit reg “START routine 500 (FIG. 4b). Prior to returning, a
ister, is stored in the new data value register R34-R35. pulse is sent on the PROG pin to assure that the indica
A two's compliment of the binary value of the last aver tor 250 is off (705). The timer/counter interrupt is en
age value An-1 is taken and added to the value X 50 abled at 706 to assure constant scanning and multiplex
(steps 603-605), which is equivalent to subtracting ing, and the registers are initialized at 707 as in step 514
An-1 from X. If the absolute value of the difference described above. The interrupt is then disabled at 708
between the new data value Xn and the last average and the flag F1 is set to "O' to signify that the program
value is 4 or more (606), an immediate update counter in is no longer in the “UPDATE' routine (step 709). If the
the RAM, R26 is loaded at step 607 with the number of 55 engine speed is not within the range, the indicator 250 is
immediate updates desired, which in the preferred em turned on at step 710 by sending a pulse on the READ
bodiment is six. That is, once the difference exceeds the pin 290 described above.
preselected value indicating a sudden increase or de When a function other than engine speed has been
crease in speed, the processor will perform six immedi selected, the “ESPDM' routine 700 counts the number
ate updates in which the new data value Xn is entered 60 of falling edges on the engine speed signal on the line 66
directly into the average value (A) register R32-R33 at for a single window (FIG. 4f 4g) in a manner generally
step 608 without averaging in the previous counts. T identical to that used with the "START' routine 500,
value is calculated and stored at steps 609-610. After except the time of the window is cut in half to minimize
the sixth immediate update after the sudden change the time required for the “ESPDM” routine. Therefore
occurred (611), an average An is again computed and 65 each pulse counted on the line 66 represents 20 RPM
stored in register R32-R33 at steps 612-617. instead of 10. The count is stored in the R5 register at
When the "UPDATE' routine is not in an immediate step 720 (FIG. 4g) and after the window is complete
update mode, a weighted average according to eqn. 1 is (721-722) is compared with the preselected limits at
 4,281,388
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steps 723-725 to provide a pulse on the READ pin if termined period of time is synchronized with a rising
engine speed is not within the desired range. If engine edge.
speed is within the range (725), control is returned to 7. The device as set forth in claim 1 further compris
the "START' routine as described above. If no rising ing means for adjusting the response of the second
edge is detected on the engine speed signal after a pre 2S
determined time (730, FIG. 4g), the lamp 250 is flashed. 8. A speed measuring device comprising;
The “ESPDM” routine 700 allows the engine speed means for providing an a-c electrical signal having a
to be constantly monitored to control the warning lamp frequency proportional to speed,
250 regardless of the function selected by the switches means for establishing a succession of clock periods,
130-136. It should be noted that the pulse count pro 10 means for counting the number of electrical signal
vided by the “ESPDM” routine in the register R5 is cycles occurring during a clock period and provid
not used to update the display 152 but merely controls ing a digital signal indicative thereof;
the lamp 250. The display, 152 is multiplexed and the means for weighting a plurality of the digital signals
function switches are scanned at steps 732-737 of the and providing a weighted average signal there
'ESPDM' rountine. 15 from,
Having fully described the preferred embodiment, it display means selectively responsive to the digital
will be apparent that many modifications and variations signal or the weighted average signal for providing
may be effected without departing from the scope of the an indication of the speed,
novel concepts of this invention. Although reference is means for comparing the weighted average signal
made to a specific microprocessor and flow chart, it will 20
with the most recent digital signal and selecting the
be apparent to one skilled in the art that numerous pro display means to be responsive to the weighted
gramming methods and techniques may be used without average signal including the most recent digital
departing from the scope of the claims below. Discrete signal if the most recent digital signal differs by less
components and other forms of large scale integration than a predetermined amount from the compared
rather than a processor may also be used. 25
weighted average, or alternatively selecting the
We claim: display means to be responsive to the most recent
1. In a tachometer: a rotating member, first means for digital signal if it differs by more than the predeter
providing an first electrical signal indicative of the mined amount from the compared weighted aver
speed of rotation of the member, second means respon 30 age.
sive to the first electrical signal for providing successive 9. The device as set forth in claim 8 wherein the
digital signals representative of the speed of rotation means for weighting the digital signals includes means
during successive time intervals, third means for aver for providing the most recent digital signal with the
aging the successive digital signals and providing an most weight.
average value, storage means for storing the average 10. The device as set forth in claim 9 wherein each of
value, fourth means for comparing the most recent 35
digital signal with the average value and updating the the previous digital signals are included in the weighted
stored average with the most recent signal if the differ average signal, each previous digital signal decreasing
ence between the average value and the most recent in weight as a new digital signal is included in the aver
signal is less a predetermined amount or alternately age.
replacing the stored average with the most recent digi 11. An instrument for measuring speed of a device,
comprising: s
tal signal if the difference is greater than or equal to the speed responsive means for providing an a-c signal
predetermined amount, and fifth means responsive. to having a frequency proportional to the speed of the
the contents of the storage means for providing an out device,
put signal indicative of the speed of rotation of the means for providing time windows;
member, 45
2. The device as set forth in claim 1 wherein the third means for providing a speed indicative signal respon
means provides a running total weighted average of the sive to the frequency of the a-c signal during the
digital signals with the latest digital signal getting the time window;
most weight. averaging means for receiving and averaging succes
3. The device as set forth in claim 2 wherein the SO sive speed indicative signals and providing an aver
running total weighted average, An, is computed ac age value signal;
cording to the following equation: display register means for selectively receiving the
average value signal or the speed indicative signal;
means for comparing the average value signal with
55 the most recent speed indicative signal and trans
where Xn is the nth digital signal. mitting said most recent speed indicative signal to
4. The device as set forth in claim 1 wherein the first the averaging means for providing an updated
means provides an electrical signal with pulses occur average value signal to the display register means if
ring at a rate depending on the speed of rotation having said average value and most recent speed indicative
rising and falling edges, and wherein the second means 60 signals differ by less than a predetermined amount
includes counter means operating a predetermined per or, alternately, if said average value and most re
iod of time for counting at least the number of either cent speed indicative signals differ by more than
rising or falling edges occurring in said period of time. the predetermined amount, entering said most re
5. The device as set forth in claim 4 wherein the cent speed indicative signal into the display register
beginning of the predetermined period of time is syn 65 means; and
chronized with one of the edges. indicator means responsive to the contents of the
6. The device as set forth in claim 5 wherein the display register means for providing an indication
counter means counts only falling edges, and the prede of the speed of the device.
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15 16
12. The instrument as set forth, in claim 11 wherein display means selectively responsive to a digital
the instrument includes a processor having program signal or an average value signal for providing a
memory means for storing program instructions and speed indication therefrom, and
executing the instructions at a predetermined rate, and means for comparing the average value signal and
wherein the means for providing time windows in the latest speed signal provided during the most
cludes counter means for providing a count representa recent timing window and selecting the display
tive of the number of instructions executed. means to be responsive to said latest speed signal
13. The instrument as set forth in claim 12 wherein if the difference between said latest speed signal
the program memory means includes a pulse counting and the average value signal is above a prese
routine, and the time windows are provided by execut O lected value, or the average value signal if the
ing the routine a preselected number of times. difference is below the preselected value.
14. The instrument as set forth in claim 11 further 25. The instrument as set forth in claim 24 wherein
comprising programmable switch means for adjusting the processor further comprises means for preventing
the length of the time window. the display means responding to a speed or average
15. The instrument as set forth in claim 11 wherein 15 value signal for a previously monitored first signal upon
the speed responsive means comprises an a-c signal selection of another of the first signals to be monitored.
generator responsive to the movement of the device, 26. The instrument as set forth in claim 24 further
and a square wave generator connected to the a-c signal including means for preventing a speed indication by
generator. the display means when a new first signal is selected for
16. The instrument as set forth in claim 15 further 20 monitoring until a speed signal for the newly selected
comprising a low pass filter connecting the signal gener first signal is provided.
ator and the square wave generator. 27. The instrument as set forth in claim 24 wherein
17. The instrument as set forth in claim 15 or 16 the processor means further comprises second means
wherein the square wave generator comprises a Schmitt for constantly monitoring one of the first signals regard
trigger having two stable states. 25 less of the first signal selected.
18. The instrument as set forth in claim 17 wherein 28. The instrument as set forth in claim 27 further
the Schmitt trigger is triggered between its two stable comprising means for providing a warning signal when
states by alternate positive and negative pulses of gener the speed indicated by the constantly monitored first
ally equal amplitude so that noise immunity of the trig signal exceeds or falls below a preselected range of
ger is approximately equal to at least twice said ampli 30 speeds.
tude. 29. The instrument as set forth in claim 24 wherein
19. The instrument as set forth in claim 18 further the display means includes a visual readout having
comprising a clipping circuit for limiting the signal driven light emitting elements, and means for driving
amplitude to the trigger. the elements at a first duty cycle when the ambient light
20. The instrument as set forth in claim 19 wherein 35 level is above a preselected level and at a second duty
the clipping circuit limits the signal amplitude to the cycle less than the first when the ambient light level is
trigger to about E0.6 volts and wherein the Schmitt below the preselected light level.
trigger is triggered between its two stable states by 30. The instrument as set forth in claim 29 wherein
alternate positive and negative pulses of approximately the visual readout comprises a digital display with n
0.3 volts. digits, and wherein the processor includes means for
21. The instrument as set forth in claim 15 wherein illuminating the digits at a duty cycle of approximately
the means for providing a speed indicative signal com 100/n percent when the ambient light is above the pre
prises counting means responsive to the leading and selected level.
trailing edges of the square wave generated by the 31. The instrument as set forth in claim 29 wherein
Square wave generator. 45 the processor includes means for executing a plurality
22. The instrument as set forth in claim 21 wherein of program instructions at a preselected rate including a
the means for providing time windows includes means routine for controlling the means for driving the light
for detecting a rising edge, and means for counting the emitting elements, wherein each element is driven dur
number of falling edges occurring after a rising edge ing a first preselected number of instructions of the
and during a time window. 50 routine if the ambient light is above the preselected
23. The instrument as set forth in claim 22 wherein level and during a second preselected number less than
the time window is syncronized with a rising edge. the first if the ambient light is below the preselected
24. An instrument for determining the speed of sev level.
eral devices, comprising: 32. In a speed measuring device including a speed
first means for sensing movement and providing a 55 sensor for providing an input signal indicative of the
plurality of first electrical signals indicative of the speed to be measured, means responsive to the input
speeds of the devices; signal for providing speed signals during successive
processor means having a plurality of inputs con time intervals, and display means responsive to the
nected to the first means for selectively monitoring speed signals for providing an indication of the mea
one of the first signals, said processor means further 60 sured speed, the improvement comprising:
including: means for providing a running total weighted aver
timing means for providing timing windows, age, An of successive speed signals according to the
means responsive to the selected first signal for equation:
providing speed signals indicative of the speed of
the device corresponding to the selected first 65
signal during the timing window,
means for averaging a plurality of the speed signals where Xn is the speed signal during the most recent
and providing an average value signal, time interval, n, means for comparing the most
 17
4,281,388
18
recent speed signal Xn with the previous running an average count per time interval during a plural
total weighted average An-1, and wherein the ity of time intervals,
display means is responsive to the average An when acceleration responsive means for determining if ac
the difference between X and and An-1 is less than celeration of the moving member exceeds a prese
a preselected value and to the signal Xn when the 5 lected limit or is less than the preselected limit,
difference is greater than the preselected value. display means automatically responsive to the count
33. In a speed measuring device including a speed of the counter means when the acceleration ex
sensor for providing an input signal indicative of the ceeds the preselected limit and to the average value
speed to be measured, means responsive to the input signal when the acceleration is less than the prese
signal for providing speed signals during successive 10 lected limit for providing an indication of the speed
time intervals, and display means responsive to the of the member.
speed signals for providing an indication of the mea 39. The device as set forth in claim 38 wherein the
sured speed, the improvement comprising: acceleration responsive means comprises means for
comparing the count of the counter means during one of
means for providing a running total weighted aver 15 the time intervals with the average value signal.
age, An, of successive signals according to the 40. A speed measuring device comprising:
equation: first means for providing speed signals representative
of the speed to be measured;
20
second means responsive to the first means for pro
viding an average value signal representative of the
wherein Xn is the speed signal during the most average value of the speed signals;
recent time interval n, and acceleration responsive third means responsive to the speed signals for pro
means for determining the rate of change of the viding an acceleration indication;
speed, said display means selectively responsive to display means associated with the first, second and
the average An when the rate of change is below a 25 third means selectively responsive to the average
preselected rate and to the speed signal Xn when value signal when the indicated acceleration is
the rate of change is above the preselected rate. below a preselected value and to the speed signals
34. In a speed measuring device including a trans when the indicated acceleration is above the prese
ducer for providing a pulse signal the frequency of 30 lected value for providing an indication of the
which is indicative of the speed to be measured, win speed.
dow generating means for providing time windows, 41. The device as set forth in claim 40 wherein the
counter means for counting the number of pulses occur third means includes means for comparing the average
ring during a time window, and display means respon value signal with the most recent speed signal provided
sive to the count of the counter means for providing an 35 by the first means.
indication of the speed, the improvement comprising: 42. The device as set forth in claims 40 or 41 wherein
memory means for storing a plurality of timing sig the average value is a running total weighted average of
nals each representing a predetermined period of the speed signals and wherein the most recent speed
time; signal given the most weight in the average.
programmable switch means for selecting one of the 40 43. The device as set forth in claim 42 wherein the
timing signals from the memory means; and average value signal (An) is determined according to
wherein said window generating means is responsive the equation:
to the timing signal selected by the programmable
switch means to provide a time window of a length
equal to the period of time represented by the se 45 where Xn is the most recent speed signal.
lected signal. 44. A method of measuring the speed of a device,
35. The device as set forth in claim 34 wherein the including the steps of:
programmable switch means comprises n two-position providing first speed signals indicative of the speed of
switches for providing an n-bit binary word, and
wherein the timing signal is selected from the memory 50 providing an during
the device
average
successive time intervals;
value signal indicative of the
means according to the value of the binary word. average value of the speed of the device;
36. The device as set forth in claim 35 wherein at least determining if acceleration of the device is above or
one switch comprises a units conversion switch for below a preselected level of acceleration;
selectively providing the indication of speed in one of outputting to a user device an indication of the aver
two units of measurement. 55 age value signal if the acceleration is below the
37. The device as set forth in claim 36 wherein the preselected value, or alternatively, outputting to
units of measurement are kilometers per hour and miles the user device an indication of one of the first
per hour. speed signals if the acceleration is above the prese
38. A device for providing a measurement of the lected value.
speed of a moving member, comprising: 60 45. The method as set forth in claim 44 wherein the
signal generator means for providing a pulse signal step of providing an average value signal includes aver
having a pulse rate proportional to the speed of the aging a plurality of the first speed signals.
member, 46. The method as set forth in claim 44 wherein the
clock means for providing successive time intervals, step of determining includes comparing the average
counter means for counting the number of pulses 65 value signal with the most recent speed signal.
occurring during the time intervals, 47. The method as set forth in claims 44 or 46 wherein
means responsive to the count of the counter means the step of providing an average value signal includes
for providing an average value signal indicative of providing a running total weighted average of the first
 4,281,388 20
19
speed signals, with the most recent speed signals given 51. A method for measuring the speed of a device,
the most weight. including the steps of:
48. A methd of measuring the speed of a driven de providing a plurality of clock periods;
vice wherein the speed is a function of both angular providing pulses the frequency of which are depen
velocity of a drive shaft and size of a driven member, dent on the speed of the device;
5 counting
the method including the steps of: the number of pulses occurring during each
providing a plurality of successive clock periods; clock period to provide a first speed signal for each
adjusting the length of the clock periods in accor period;
dance with the size of the driven member; averaging the pulse counts for a plurality of clock
providing pulses the frequency of which is dependent O perids to provide an average speed signal;
on the angular velocity of the drive shaft; comparing the average speed signal with the first
counting the number of pulses occurring during each speed signal;
clock period; and providing a speed indication responsive to the most
providing an indication of the speed from the pulse recent first speed signal if the difference between
COunts.
15 the compared average and first speed signals is
49. The method as set forth in claim 48 wherein the
greater than a preselected limit, or alternatively,
step of adjusting the length of the clock periods includes providing a speed indication responsive to the av
erage speed signal if the difference is less than the
the steps of: preselected limit.
storing a plurality of binary values at locations in a 20 52. The method as set forth in claim 51 wherein the
memory; step of averaging includes providing a running total
selecting a binary value according to driven member weighted average of the pulse counts.
size; 53. The method as set forth in claim 52 wherein the
loading the binary value into a register; and weighted average (An) is provided according to the
decrementing the register during regular intervals of 25 following equation:
time until the register reaches a preselected value.
50. The method as set forth in claim 49 wherein the
step of decrementing includes operating a processor in
cycles at a preselected instruction rate and subtracting where Xn is the most recent k sk
first speed
k
signal.
from the register during each cycle. 30

35

40

45

50

55

60

65
 UNITED STATES PATENT AND TRADEMARK OFFICE
CERTFCATE OF CORRECTION
PATENT NO. : 4, 281,388
O DATED : July 28, 1981
NVENTOR(S) : K. D. Friend, D. W. Gadtke, and D. H. Ziegler
it is certified that error appears in the above-identified patent and that said Letters Patent
is hereby corrected as shown below:
O Column l3, line 28, delete "an" and insert -- a --.
Column l3 line 54, after "l" insert -- + --.
Column 14, line 6, delete. ";" and insert -- : --.
Column l4, line l2, delete ";" and insert -- , --.
Column l6, line l4, after "means" insert -- from --.
Column 17 line 4, delete "and" second occurence.
Column 17 line 16, after "successive" insert -- speed --.
Column l8, line 38, after "signal" insert -- is --.
Column 20, line l0, delete "perids" and insert -- periods --.
signed and escaled this
Sirth Day of April 1982
SEAL

GERALDJ. MOSSINGHOFF
Attesting Officer . Commissioner of Patents and Trademarks