Volume – 11 | Issue – 01

Jan 2022
FIRST BIN
A Newsletter for the
Semiconductor Engineering Community

Contents Dear Customer,

I hope you are off to a great start this New Year!

From the CEO’s Desk
I hope you and your families are staying safe and healthy!

Tessolve Showcase At Tessolve, we are keeping a close watch on the Covid and taking all
necessary precautions to ensure employee safety and ensuring
1. DDR HTOL Strategy revolution uninterrupted support for your project delivery. We are thankful for your
Anirudh Mathur – Manager, Test Engineering support in these challenging times.

I am pleased to inform you that Tessolve is building 2 Test Engineering labs

with world-class equipment in San Jose and Austin, US. The Bay area test
Tessolve Engineering Challenge Contest lab is going to commence operations in March. These test labs will greatly
enhance the existing Test & product engineering capacity and offer
1. An Approach to Improve Trim Accuracy using Delta increased flexibility for silicon debug and bring up local to the U.S. region.
Current Method
We have continued to invest and grow over the last 12 months. With over
Kandhan Rajakumar – Manager, Test Engineering
2500 employees worldwide, we are a unique player in the semiconductor
Baranivarnan P B – Sr. Test Engineer 1, Test Engineering engineering solutions space with end-to-end capabilities in Chip Design,
Test & Product engineering, and Embedded System Design under one roof.
Our Silicon Design team has grown over 30% to a 700 member team and
has successfully taped out several designs in the last 6 months.

We have also commenced our operations in Romania. We look forward to

Editorial Team enhancing Tessolve support for European business needs from our
Romania center. We are further expanding our Asia-Pac presence through
ADVISORY COMMITTEE EDITORIAL SUPPORT setting up offices in the Philippines and Taiwan.
Srinivas Chinamilli Rakesh Rout
Rajakumar D Tessolve joined GlobalFoundries’ Design Enablement Network Program as
a Design Partner to bring advanced design solutions to accelerate
customer product development. The strategic partnership with GF aims to
TECHNICAL COMMITTEE OPERATIONS SUPPORT bring state-of-the-art design solutions across multiple end markets
Vidyut Yagnik Thirumalesh Babu Murthy including automotive, industrial, server, graphics, and mobile platforms.
Srinivasprasad B V
Prashanth Kudva MARKETING I am also happy to announce the partnership with AT&T and DynamoEdge
Sudarshan Sarma HS Tanusree Mathad to provide real-time Chip to Cloud data analytics in the Automotive domain.
Vinayaka L.G Tessolve designed Automotive Gateway, DynamoEdge AI analytics and
Banukumar Murugesan AT&T 5G infrastructure will power this sensor to cloud architecture to
Prasad Mantri improve the user experience and drive near-real-time intelligence with
vehicles. This application will be useful for Autonomous Vehicles,
Connected Cars, First responders, 5G sports entertainment, and a host of
other applications.

This year, Tessolve is recognized among the 10 Best Electronics

Printed and Published on behalf of Companies To Work For In Bangalore. This is the result of the effort we are
Tessolve Semiconductor Pvt. Ltd. putting in making Tessolve a great place to work and learn for our
employees.
Plot # 31, Electronic City,
Phase 2, Bangalore 560 100, I thank you for your support in these challenging times and look forward to
Karnataka, India. creating a greater semiconductor ecosystem.
Tel: +91 80 4181 2626
www.tessolve.com
Your kind enquiries / feedback solicited at,
[email protected] / [email protected]
Best Regards,
Srinivas Chinamilli
Co-Founder & CEO
Tessolve Semiconductor

01
Tessolve Showcase
1. DDR HTOL STRATEGY REVOLUTION Step2: Data Toggles Enhancement

Anirudh Mathur – Manager, Test Engineering • Increase the parallelism between different channels/clusters data
toggles. Design architecture inherently introduces a delay
between the data flow of the multiple channels & clusters. An
increasing number of data burst/toggles reduces the inherent
Abstract delay, in turn reducing the idle%.

With the evolution of high-speed PHYs and their newer architecture, INITIALIZATION 1
following an orthodox validation approach doesn’t guarantee the
desired Quality and Performance evaluation. Thus, an equivalent shift
in the Post Si validation strategy is deployed with adaptive cum MC/PHY INIT 2

innovative validation techniques. This article presents a similar case

study for DDRPHY that observed High degradation in critical DDR Frequency Switch 3
performance parameter post HTOL (High-temperature operating life)
mainly due to limited active DDR clock during stress via conventional
Transfer Interface 4
HTOL Test strategy and how it overcame with Test-case enhancement. Configuration

Introduction Transfer Interface 5

Trigger
High-temperature operating life (HTOL) is a test applied to integrated
circuits (ICs) to determine reliability. This test stresses the IC at an Data Traffic 6
elevated temperature & voltage for a predefined period of time. The IC
is usually monitored under stress and tested at intermediate intervals. Expected v/s Received
7
This reliability stress test is used to trigger potential failure modes and data Check

assess IC lifetime.
Fig2: ATE Test-case
Motivation
Step3: Increasing Active%
On write & read DDR bus paths, high fall out on Eye Width degradation
was reported on HTOL stressed devices with the identical Duty Cycle Loop steps 4–7 shown in Fig2 to increase active% since steps 1 - 3
correction values that were used on the unstressed device (practical contribute mostly towards the idle% in the test case. Several data
scenario). Detailed test-case analysis revealed that DDR Clock was traffic test-loops in the HTOL stress test case should be set to a
toggling for a very limited time during the execution of the entire test maximum possible value to increase test time of steps 4-7 to 75% -
case which couldn’t meet desired Active: Idle ratio as per the practical close to the practical scenario. Steps 1-3 contribute to the remaining
application. 25% (idle) of the total test case. All design parameters were validated
post-test-case enhancement and no issues were seen.
Approach
Types of
Step1: Un-gating DDR clock Approach
Strategy Clock Ac�ve%

Un-gating the clock at the SDR to DDR Latch multiplexer, just before the 1 Test Loop
Limited data length
I/O transmitter ensured that the clock toggles throughout the test case. Default ~3%
approach Latch mux select clock disabled
Clock input to Latch mux disabled
In Fig1, the clock is un-gated at the input of the Latch Mux along with
Maximum possible test loops
the Latch Mux clock that makes sure the clock is toggled at the output Maximum possible data length
Proposed
of the Latch Mux as well, making clock active % equivalent to 75% Approach Latch mux select clock enabled ~75%

which is close to practical application. Clock input to latch mux un-

gated/toggled throughout.

DATA/CLOCK Table1: HTOL Test-case Strategy

Note: Max test loops are as per HTOL tester executable file
allowable limit.

LATCH MUX SELECT Conclusion

CLOCK
This approach helped in avoiding false failures post HTOL stressing. It
is also a better approach providing a close measurement of IC lifetimes
compared to the existing approach of running a functional test case for
Fig1: SDR to DDR Latch mux specific hours.

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Tessolve Engineering
Challenge Contest
1. AN APPROACH TO IMPROVE TRIM
ACCURACY USING DELTA CURRENT METHOD
Kandhan Rajakumar – Manager, Test Engineering
Baranivarnan P B – Sr. Test Engineer 1,
Test Engineering

Abstract
As per the design, the Current sense trimming block is critical which
majorly affects the over-current protection block. Current sense gain
trimming is very sensitive to contact resistance and due to that the gain
Picture 2: CSA gain at I2 shows DUT1 (blue) has
trim code measured by the same DUT at different sites does not match. larger deviation compared to DUT2 & 3 (red & green)
Also, the step size is too low, and it was challenging to measure with a
DC Diff meter even with more sample averaging. However, the use of
the delta current trimming method fixed the deviation on gain trim code
with efficient test time.
Use of Delta current trimming method for
improving trim accuracy:
Issues faced in existing method of trim code
calculation: When DUT is placed at different sites, CS gain output differs due to
varying contact resistance. CS gain output is measured while sinking
Current sense gain trim code had variation device to device, and step with two different currents (I1 and I2) at the default trim code set on CS
size between trim codes were not uniform. This issue was persistent gain trim register. The offset error caused by contact resistance gets
and could not be nullified using existing test method.
canceled out while taking the difference of CS gain output measured at
Root cause analysis: two different currents (as contact resistance remains the same at both
currents). The gain was calculated by dividing differential voltage and
1. Trimmed few devices on ATE and collected data across
delta current. Based on the gain difference from Target, found out the
multiple sites.
number of trim codes that need to be adjusted to achieve the target
2. Current sense (CS) gain trim code had larger deviation when gain. Later obtained the final trim code required for achieving the target
verified on Bench setup. gain and fused the device.
3. Collected data with more devices at different currents (I1, I2)
Example:
4. Based on analysis, it was found that there was always
significant deviation on few devices tested at different sites. Later, With 900mA (I1) of load, the voltage measured at a particular
confirmed that it was mainly due to the contact resistance trim code is V1 (expected). Due to the contact resistance variation
variation and more deviation was observed on CS gain trim code. (Rcontact), the measured voltage will be,

Below picture depicts the data collected on 3 units and it is evident that Vm1= V1 + Voffset (Actual)
DUT1 has larger deviation compared to DUT2 & DUT3 when the CS gain
trim code is measured with two different currents independently. With 700mA (I2) of load, the voltage measured at a particular
trim code is V2 (expected). Due to the contact resistance variation
(Rcontact), the measured voltage will be,

Vm2 = V2 + Voffset (Actual)

Difference of these measured voltages (Vm1 – Vm2) at 2

loads I1 and I2 almost nullifies the Voffset caused by contact
resistance. This makes the trim code to be even across the sites for a
particular device.

To confirm the deviation on trim code, trimmed a few parts and verified
at different sites, using delta current trimming method. The gain trim
code was closer and obtained more accurate measurements. The
below picture depicts the data collected on 3 units where CS gain trim
code matched very closely,

From the volume data analysis on the sweep trim code method, the
trim code sweep method is modified to the interpolation method with a
Picture 1: CSA gain at I1 shows DUT1 (blue) has step size of 4 codes/mV. With this method, the ATE results were
larger deviation compared to DUT2 & 3 (red & green) matching with the Bench results.

03
 Conclusion:
1. With Delta current trimming method, the effect of contact
resistance is nullified. Hence, desired trim code and also stability of
results are achieved by improving the trimming accuracy.

2. Large trimmed samples were verified on bench setup and

confirmed that post-measurement values were within datasheet
specification.

3. This method also improved the test time by avoiding linear

trim code search.

Picture 3: CSA gain after

implement 2-point current trimming

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