Time shared architecture
Ch-9: Book: Dr Shoab
Ch-8,10: Book: Stephen Brown
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Architecture design
• Nyquist Sampling Theorem
• Fully dedicated architecture
– Unfolded architecture
• Time shared architecture
– Folded architecture
– Bit serial architecture
– Digit serial architecture
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Fully dedicated architecture
Example
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Bit serial architecture
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Digit serial architecture
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Sequential circuit
• Outputs depend on the past behavior of the
circuit, as well as on the present values of
inputs
• Also known as Finite state machines (FSM)
• Synchronous Sequential circuit
– a clock signal is used to control the operation of
the sequential circuit
• Asynchronous Sequential circuit
– no clock signal is used
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Sequential circuit realization
• Inputs: W
• Outputs: Z
• States: Q
• Types: Mealy and Moore
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FSM implementation
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Design example- Moore
• 1. The circuit has one input, w, and one output, z.
• 2. All changes in the circuit occur on the positive
edge of a clock signal.
• 3. The output z is equal to 1 if during two
immediately preceding clock cycles the input w
was equal to 1. Otherwise, the value of z is equal
to 0.
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State machine design
• Let the starting state is called state ‘A’. As long as the
input w is 0
• When w becomes equal to 1, the machine move to a
different state ‘B’, keeping output z=0
• When in state B, if w is 0 at the next active clock edge,
the circuit should move back to state A. However, if w =
1 when in state B, the circuit should change to a third
state, C, and it should then generate an output z = 1
• The circuit should remain in state ‘C’ as long as w = 1
and should continue to maintain z = 1.
• When w becomes 0, the machine should move back to
state A
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State diagram
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State table
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Generalized circuit
Present state?
Next state?
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State assignment
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Combinational circuit
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Final implementation
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Timing diagram
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• Verilog code
Moore
FSM
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• Verilog code
Moore
FSM, second version
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Mealy State Model
• Previous specs
– output z =1 in the clock cycle that follows the
detection of the second occurrence of w = 1
• New specs
– z should be equal to 1 in the same clock cycle
when the second occurrence of w = 1 is detected
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State diagram
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State table & Circuit
Verilog
Code
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Verilog code- Mealy
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Verilog code- Mealy
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Timing diagram
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Serial Adder Example
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Serial Adder- Mealy FSM
Next state eq.
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Output eq.
Serial Adder- Mealy FSM
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Serial Adder- Moore FSM
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Serial Adder- Moore FSM
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Counter FSM
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Counter FSM
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One hot encoding
• Uses as many state variables as there are
states in a sequential circuit
• for each state all but one of the state variables
are equal to 0
• Example
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Algorithmic State Machine (ASM)
Charts
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Timing diagram
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State box
• It is equivalent to a node in the state diagram
or a row in the state table.
• The name of the state is indicated outside the
box in the top-left corner
• The Moore-type outputs are listed inside the
box
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Decision box
• A diamond indicates that the stated condition
expression is to be tested and the exit path is
to be chosen accordingly
• The condition expression consists of one or
more inputs to the FSM
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Conditional output box
• An oval denotes the output signals that are of
Mealy type
• These outputs depend on the values of the
state variables and the inputs of the FSM
• The condition that determines whether such
outputs are generated is specified in a
decision box
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Moore/ Mealy ASM charts
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Example: A Bit-Counting Circuit
• pseudo-code
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Pseudo code based ASM chart
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Data-path and control circuits
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Datapath- Bit counting example
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ASM chart- Bit counting example
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Timing diagram
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Simulation results
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Verilog code- Bit counting FSM
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• Verilog
code, Bit
counting
FSM
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• Verilog code,
Bit counting
FSM
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• Verilog
code, Bit
counting
FSM
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• Right to left
shift
register
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Shift-and-Add Multiplier
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ASM chart for multiplier
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• Datapath
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• ASM chart
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Multiplier code
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Multiplier
code
• Control unit
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FSM outputs
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Data-path circuit
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Simulation results for the multiplier
circuit
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Divider
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• ASM
• Divider
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Data path: divider
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• ASM chart,
Control signals
of data-path
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Square-root Approximation
• State machine based design for Euclidean
distance calculation
– Multi-threaded architecture
– Resource optimization
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ASM
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Variable Usage chart
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Register assignment
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Operation usage
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Computation units
• Absolute value unit
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Computation units
• Min/max units
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ASM
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Data-path
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Complete data-path circuit
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