May 2011 Doc ID 13902 Rev 13 1/1093

RM0008
Reference manual
STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx
and STM32F107xx advanced ARM-based 32-bit MCUs
Introduction
This reference manual targets application developers. It provides complete information on
how to use the STM32F101xx, STM32F102xx, STM32F103xx and
STM32F105xx/STM32F107xx microcontroller memory and peripherals. The STM32F101xx,
STM32F102xx, STM32F103xx and STM32F105xx/STM32F107xx will be referred to as
STM32F10xxx throughout the document, unless otherwise specified.
The STM32F10xxx is a family of microcontrollers with different memory sizes, packages and
peripherals.
For ordering information, mechanical and electrical device characteristics please refer to the
low-, medium-, high- and XL-density STM32F101xx and STM32F103xx datasheets, to the
low- and medium-density STM32F102xx datasheets and to the
STM32F105xx/STM32F107xx connectivity line datasheet.
For information on programming, erasing and protection of the internal Flash memory
please refer to:
RM0042, the Flash programming manual for low-, medium- high-density and
connectivity line STM32F10xxx devices
PM0068, the Flash programming manual for XL-density STM32F10xxx devices.
For information on the ARM Cortex-M3 core, please refer to the STM32F10xxx Cortex-
M3 programming manual (PM0056).
Related documents
Available from www.st.com:
STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx/STM32F107xx and
datasheets
STM32F10xxx Cortex-M3 programming manual (PM0056)
STM32F10xxx Flash programming manual (PM0042)
STM32F10xxx XL-density Flash programming manual (PM0068)
www.st.com

Contents RM0008
2/1093 Doc ID 13902 Rev 13
Contents
1 Overview of the manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2 Documentation conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
2.1 List of abbreviations for registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
2.2 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
2.3 Peripheral availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3 Memory and bus architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.1 System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.2 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.3 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.3.1 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.3.2 Bit banding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.3.3 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.4 Boot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
4 CRC calculation unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
4.1 CRC introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
4.2 CRC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
4.3 CRC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.4 CRC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.4.1 Data register (CRC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.4.2 Independent data register (CRC_IDR) . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.4.3 Control register (CRC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
4.4.4 CRC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
5 Power control (PWR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
5.1 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
5.1.1 Independent A/D and D/A converter supply and reference voltage . . . . 66
5.1.2 Battery backup domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
5.1.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
5.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
5.2.1 Power on reset (POR)/power down reset (PDR) . . . . . . . . . . . . . . . . . . 68
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5.2.2 Programmable voltage detector (PVD) . . . . . . . . . . . . . . . . . . . . . . . . . 68
5.3 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
5.3.1 Slowing down system clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
5.3.2 Peripheral clock gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
5.3.3 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
5.3.4 Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
5.3.5 Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
5.3.6 Auto-wakeup (AWU) from low-power mode . . . . . . . . . . . . . . . . . . . . . . 75
5.4 Power control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
5.4.1 Power control register (PWR_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
5.4.2 Power control/status register (PWR_CSR) . . . . . . . . . . . . . . . . . . . . . . 77
5.4.3 PWR register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6 Backup registers (BKP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.1 BKP introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.2 BKP main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.3 BKP functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
6.3.1 Tamper detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
6.3.2 RTC calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
6.4 BKP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.4.1 Backup data register x (BKP_DRx) (x = 1 ..42) . . . . . . . . . . . . . . . . . . . 81
6.4.2 RTC clock calibration register (BKP_RTCCR) . . . . . . . . . . . . . . . . . . . . 81
6.4.3 Backup control register (BKP_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6.4.4 Backup control/status register (BKP_CSR) . . . . . . . . . . . . . . . . . . . . . . 82
6.4.5 BKP register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
7 Low-, medium-, high- and XL-density reset and clock
control (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
7.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
7.1.1 System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
7.1.2 Power reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
7.1.3 Backup domain reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
7.2 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
7.2.1 HSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
7.2.2 HSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
7.2.3 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

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7.2.4 LSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
7.2.5 LSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
7.2.6 System clock (SYSCLK) selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
7.2.7 Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
7.2.8 RTC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
7.2.9 Watchdog clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
7.2.10 Clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
7.3 RCC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
7.3.1 Clock control register (RCC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
7.3.2 Clock configuration register (RCC_CFGR) . . . . . . . . . . . . . . . . . . . . . . 98
7.3.3 Clock interrupt register (RCC_CIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
7.3.4 APB2 peripheral reset register (RCC_APB2RSTR) . . . . . . . . . . . . . . 103
7.3.5 APB1 peripheral reset register (RCC_APB1RSTR) . . . . . . . . . . . . . . 106
7.3.6 AHB peripheral clock enable register (RCC_AHBENR) . . . . . . . . . . . 108
7.3.7 APB2 peripheral clock enable register (RCC_APB2ENR) . . . . . . . . . . 109
7.3.8 APB1 peripheral clock enable register (RCC_APB1ENR) . . . . . . . . . . 111
7.3.9 Backup domain control register (RCC_BDCR) . . . . . . . . . . . . . . . . . . 115
7.3.10 Control/status register (RCC_CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
7.3.11 RCC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
8 Connectivity line devices: reset and clock control (RCC) . . . . . . . . . 120
8.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
8.1.1 System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
8.1.2 Power reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
8.1.3 Backup domain reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
8.2 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
8.2.1 HSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
8.2.2 HSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
8.2.3 PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
8.2.4 LSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
8.2.5 LSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
8.2.6 System clock (SYSCLK) selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
8.2.7 Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
8.2.8 RTC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
8.2.9 Watchdog clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
8.2.10 Clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
8.3 RCC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
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8.3.1 Clock control register (RCC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
8.3.2 Clock configuration register (RCC_CFGR) . . . . . . . . . . . . . . . . . . . . . 131
8.3.3 Clock interrupt register (RCC_CIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
8.3.4 APB2 peripheral reset register (RCC_APB2RSTR) . . . . . . . . . . . . . . 137
8.3.5 APB1 peripheral reset register (RCC_APB1RSTR) . . . . . . . . . . . . . . 138
8.3.6 AHB Peripheral Clock enable register (RCC_AHBENR) . . . . . . . . . . . 141
8.3.7 APB2 peripheral clock enable register (RCC_APB2ENR) . . . . . . . . . . 142
8.3.8 APB1 peripheral clock enable register (RCC_APB1ENR) . . . . . . . . . . 144
8.3.9 Backup domain control register (RCC_BDCR) . . . . . . . . . . . . . . . . . . 146
8.3.10 Control/status register (RCC_CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
8.3.11 AHB peripheral clock reset register (RCC_AHBRSTR) . . . . . . . . . . . . 149
8.3.12 Clock configuration register2 (RCC_CFGR2) . . . . . . . . . . . . . . . . . . . 150
8.3.13 RCC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
9 General-purpose and alternate-function I/Os (GPIOs and AFIOs) . . 154
9.1 GPIO functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
9.1.1 General-purpose I/O (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
9.1.2 Atomic bit set or reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
9.1.3 External interrupt/wakeup lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
9.1.4 Alternate functions (AF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
9.1.5 Software remapping of I/O alternate functions . . . . . . . . . . . . . . . . . . 157
9.1.6 GPIO locking mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
9.1.7 Input configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
9.1.8 Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
9.1.9 Alternate function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
9.1.10 Analog configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
9.1.11 GPIO configurations for device peripherals . . . . . . . . . . . . . . . . . . . . . 161
9.2 GPIO registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
9.2.1 Port configuration register low (GPIOx_CRL) (x=A..G) . . . . . . . . . . . . 166
9.2.2 Port configuration register high (GPIOx_CRH) (x=A..G) . . . . . . . . . . . 167
9.2.3 Port input data register (GPIOx_IDR) (x=A..G) . . . . . . . . . . . . . . . . . . 167
9.2.4 Port output data register (GPIOx_ODR) (x=A..G) . . . . . . . . . . . . . . . . 168
9.2.5 Port bit set/reset register (GPIOx_BSRR) (x=A..G) . . . . . . . . . . . . . . . 168
9.2.6 Port bit reset register (GPIOx_BRR) (x=A..G) . . . . . . . . . . . . . . . . . . . 169
9.2.7 Port configuration lock register (GPIOx_LCKR) (x=A..G) . . . . . . . . . . 169
9.3 Alternate function I/O and debug configuration (AFIO) . . . . . . . . . . . . . 170
9.3.1 Using OSC32_IN/OSC32_OUT pins as GPIO ports PC14/PC15 . . . . 170

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9.3.2 Using OSC_IN/OSC_OUT pins as GPIO ports PD0/PD1 . . . . . . . . . . 170
9.3.3 CAN1 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
9.3.4 CAN2 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
9.3.5 JTAG/SWD alternate function remapping . . . . . . . . . . . . . . . . . . . . . . 171
9.3.6 ADC alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
9.3.7 Timer alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
9.3.8 USART alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . 175
9.3.9 I2C1 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
9.3.10 SPI1 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
9.3.11 SPI3/I2S3 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . 176
9.3.12 Ethernet alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . 176
9.4 AFIO registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
9.4.1 Event control register (AFIO_EVCR) . . . . . . . . . . . . . . . . . . . . . . . . . . 178
9.4.2 AF remap and debug I/O configuration register (AFIO_MAPR) . . . . . . 179
9.4.3 External interrupt configuration register 1 (AFIO_EXTICR1) . . . . . . . . 185
9.4.4 External interrupt configuration register 2 (AFIO_EXTICR2) . . . . . . . . 185
9.4.5 External interrupt configuration register 3 (AFIO_EXTICR3) . . . . . . . . 186
9.4.6 External interrupt configuration register 4 (AFIO_EXTICR4) . . . . . . . . 186
9.4.7 AF remap and debug I/O configuration register2 (AFIO_MAPR2) . . . . 187
9.5 GPIO and AFIO register maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
10 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
10.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 190
10.1.1 SysTick calibration value register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
10.1.2 Interrupt and exception vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
10.2 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . 198
10.2.1 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
10.2.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
10.2.3 Wakeup event management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
10.2.4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
10.2.5 External interrupt/event line mapping . . . . . . . . . . . . . . . . . . . . . . . . . 200
10.3 EXTI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
10.3.1 Interrupt mask register (EXTI_IMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
10.3.2 Event mask register (EXTI_EMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
10.3.3 Rising trigger selection register (EXTI_RTSR) . . . . . . . . . . . . . . . . . . 203
10.3.4 Falling trigger selection register (EXTI_FTSR) . . . . . . . . . . . . . . . . . . 203
10.3.5 Software interrupt event register (EXTI_SWIER) . . . . . . . . . . . . . . . . . 204
RM0008 Contents
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10.3.6 Pending register (EXTI_PR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
10.3.7 EXTI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
11 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
11.1 ADC introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
11.2 ADC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
11.3 ADC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
11.3.1 ADC on-off control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
11.3.2 ADC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
11.3.3 Channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
11.3.4 Single conversion mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
11.3.5 Continuous conversion mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
11.3.6 Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
11.3.7 Analog watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
11.3.8 Scan mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
11.3.9 Injected channel management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
11.3.10 Discontinuous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
11.4 Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
11.5 Data alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
11.6 Channel-by-channel programmable sample time . . . . . . . . . . . . . . . . . . 216
11.7 Conversion on external trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
11.8 DMA request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
11.9 Dual ADC mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
11.9.1 Injected simultaneous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
11.9.2 Regular simultaneous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
11.9.3 Fast interleaved mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
11.9.4 Slow interleaved mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
11.9.5 Alternate trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
11.9.6 Independent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
11.9.7 Combined regular/injected simultaneous mode . . . . . . . . . . . . . . . . . . 224
11.9.8 Combined regular simultaneous + alternate trigger mode . . . . . . . . . . 224
11.9.9 Combined injected simultaneous + interleaved . . . . . . . . . . . . . . . . . . 225
11.10 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
11.11 ADC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
11.12 ADC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
11.12.1 ADC status register (ADC_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228

Contents RM0008
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11.12.2 ADC control register 1 (ADC_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
11.12.3 ADC control register 2 (ADC_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
11.12.4 ADC sample time register 1 (ADC_SMPR1) . . . . . . . . . . . . . . . . . . . . 235
11.12.5 ADC sample time register 2 (ADC_SMPR2) . . . . . . . . . . . . . . . . . . . . 236
11.12.6 ADC injected channel data offset register x (ADC_JOFRx)(x=1..4) . . 236
11.12.7 ADC watchdog high threshold register (ADC_HTR) . . . . . . . . . . . . . . 237
11.12.8 ADC watchdog low threshold register (ADC_LTR) . . . . . . . . . . . . . . . 237
11.12.9 ADC regular sequence register 1 (ADC_SQR1) . . . . . . . . . . . . . . . . . 238
11.12.10 ADC regular sequence register 2 (ADC_SQR2) . . . . . . . . . . . . . . . . . 239
11.12.11 ADC regular sequence register 3 (ADC_SQR3) . . . . . . . . . . . . . . . . . 240
11.12.12 ADC injected sequence register (ADC_JSQR) . . . . . . . . . . . . . . . . . . 241
11.12.13 ADC injected data register x (ADC_JDRx) (x= 1..4) . . . . . . . . . . . . . . 242
11.12.14 ADC regular data register (ADC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . 242
11.12.15 ADC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
12 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
12.1 DAC introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
12.2 DAC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
12.3 DAC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
12.3.1 DAC channel enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
12.3.2 DAC output buffer enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
12.3.3 DAC data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
12.3.4 DAC conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
12.3.5 DAC output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
12.3.6 DAC trigger selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
12.3.7 DMA request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
12.3.8 Noise generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
12.3.9 Triangle-wave generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
12.4 Dual DAC channel conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
12.4.1 Independent trigger without wave generation . . . . . . . . . . . . . . . . . . . 252
12.4.2 Independent trigger with same LFSR generation . . . . . . . . . . . . . . . . 253
12.4.3 Independent trigger with different LFSR generation . . . . . . . . . . . . . . 253
12.4.4 Independent trigger with same triangle generation . . . . . . . . . . . . . . . 253
12.4.5 Independent trigger with different triangle generation . . . . . . . . . . . . . 254
12.4.6 Simultaneous software start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
12.4.7 Simultaneous trigger without wave generation . . . . . . . . . . . . . . . . . . 254
12.4.8 Simultaneous trigger with same LFSR generation . . . . . . . . . . . . . . . 255
RM0008 Contents
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12.4.9 Simultaneous trigger with different LFSR generation . . . . . . . . . . . . . 255
12.4.10 Simultaneous trigger with same triangle generation . . . . . . . . . . . . . . 255
12.4.11 Simultaneous trigger with different triangle generation . . . . . . . . . . . . 256
12.5 DAC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
12.5.1 DAC control register (DAC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
12.5.2 DAC software trigger register (DAC_SWTRIGR) . . . . . . . . . . . . . . . . . 259
12.5.3 DAC channel1 12-bit right-aligned data holding register
(DAC_DHR12R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
12.5.4 DAC channel1 12-bit left aligned data holding register
(DAC_DHR12L1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
12.5.5 DAC channel1 8-bit right aligned data holding register
(DAC_DHR8R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
12.5.6 DAC channel2 12-bit right aligned data holding register
(DAC_DHR12R2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
12.5.7 DAC channel2 12-bit left aligned data holding register
(DAC_DHR12L2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
12.5.8 DAC channel2 8-bit right-aligned data holding register
(DAC_DHR8R2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
12.5.9 Dual DAC 12-bit right-aligned data holding register
(DAC_DHR12RD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
12.5.10 DUAL DAC 12-bit left aligned data holding register
(DAC_DHR12LD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
12.5.11 DUAL DAC 8-bit right aligned data holding register
(DAC_DHR8RD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
12.5.12 DAC channel1 data output register (DAC_DOR1) . . . . . . . . . . . . . . . . 263
12.5.13 DAC channel2 data output register (DAC_DOR2) . . . . . . . . . . . . . . . . 263
12.5.14 DAC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
13 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . 265
13.1 DMA introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
13.2 DMA main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
13.3 DMA functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
13.3.1 DMA transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
13.3.2 Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
13.3.3 DMA channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
13.3.4 Programmable data width, data alignment and endians . . . . . . . . . . . 270
13.3.5 Error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
13.3.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
13.3.7 DMA request mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272

Contents RM0008
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13.4 DMA registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
13.4.1 DMA interrupt status register (DMA_ISR) . . . . . . . . . . . . . . . . . . . . . . 275
13.4.2 DMA interrupt flag clear register (DMA_IFCR) . . . . . . . . . . . . . . . . . . 276
13.4.3 DMA channel x configuration register (DMA_CCRx) (x = 1..7,
where x = channel number) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
13.4.4 DMA channel x number of data register (DMA_CNDTRx) (x = 1..7),
where x = channel number) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
13.4.5 DMA channel x peripheral address register (DMA_CPARx) (x = 1..7),
where x = channel number) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
13.4.6 DMA channel x memory address register (DMA_CMARx) (x = 1..7),
where x = channel number) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
13.4.7 DMA register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
14 Advanced-control timers (TIM1&TIM8) . . . . . . . . . . . . . . . . . . . . . . . . 282
14.1 TIM1&TIM8 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
14.2 TIM1&TIM8 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
14.3 TIM1&TIM8 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
14.3.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
14.3.2 Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
14.3.3 Repetition counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
14.3.4 Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
14.3.5 Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
14.3.6 Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
14.3.7 PWM input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
14.3.8 Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
14.3.9 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
14.3.10 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
14.3.11 Complementary outputs and dead-time insertion . . . . . . . . . . . . . . . . 307
14.3.12 Using the break function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
14.3.13 Clearing the OCxREF signal on an external event . . . . . . . . . . . . . . . 311
14.3.14 6-step PWM generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
14.3.15 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
14.3.16 Encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
14.3.17 Timer input XOR function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
14.3.18 Interfacing with Hall sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
14.3.19 TIMx and external trigger synchronization . . . . . . . . . . . . . . . . . . . . . . 319
14.3.20 Timer synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
14.3.21 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
RM0008 Contents
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14.4 TIM1&TIM8 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
14.4.1 TIM1&TIM8 control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . . . 323
14.4.2 TIM1&TIM8 control register 2 (TIMx_CR2) . . . . . . . . . . . . . . . . . . . . . 324
14.4.3 TIM1&TIM8 slave mode control register (TIMx_SMCR) . . . . . . . . . . . 326
14.4.4 TIM1&TIM8 DMA/interrupt enable register (TIMx_DIER) . . . . . . . . . . 328
14.4.5 TIM1&TIM8 status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . . . 330
14.4.6 TIM1&TIM8 event generation register (TIMx_EGR) . . . . . . . . . . . . . . 331
14.4.7 TIM1&TIM8 capture/compare mode register 1 (TIMx_CCMR1) . . . . . 333
14.4.8 TIM1&TIM8 capture/compare mode register 2 (TIMx_CCMR2) . . . . . 336
14.4.9 TIM1&TIM8 capture/compare enable register (TIMx_CCER) . . . . . . . 337
14.4.10 TIM1&TIM8 counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
14.4.11 TIM1&TIM8 prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
14.4.12 TIM1&TIM8 auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . . . . 340
14.4.13 TIM1&TIM8 repetition counter register (TIMx_RCR) . . . . . . . . . . . . . . 341
14.4.14 TIM1&TIM8 capture/compare register 1 (TIMx_CCR1) . . . . . . . . . . . . 341
14.4.15 TIM1&TIM8 capture/compare register 2 (TIMx_CCR2) . . . . . . . . . . . . 342
14.4.16 TIM1&TIM8 capture/compare register 3 (TIMx_CCR3) . . . . . . . . . . . . 342
14.4.17 TIM1&TIM8 capture/compare register 4 (TIMx_CCR4) . . . . . . . . . . . . 343
14.4.18 TIM1&TIM8 break and dead-time register (TIMx_BDTR) . . . . . . . . . . 343
14.4.19 TIM1&TIM8 DMA control register (TIMx_DCR) . . . . . . . . . . . . . . . . . . 345
14.4.20 TIM1&TIM8 DMA address for full transfer (TIMx_DMAR) . . . . . . . . . . 346
14.4.21 TIM1&TIM8 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
15 General-purpose timers (TIM2 to TIM5) . . . . . . . . . . . . . . . . . . . . . . . . 349
15.1 TIM2 to TIM5 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
15.2 TIMx main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
15.3 TIMx functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
15.3.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
15.3.2 Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
15.3.3 Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
15.3.4 Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365
15.3.5 Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
15.3.6 PWM input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
15.3.7 Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
15.3.8 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
15.3.9 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
15.3.10 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373

Contents RM0008
12/1093 Doc ID 13902 Rev 13
15.3.11 Clearing the OCxREF signal on an external event . . . . . . . . . . . . . . . 374
15.3.12 Encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375
15.3.13 Timer input XOR function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377
15.3.14 Timers and external trigger synchronization . . . . . . . . . . . . . . . . . . . . 377
15.3.15 Timer synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
15.3.16 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385
15.4 TIMx2 to TIM5 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386
15.4.1 TIMx control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . 386
15.4.2 TIMx control register 2 (TIMx_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . 388
15.4.3 TIMx slave mode control register (TIMx_SMCR) . . . . . . . . . . . . . . . . . 389
15.4.4 TIMx DMA/Interrupt enable register (TIMx_DIER) . . . . . . . . . . . . . . . . 391
15.4.5 TIMx status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
15.4.6 TIMx event generation register (TIMx_EGR) . . . . . . . . . . . . . . . . . . . . 394
15.4.7 TIMx capture/compare mode register 1 (TIMx_CCMR1) . . . . . . . . . . . 395
15.4.8 TIMx capture/compare mode register 2 (TIMx_CCMR2) . . . . . . . . . . . 398
15.4.9 TIMx capture/compare enable register (TIMx_CCER) . . . . . . . . . . . . . 399
15.4.10 TIMx counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400
15.4.11 TIMx prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
15.4.12 TIMx auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . . . . . . . . . 401
15.4.13 TIMx capture/compare register 1 (TIMx_CCR1) . . . . . . . . . . . . . . . . . 402
15.4.14 TIMx capture/compare register 2 (TIMx_CCR2) . . . . . . . . . . . . . . . . . 402
15.4.15 TIMx capture/compare register 3 (TIMx_CCR3) . . . . . . . . . . . . . . . . . 403
15.4.16 TIMx capture/compare register 4 (TIMx_CCR4) . . . . . . . . . . . . . . . . . 403
15.4.17 TIMx DMA control register (TIMx_DCR) . . . . . . . . . . . . . . . . . . . . . . . 404
15.4.18 TIMx DMA address for full transfer (TIMx_DMAR) . . . . . . . . . . . . . . . 404
15.4.19 TIMx register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405
16 General-purpose timers (TIM9 to TIM14) . . . . . . . . . . . . . . . . . . . . . . . 408
16.1 TIM9 to TIM14 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408
16.2 TIM9 to TIM14 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409
16.2.1 TIM9/TIM12 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409
16.3 TIM10/TIM11 and TIM13/TIM14 main features . . . . . . . . . . . . . . . . . . . 410
16.4 TIM9 to TIM14 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
16.4.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
16.4.2 Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412
16.4.3 Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
16.4.4 Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
RM0008 Contents
Doc ID 13902 Rev 13 13/1093

16.4.5 Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418
16.4.6 PWM input mode (only for TIM9/12) . . . . . . . . . . . . . . . . . . . . . . . . . . 419
16.4.7 Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420
16.4.8 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421
16.4.9 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422
16.4.10 One-pulse mode (only for TIM9/12) . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
16.4.11 TIM9/12 external trigger synchronization . . . . . . . . . . . . . . . . . . . . . . . 424
16.4.12 Timer synchronization (TIM9/12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427
16.4.13 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427
16.5 TIM9 and TIM12 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428
16.5.1 TIM9/12 control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . . . . . . 428
16.5.2 TIM9/12 slave mode control register (TIMx_SMCR) . . . . . . . . . . . . . . 429
16.5.3 TIM9/12 Interrupt enable register (TIMx_DIER) . . . . . . . . . . . . . . . . . 430
16.5.4 TIM9/12 status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 431
16.5.5 TIM9/12 event generation register (TIMx_EGR) . . . . . . . . . . . . . . . . . 432
16.5.6 TIM9/12 capture/compare mode register 1 (TIMx_CCMR1) . . . . . . . . 433
16.5.7 TIM9/12 capture/compare enable register (TIMx_CCER) . . . . . . . . . . 436
16.5.8 TIM9/12 counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437
16.5.9 TIM9/12 prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437
16.5.10 TIM9/12 auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . . . . . . 437
16.5.11 TIM9/12 capture/compare register 1 (TIMx_CCR1) . . . . . . . . . . . . . . 438
16.5.12 TIM9/12 capture/compare register 2 (TIMx_CCR2) . . . . . . . . . . . . . . 438
16.5.13 TIM9/12 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438
16.6 TIM10/11/13/14 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440
16.6.1 TIM10/11/13/14 control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . 440
16.6.2 TIM10/11/13/14 Interrupt enable register (TIMx_DIER) . . . . . . . . . . . 441
16.6.3 TIM10/11/13/14 status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . 441
16.6.4 TIM10/11/13/14 event generation register (TIMx_EGR) . . . . . . . . . . . 442
16.6.5 TIM10/11/13/14 capture/compare mode register 1
(TIMx_CCMR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443
16.6.6 TIM10/11/13/14 capture/compare enable register
(TIMx_CCER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445
16.6.7 TIM10/11/13/14 counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . 446
16.6.8 TIM10/11/13/14 prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . 446
16.6.9 TIM10/11/13/14 auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . 446
16.6.10 TIM10/11/13/14 capture/compare register 1 (TIMx_CCR1) . . . . . . . . 447
16.6.11 TIM10/11/13/14 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447

Contents RM0008
14/1093 Doc ID 13902 Rev 13
17 Basic timers (TIM6&TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449
17.1 TIM6&TIM7 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449
17.2 TIM6&TIM7 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449
17.3 TIM6&TIM7 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450
17.3.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450
17.3.2 Counting mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452
17.3.3 Clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454
17.3.4 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
17.4 TIM6&TIM7 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
17.4.1 TIM6&TIM7 control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . . . 455
17.4.2 TIM6&TIM7 control register 2 (TIMx_CR2) . . . . . . . . . . . . . . . . . . . . . 457
17.4.3 TIM6&TIM7 DMA/Interrupt enable register (TIMx_DIER) . . . . . . . . . . 457
17.4.4 TIM6&TIM7 status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . . . 458
17.4.5 TIM6&TIM7 event generation register (TIMx_EGR) . . . . . . . . . . . . . . 458
17.4.6 TIM6&TIM7 counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458
17.4.7 TIM6&TIM7 prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 459
17.4.8 TIM6&TIM7 auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . . . . 459
17.4.9 TIM6&TIM7 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460
18 Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461
18.1 RTC introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461
18.2 RTC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462
18.3 RTC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463
18.3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463
18.3.2 Resetting RTC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464
18.3.3 Reading RTC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464
18.3.4 Configuring RTC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464
18.3.5 RTC flag assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465
18.4 RTC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466
18.4.1 RTC control register high (RTC_CRH) . . . . . . . . . . . . . . . . . . . . . . . . 466
18.4.2 RTC control register low (RTC_CRL) . . . . . . . . . . . . . . . . . . . . . . . . . . 467
18.4.3 RTC prescaler load register (RTC_PRLH / RTC_PRLL) . . . . . . . . . . . 468
18.4.4 RTC prescaler divider register (RTC_DIVH / RTC_DIVL) . . . . . . . . . . 469
18.4.5 RTC counter register (RTC_CNTH / RTC_CNTL) . . . . . . . . . . . . . . . . 470
18.4.6 RTC alarm register high (RTC_ALRH / RTC_ALRL) . . . . . . . . . . . . . . 471
18.4.7 RTC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472
RM0008 Contents
Doc ID 13902 Rev 13 15/1093

19 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473
19.1 IWDG introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473
19.2 IWDG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473
19.3 IWDG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473
19.3.1 Hardware watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474
19.3.2 Register access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474
19.3.3 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474
19.4 IWDG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475
19.4.1 Key register (IWDG_KR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475
19.4.2 Prescaler register (IWDG_PR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476
19.4.3 Reload register (IWDG_RLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476
19.4.4 Status register (IWDG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477
19.4.5 IWDG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477
20 Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478
20.1 WWDG introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478
20.2 WWDG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478
20.3 WWDG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478
20.4 How to program the watchdog timeout . . . . . . . . . . . . . . . . . . . . . . . . . . 480
20.5 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481
20.6 WWDG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482
20.6.1 Control register (WWDG_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482
20.6.2 Configuration register (WWDG_CFR) . . . . . . . . . . . . . . . . . . . . . . . . . 483
20.6.3 Status register (WWDG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483
20.6.4 WWDG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484
21 Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . 485
21.1 FSMC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485
21.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486
21.3 AHB interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487
21.3.1 Supported memories and transactions . . . . . . . . . . . . . . . . . . . . . . . . 488
21.4 External device address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489
21.4.1 NOR/PSRAM address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489
21.4.2 NAND/PC Card address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490
21.5 NOR Flash/PSRAM controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491

Contents RM0008
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21.5.1 External memory interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492
21.5.2 Supported memories and transactions . . . . . . . . . . . . . . . . . . . . . . . . 494
21.5.3 General timing rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495
21.5.4 NOR Flash/PSRAM controller asynchronous transactions . . . . . . . . . 495
21.5.5 Synchronous burst transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511
21.5.6 NOR/PSRAM controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517
21.6 NAND Flash/PC Card controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522
21.6.1 External memory interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523
21.6.2 NAND Flash / PC Card supported memories and transactions . . . . . . 525
21.6.3 Timing diagrams for NAND and PC Card . . . . . . . . . . . . . . . . . . . . . . 525
21.6.4 NAND Flash operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526
21.6.5 NAND Flash pre-wait functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527
21.6.6 Error correction code computation ECC (NAND Flash) . . . . . . . . . . . . 528
21.6.7 PC Card/CompactFlash operations . . . . . . . . . . . . . . . . . . . . . . . . . . . 528
21.6.8 NAND Flash/PC Card controller registers . . . . . . . . . . . . . . . . . . . . . . 531
21.6.9 FSMC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537
22 Secure digital input/output interface (SDIO) . . . . . . . . . . . . . . . . . . . . 539
22.1 SDIO main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539
22.2 SDIO bus topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540
22.3 SDIO functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542
22.3.1 SDIO adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543
22.3.2 SDIO AHB interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553
22.4 Card functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554
22.4.1 Card identification mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554
22.4.2 Card reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554
22.4.3 Operating voltage range validation . . . . . . . . . . . . . . . . . . . . . . . . . . . 554
22.4.4 Card identification process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555
22.4.5 Block write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556
22.4.6 Block read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556
22.4.7 Stream access, stream write and stream read (MultiMediaCard only) 557
22.4.8 Erase: group erase and sector erase . . . . . . . . . . . . . . . . . . . . . . . . . . 558
22.4.9 Wide bus selection or deselection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559
22.4.10 Protection management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559
22.4.11 Card status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562
22.4.12 SD status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565
22.4.13 SD I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569
RM0008 Contents
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22.4.14 Commands and responses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570
22.5 Response formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573
22.5.1 R1 (normal response command) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574
22.5.2 R1b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574
22.5.3 R2 (CID, CSD register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574
22.5.4 R3 (OCR register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574
22.5.5 R4 (Fast I/O) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575
22.5.6 R4b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575
22.5.7 R5 (interrupt request) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576
22.5.8 R6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576
22.6 SDIO I/O card-specific operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577
22.6.1 SDIO I/O read wait operation by SDIO_D2 signalling . . . . . . . . . . . . . 577
22.6.2 SDIO read wait operation by stopping SDIO_CK . . . . . . . . . . . . . . . . 577
22.6.3 SDIO suspend/resume operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578
22.6.4 SDIO interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578
22.7 CE-ATA specific operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578
22.7.1 Command completion signal disable . . . . . . . . . . . . . . . . . . . . . . . . . . 578
22.7.2 Command completion signal enable . . . . . . . . . . . . . . . . . . . . . . . . . . 578
22.7.3 CE-ATA interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579
22.7.4 Aborting CMD61 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579
22.8 HW flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579
22.9 SDIO registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579
22.9.1 SDIO power control register (SDIO_POWER) . . . . . . . . . . . . . . . . . . . 580
22.9.2 SDI clock control register (SDIO_CLKCR) . . . . . . . . . . . . . . . . . . . . . . 580
22.9.3 SDIO argument register (SDIO_ARG) . . . . . . . . . . . . . . . . . . . . . . . . . 581
22.9.4 SDIO command register (SDIO_CMD) . . . . . . . . . . . . . . . . . . . . . . . . 582
22.9.5 SDIO command response register (SDIO_RESPCMD) . . . . . . . . . . . 583
22.9.6 SDIO response 1..4 register (SDIO_RESPx) . . . . . . . . . . . . . . . . . . . 583
22.9.7 SDIO data timer register (SDIO_DTIMER) . . . . . . . . . . . . . . . . . . . . . 584
22.9.8 SDIO data length register (SDIO_DLEN) . . . . . . . . . . . . . . . . . . . . . . 584
22.9.9 SDIO data control register (SDIO_DCTRL) . . . . . . . . . . . . . . . . . . . . . 585
22.9.10 SDIO data counter register (SDIO_DCOUNT) . . . . . . . . . . . . . . . . . . 586
22.9.11 SDIO status register (SDIO_STA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587
22.9.12 SDIO interrupt clear register (SDIO_ICR) . . . . . . . . . . . . . . . . . . . . . . 588
22.9.13 SDIO mask register (SDIO_MASK) . . . . . . . . . . . . . . . . . . . . . . . . . . . 590
22.9.14 SDIO FIFO counter register (SDIO_FIFOCNT) . . . . . . . . . . . . . . . . . . 592

Contents RM0008
18/1093 Doc ID 13902 Rev 13
22.9.15 SDIO data FIFO register (SDIO_FIFO) . . . . . . . . . . . . . . . . . . . . . . . . 593
22.9.16 SDIO register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593
23 Universal serial bus full-speed device interface (USB) . . . . . . . . . . . 595
23.1 USB introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595
23.2 USB main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595
23.3 USB functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595
23.3.1 Description of USB blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597
23.4 Programming considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598
23.4.1 Generic USB device programming . . . . . . . . . . . . . . . . . . . . . . . . . . . 598
23.4.2 System and power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599
23.4.3 Double-buffered endpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603
23.4.4 Isochronous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607
23.4.5 Suspend/Resume events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608
23.5 USB registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610
23.5.1 Common registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610
23.5.2 Endpoint-specific registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617
23.5.3 Buffer descriptor table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621
23.5.4 USB register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624
24 Controller area network (bxCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626
24.1 bxCAN introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626
24.2 bxCAN main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626
24.3 bxCAN general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627
24.3.1 CAN 2.0B active core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628
24.3.2 Control, status and configuration registers . . . . . . . . . . . . . . . . . . . . . 628
24.3.3 Tx mailboxes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628
24.3.4 Acceptance filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628
24.4 bxCAN operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629
24.4.1 Initialization mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 630
24.4.2 Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 630
24.4.3 Sleep mode (low power) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 630
24.5 Test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 631
24.5.1 Silent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 631
24.5.2 Loop back mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632
24.5.3 Loop back combined with silent mode . . . . . . . . . . . . . . . . . . . . . . . . . 632
RM0008 Contents
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24.6 STM32F10xxx in Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633
24.7 bxCAN functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633
24.7.1 Transmission handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633
24.7.2 Time triggered communication mode . . . . . . . . . . . . . . . . . . . . . . . . . 635
24.7.3 Reception handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635
24.7.4 Identifier filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636
24.7.5 Message storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640
24.7.6 Error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642
24.7.7 Bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642
24.8 bxCAN interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 644
24.9 CAN registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 646
24.9.1 Register access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 646
24.9.2 CAN control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 646
24.9.3 CAN mailbox registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656
24.9.4 CAN filter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 663
24.9.5 bxCAN register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667
25 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 670
25.1 SPI introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 670
25.2 SPI and I
2
S main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671
25.2.1 SPI features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671
25.2.2 I
2
S features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672
25.3 SPI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673
25.3.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673
25.3.2 Configuring the SPI in slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676
25.3.3 Configuring the SPI in master mode . . . . . . . . . . . . . . . . . . . . . . . . . . 678
25.3.4 Configuring the SPI for Simplex communication . . . . . . . . . . . . . . . . . 679
25.3.5 Data transmission and reception procedures . . . . . . . . . . . . . . . . . . . 679
25.3.6 CRC calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686
25.3.7 Status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688
25.3.8 Disabling the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689
25.3.9 SPI communication using DMA (direct memory addressing) . . . . . . . 690
25.3.10 Error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691
25.3.11 SPI interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 692
25.4 I
2
S functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693

Contents RM0008
20/1093 Doc ID 13902 Rev 13
25.4.1 The I
2
S audio protocol is not available in low- and medium-density
devices. This section concerns only high-density, XL-density and
connectivity line devices. I
2
S general description 693
25.4.2 Supported audio protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694
25.4.3 Clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 701
25.4.4 I
2
S master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 706
25.4.5 I
2
S slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 707
25.4.6 Status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 709
25.4.7 Error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 710
25.4.8 I
2
S interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711
25.4.9 DMA features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711
25.5 SPI and I
2
S registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712
25.5.1 SPI control register 1 (SPI_CR1) (not used in I
2
S mode) . . . . . . . . . . 712
25.5.2 SPI control register 2 (SPI_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714
25.5.3 SPI status register (SPI_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 715
25.5.4 SPI data register (SPI_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 716
25.5.5 SPI CRC polynomial register (SPI_CRCPR) (not used in I
2
S
mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 716
25.5.6 SPI RX CRC register (SPI_RXCRCR) (not used in I
2
S mode) . . . . . . 717
25.5.7 SPI TX CRC register (SPI_TXCRCR) (not used in I
2
S mode) . . . . . . 717
25.5.8 SPI_I
2
S configuration register (SPI_I2SCFGR) . . . . . . . . . . . . . . . . . . 718
25.5.9 SPI_I
2
S prescaler register (SPI_I2SPR) . . . . . . . . . . . . . . . . . . . . . . . 719
25.5.10 SPI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720
26 Inter-integrated circuit (I
2
C) interface . . . . . . . . . . . . . . . . . . . . . . . . . 721
26.1 I
2
C introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 721
26.2 I
2
C main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 721
26.3 I
2
C functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 722
26.3.1 Mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 722
26.3.2 I2C slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 724
26.3.3 I2C master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726
26.3.4 Error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 734
26.3.5 SDA/SCL line control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735
26.3.6 SMBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736
26.3.7 DMA requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738
26.3.8 Packet error checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 740
26.4 I
2
C interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 740
RM0008 Contents
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26.5 I
2
C debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742
26.6 I
2
C registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742
26.6.1 I
2
C Control register 1 (I2C_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742
26.6.2 I
2
C Control register 2 (I2C_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744
26.6.3 I
2
C Own address register 1 (I2C_OAR1) . . . . . . . . . . . . . . . . . . . . . . . 746
26.6.4 I
2
C Own address register 2 (I2C_OAR2) . . . . . . . . . . . . . . . . . . . . . . . 746
26.6.5 I
2
C Data register (I2C_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 747
26.6.6 I
2
C Status register 1 (I2C_SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 747
26.6.7 I
2
C Status register 2 (I2C_SR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751
26.6.8 I
2
C Clock control register (I2C_CCR) . . . . . . . . . . . . . . . . . . . . . . . . . 752
26.6.9 I
2
C TRISE register (I2C_TRISE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753
26.6.10 I2C register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 754
27 Universal synchronous asynchronous receiver
transmitter (USART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 755
27.1 USART introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 755
27.2 USART main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 756
27.3 USART functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 757
27.3.1 USART character description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 760
27.3.2 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 761
27.3.3 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 764
27.3.4 Fractional baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 768
27.3.5 USART receivers tolerance to clock deviation . . . . . . . . . . . . . . . . . . 770
27.3.6 Multiprocessor communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770
27.3.7 Parity control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 772
27.3.8 LIN (local interconnection network) mode . . . . . . . . . . . . . . . . . . . . . . 773
27.3.9 USART synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 775
27.3.10 Single-wire half-duplex communication . . . . . . . . . . . . . . . . . . . . . . . . 777
27.3.11 Smartcard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 778
27.3.12 IrDA SIR ENDEC block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 780
27.3.13 Continuous communication using DMA . . . . . . . . . . . . . . . . . . . . . . . . 782
27.3.14 Hardware flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 785
27.4 USART interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 786
27.5 USART mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 787
27.6 USART registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 787
27.6.1 Status register (USART_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 788

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27.6.2 Data register (USART_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 790
27.6.3 Baud rate register (USART_BRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 790
27.6.4 Control register 1 (USART_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 791
27.6.5 Control register 2 (USART_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 793
27.6.6 Control register 3 (USART_CR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 794
27.6.7 Guard time and prescaler register (USART_GTPR) . . . . . . . . . . . . . . 796
27.6.8 USART register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 797
28 USB on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . . . . . . . . . . . . 798
28.1 OTG_FS introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 798
28.2 OTG_FS main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 799
28.2.1 General features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 799
28.2.2 Host-mode features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800
28.2.3 Peripheral-mode features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800
28.3 OTG_FS functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 801
28.3.1 OTG full-speed core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 801
28.3.2 Full-speed OTG PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 801
28.4 OTG dual role device (DRD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 802
28.4.1 ID line detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803
28.4.2 HNP dual role device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803
28.4.3 SRP dual role device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803
28.5 USB peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 804
28.5.1 SRP-capable peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 804
28.5.2 Peripheral states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 805
28.5.3 Peripheral endpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 806
28.6 USB host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 808
28.6.1 SRP-capable host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 809
28.6.2 USB host states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 809
28.6.3 Host channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810
28.6.4 Host scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 812
28.7 SOF trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 813
28.7.1 Host SOFs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 813
28.7.2 Peripheral SOFs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 813
28.8 Power options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 814
28.9 Dynamic update of the OTG_FS_HFIR register . . . . . . . . . . . . . . . . . . . 815
28.10 USB data FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 815
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28.11 Peripheral FIFO architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 816
28.11.1 Peripheral Rx FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 816
28.11.2 Peripheral Tx FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817
28.12 Host FIFO architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817
28.12.1 Host Rx FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817
28.12.2 Host Tx FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 818
28.13 FIFO RAM allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 818
28.13.1 Device mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 818
28.13.2 Host mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 819
28.14 USB system performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 819
28.15 OTG_FS interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 820
28.16 OTG_FS control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 822
28.16.1 CSR memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 823
28.16.2 OTG_FS global registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 827
28.16.3 Host-mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 848
28.16.4 Device-mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 859
28.16.5 OTG_FS power and clock gating control register
(OTG_FS_PCGCCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 881
28.16.6 OTG_FS register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 882
28.17 OTG_FS programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 888
28.17.1 Core initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 888
28.17.2 Host initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 890
28.17.3 Device initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 890
28.17.4 Host programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 891
28.17.5 Device programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 908
28.17.6 Operational model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 910
28.17.7 Worst case response time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 927
28.17.8 OTG programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 928
29 Ethernet (ETH): media access control (MAC) with
DMA controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 935
29.1 Ethernet introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 935
29.2 Ethernet main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 935
29.2.1 MAC core features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 936
29.2.2 DMA features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 937
29.2.3 PTP features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 937

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29.3 Ethernet pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 938
29.4 Ethernet functional description: SMI, MII and RMII . . . . . . . . . . . . . . . . 939
29.4.1 Station management interface: SMI . . . . . . . . . . . . . . . . . . . . . . . . . . . 939
29.4.2 Media-independent interface: MII . . . . . . . . . . . . . . . . . . . . . . . . . . . . 942
29.4.3 Reduced media-independent interface: RMII . . . . . . . . . . . . . . . . . . . 945
29.4.4 MII/RMII selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 946
29.5 Ethernet functional description: MAC 802.3 . . . . . . . . . . . . . . . . . . . . . . 947
29.5.1 MAC 802.3 frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 947
29.5.2 MAC frame transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 951
29.5.3 MAC frame reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 958
29.5.4 MAC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 963
29.5.5 MAC filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 963
29.5.6 MAC loopback mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 966
29.5.7 MAC management counters: MMC . . . . . . . . . . . . . . . . . . . . . . . . . . . 966
29.5.8 Power management: PMT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 967
29.5.9 Precision time protocol (IEEE1588 PTP) . . . . . . . . . . . . . . . . . . . . . . . 970
29.6 Ethernet functional description: DMA controller operation . . . . . . . . . . . 976
29.6.1 Initialization of a transfer using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . 977
29.6.2 Host bus burst access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 977
29.6.3 Host data buffer alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 978
29.6.4 Buffer size calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 978
29.6.5 DMA arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 979
29.6.6 Error response to DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 979
29.6.7 Tx DMA configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 979
29.6.8 Rx DMA configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 988
29.6.9 DMA interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 997
29.7 Ethernet interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 998
29.8 Ethernet register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 999
29.8.1 MAC register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 999
29.8.2 MMC register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1016
29.8.3 IEEE 1588 time stamp registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1021
29.8.4 DMA register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1025
29.8.5 Ethernet register maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1039
30 Device electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1042
30.1 Memory size registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1042
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30.1.1 Flash size register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1042
30.2 Unique device ID register (96 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1043
31 Debug support (DBG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1045
31.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1045
31.2 Reference ARM documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1047
31.3 SWJ debug port (serial wire and JTAG) . . . . . . . . . . . . . . . . . . . . . . . . 1047
31.3.1 Mechanism to select the JTAG-DP or the SW-DP . . . . . . . . . . . . . . . 1047
31.4 Pinout and debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1048
31.4.1 SWJ debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1049
31.4.2 Flexible SWJ-DP pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1049
31.4.3 Internal pull-up and pull-down on JTAG pins . . . . . . . . . . . . . . . . . . . 1050
31.4.4 Using serial wire and releasing the unused debug pins as GPIOs . . 1051
31.5 STM32F10xxx JTAG TAP connection . . . . . . . . . . . . . . . . . . . . . . . . . 1051
31.6 ID codes and locking mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1052
31.6.1 MCU device ID code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1052
31.6.2 Boundary scan TAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1053
31.6.3 Cortex-M3 TAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1054
31.6.4 Cortex-M3 JEDEC-106 ID code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1054
31.7 JTAG debug port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1054
31.8 SW debug port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1056
31.8.1 SW protocol introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1056
31.8.2 SW protocol sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1056
31.8.3 SW-DP state machine (reset, idle states, ID code) . . . . . . . . . . . . . . 1057
31.8.4 DP and AP read/write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1057
31.8.5 SW-DP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1058
31.8.6 SW-AP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1058
31.9 AHB-AP (AHB access port) - valid for both JTAG-DP
and SW-DP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1059
31.10 Core debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1060
31.11 Capability of the debugger host to connect under system reset . . . . . 1060
31.12 FPB (Flash patch breakpoint) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1061
31.13 DWT (data watchpoint trigger) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1062
31.14 ITM (instrumentation trace macrocell) . . . . . . . . . . . . . . . . . . . . . . . . . 1062
31.14.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1062
31.14.2 Time stamp packets, synchronization and overflow packets . . . . . . . 1062

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31.15 ETM (Embedded trace macrocell) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1064
31.15.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1064
31.15.2 Signal protocol, packet types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1064
31.15.3 Main ETM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1065
31.15.4 Configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1065
31.16 MCU debug component (DBGMCU) . . . . . . . . . . . . . . . . . . . . . . . . . . 1065
31.16.1 Debug support for low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . 1065
31.16.2 Debug support for timers, watchdog, bxCAN and I
2
C . . . . . . . . . . . . 1066
31.16.3 Debug MCU configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . 1066
31.17 TPIU (trace port interface unit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1068
31.17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1068
31.17.2 TRACE pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1069
31.17.3 TPUI formatter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1071
31.17.4 TPUI frame synchronization packets . . . . . . . . . . . . . . . . . . . . . . . . . 1071
31.17.5 Transmission of the synchronization frame packet . . . . . . . . . . . . . . 1071
31.17.6 Synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1072
31.17.7 Asynchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1072
31.17.8 TRACECLKIN connection inside the STM32F10xxx . . . . . . . . . . . . . 1072
31.17.9 TPIU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1073
31.17.10 Example of configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1074
31.18 DBG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1074
32 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1075
RM0008 List of tables
Doc ID 13902 Rev 13 27/1093

List of tables
Table 1. Sections related to each STM32F10xxx product . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 2. Sections related to each peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 3. Register boundary addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 4. Flash module organization (low-density devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 5. Flash module organization (medium-density devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 6. Flash module organization (high-density devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 7. Flash module organization (connectivity line devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 8. XL-density Flash module organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 9. Boot modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 10. CRC calculation unit register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 11. Low-power mode summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 12. Sleep-now. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 13. Sleep-on-exit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 14. Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 15. Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 16. PWR register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 17. BKP register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 18. RCC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Table 19. RCC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Table 20. Port bit configuration table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Table 21. Output MODE bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Table 22. Advanced timers TIM1/TIM8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Table 23. General-purpose timers TIM2/3/4/5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Table 24. USARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Table 25. SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Table 26. I2S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Table 27. I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Table 28. BxCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Table 29. USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Table 30. OTG_FS pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Table 31. SDIO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Table 32. FSMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Table 33. Other IOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Table 34. CAN1 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Table 35. CAN2 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Table 36. Debug interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Table 37. Debug port mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Table 38. ADC1 external trigger injected conversion alternate function remapping. . . . . . . . . . . . . 172
Table 39. ADC1 external trigger regular conversion alternate function remapping . . . . . . . . . . . . . 172
Table 40. ADC2 external trigger injected conversion alternate function remapping. . . . . . . . . . . . . 172
Table 41. ADC2 external trigger regular conversion alternate function remapping . . . . . . . . . . . . . 173
Table 42. TIM5 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Table 43. TIM4 alternate function remapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Table 44. TIM3 alternate function remapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Table 45. TIM2 alternate function remapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Table 46. TIM1 alternate function remapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Table 47. TIM9 remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Table 48. TIM10 remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

List of tables RM0008
28/1093 Doc ID 13902 Rev 13
Table 49. TIM11 remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Table 50. TIM13 remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Table 51. TIM14 remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Table 52. USART3 remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Table 53. USART2 remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Table 54. USART1 remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Table 55. I2C1 remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Table 56. SPI1 remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Table 57. SPI3/I2S3 remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Table 58. ETH remapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Table 59. GPIO register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Table 60. AFIO register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Table 61. Vector table for connectivity line devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Table 62. Vector table for XL-density devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Table 63. Vector table for other STM32F10xxx devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Table 64. External interrupt/event controller register map and reset values. . . . . . . . . . . . . . . . . . . 205
Table 65. ADC pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Table 66. Analog watchdog channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Table 67. External trigger for regular channels for ADC1 and ADC2 . . . . . . . . . . . . . . . . . . . . . . . . 216
Table 68. External trigger for injected channels for ADC1 and ADC2 . . . . . . . . . . . . . . . . . . . . . . . 217
Table 69. External trigger for regular channels for ADC3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Table 70. External trigger for injected channels for ADC3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Table 71. ADC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Table 72. ADC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Table 73. DAC pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Table 74. External triggers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Table 75. DAC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
Table 76. Programmable data width & endian behavior (when bits PINC = MINC = 1) . . . . . . . . . . 270
Table 77. DMA interrupt requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
Table 78. Summary of DMA1 requests for each channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
Table 79. Summary of DMA2 requests for each channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Table 80. DMA register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
Table 81. Counting direction versus encoder signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
Table 82. TIMx Internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
Table 83. Output control bits for complementary OCx and OCxN channels with
break feature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
Table 84. TIM1&TIM8 register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
Table 85. Counting direction versus encoder signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
Table 86. TIMx Internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390
Table 87. Output control bit for standard OCx channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400
Table 88. TIMx register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405
Table 89. TIMx internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430
Table 90. Output control bit for standard OCx channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437
Table 91. TIM9/12 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438
Table 92. Output control bit for standard OCx channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445
Table 93. TIM10/11/13/14 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447
Table 94. TIM6&TIM7 register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460
Table 95. RTC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472
Table 96. Min/max IWDG timeout period at 40 kHz (LSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474
Table 97. IWDG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477
Table 98. Min-max timeout value @36 MHz (PCLK1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481
Table 99. WWDG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484
RM0008 List of tables
Doc ID 13902 Rev 13 29/1093

Table 100. NOR/PSRAM bank selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489
Table 101. External memory address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490
Table 102. Memory mapping and timing registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490
Table 103. NAND bank selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490
Table 104. Programmable NOR/PSRAM access parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491
Table 105. Nonmultipled I/O NOR Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492
Table 106. Multiplexed I/O NOR Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492
Table 107. Nonmultiplexed I/Os PSRAM/SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493
Table 108. NOR Flash/PSRAM supported memories and transactions . . . . . . . . . . . . . . . . . . . . . . . 494
Table 109. FSMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497
Table 110. FSMC_BTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497
Table 111. FSMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499
Table 112. FSMC_BTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499
Table 113. FSMC_BWTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499
Table 114. FSMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501
Table 115. FSMC_BTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502
Table 116. FSMC_BWTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502
Table 117. FSMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504
Table 118. FSMC_BTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504
Table 119. FSMC_BWTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504
Table 120. FSMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506
Table 121. FSMC_BTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506
Table 122. FSMC_BWTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506
Table 123. FSMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508
Table 124. FSMC_BTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508
Table 125. FSMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513
Table 126. FSMC_BTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514
Table 127. FSMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516
Table 128. FSMC_BTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516
Table 129. Programmable NAND/PC Card access parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523
Table 130. 8-bit NAND Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523
Table 131. 16-bit NAND Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524
Table 132. 16-bit PC Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524
Table 133. Supported memories and transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525
Table 134. 16-bit PC-Card signals and access type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529
Table 135. ECC result relevant bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536
Table 136. FSMC register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537
Table 137. SDIO I/O definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543
Table 138. Command format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547
Table 139. Short response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548
Table 140. Long response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548
Table 141. Command path status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548
Table 142. Data token format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551
Table 143. Transmit FIFO status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552
Table 144. Receive FIFO status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553
Table 145. Card status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563
Table 146. SD status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565
Table 147. Speed class code field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567
Table 148. Performance move field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567
Table 149. AU_SIZE field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567
Table 150. Maximum AU size. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568
Table 151. Erase size field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568

List of tables RM0008
30/1093 Doc ID 13902 Rev 13
Table 152. Erase timeout field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568
Table 153. Erase offset field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569
Table 154. Block-oriented write commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571
Table 155. Block-oriented write protection commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572
Table 156. Erase commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572
Table 157. I/O mode commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572
Table 158. Lock card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573
Table 159. Application-specific commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573
Table 160. R1 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574
Table 161. R2 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574
Table 162. R3 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575
Table 163. R4 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575
Table 164. R4b response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575
Table 165. R5 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576
Table 166. R6 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576
Table 167. Response type and SDIO_RESPx registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583
Table 168. SDIO register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593
Table 169. Double-buffering buffer flag definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605
Table 170. Bulk double-buffering memory buffers usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 606
Table 171. Isochronous memory buffers usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607
Table 172. Resume event detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609
Table 173. Reception status encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 620
Table 174. Endpoint type encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 620
Table 175. Endpoint kind meaning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 620
Table 176. Transmission status encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 620
Table 177. Definition of allocated buffer memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624
Table 178. USB register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624
Table 179. Transmit mailbox mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641
Table 180. Receive mailbox mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641
Table 181. bxCAN register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667
Table 182. SPI interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 692
Table 183. Audio-frequency precision using standard 8 MHz HSE (high-density and XL-density
devices only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703
Table 184. Audio-frequency precision using standard 25 MHz and PLL3
(connectivity line devices only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704
Table 185. Audio-frequency precision using standard 14.7456 MHz and PLL3
(connectivity line devices only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705
Table 186. I
2
S interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711
Table 187. SPI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720
Table 188. SMBus vs. I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736
Table 189. I2C Interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 740
Table 190. I2C register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 754
Table 191. Noise detection from sampled data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767
Table 192. Error calculation for programmed baud rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 769
Table 193. USART receivers tolerance when DIV_Fraction is 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770
Table 194. USART receivers tolerance when DIV_Fraction is different from 0 . . . . . . . . . . . . . . . . . 770
Table 195. Frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 772
Table 196. USART interrupt requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 786
Table 197. USART mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 787
Table 198. USART register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 797
Table 199. Core global control and status registers (CSRs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 823
Table 200. Host-mode control and status registers (CSRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824
RM0008 List of tables
Doc ID 13902 Rev 13 31/1093

Table 201. Device-mode control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825
Table 202. Data FIFO (DFIFO) access register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 827
Table 203. Power and clock gating control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 827
Table 204. Minimum duration for soft disconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 861
Table 205. OTG_FS register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 882
Table 206. Ethernet pin configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 938
Table 207. Management frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 940
Table 208. Clock range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 942
Table 209. TX interface signal encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 944
Table 210. RX interface signal encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 944
Table 211. Frame statuses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 960
Table 212. Destination address filtering table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 965
Table 213. Source address filtering table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 966
Table 214. Receive descriptor 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 994
Table 215. Ethernet register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1039
Table 216. SWJ debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1049
Table 217. Flexible SWJ-DP pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1050
Table 218. JTAG debug port data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1054
Table 219. 32-bit debug port registers addressed through the shifted value A[3:2] . . . . . . . . . . . . . 1055
Table 220. Packet request (8-bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1056
Table 221. ACK response (3 bits). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1057
Table 222. DATA transfer (33 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1057
Table 223. SW-DP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1058
Table 224. Cortex-M3 AHB-AP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1059
Table 225. Core debug registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1060
Table 226. Main ITM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1063
Table 227. Main ETM registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1065
Table 228. Asynchronous TRACE pin assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1069
Table 229. Synchronous TRACE pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1069
Table 230. Flexible TRACE pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1070
Table 231. Important TPIU registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1073
Table 232. DBG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1074
Table 233. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1075

List of figures RM0008
32/1093 Doc ID 13902 Rev 13
List of figures
Figure 1. System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 2. System architecture in connectivity line devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 3. CRC calculation unit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 4. Power supply overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 5. Power on reset/power down reset waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 6. PVD thresholds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 7. Simplified diagram of the reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 8. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 9. HSE/ LSE clock sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 10. Simplified diagram of the reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Figure 11. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Figure 12. HSE/ LSE clock sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Figure 13. Basic structure of a standard I/O port bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Figure 14. Basic structure of a five-volt tolerant I/O port bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Figure 15. Input floating/pull up/pull down configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Figure 16. Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Figure 17. Alternate function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Figure 18. High impedance-analog configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Figure 19. ADC / DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Figure 20. External interrupt/event controller block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Figure 21. External interrupt/event GPIO mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Figure 22. Single ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Figure 23. Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Figure 24. Analog watchdog guarded area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Figure 25. Injected conversion latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Figure 26. Calibration timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Figure 27. Right alignment of data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Figure 28. Left alignment of data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Figure 29. Dual ADC block diagram
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Figure 30. Injected simultaneous mode on 4 channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Figure 31. Regular simultaneous mode on 16 channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Figure 32. Fast interleaved mode on 1 channel in continuous conversion mode . . . . . . . . . . . . . . . 222
Figure 33. Slow interleaved mode on 1 channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Figure 34. Alternate trigger: injected channel group of each ADC. . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Figure 35. Alternate trigger: 4 injected channels (each ADC) in discontinuous model . . . . . . . . . . . 224
Figure 36. Alternate + Regular simultaneous. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Figure 37. Case of trigger occurring during injected conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Figure 38. Interleaved single channel with injected sequence CH11, CH12 . . . . . . . . . . . . . . . . . . . 225
Figure 39. Temperature sensor and VREFINT channel block diagram . . . . . . . . . . . . . . . . . . . . . . 226
Figure 40. DAC channel block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Figure 41. Data registers in single DAC channel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Figure 42. Data registers in dual DAC channel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Figure 43. Timing diagram for conversion with trigger disabled TEN = 0 . . . . . . . . . . . . . . . . . . . . . 249
Figure 44. DAC LFSR register calculation algorithm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Figure 45. DAC conversion (SW trigger enabled) with LFSR wave generation. . . . . . . . . . . . . . . . . 251
Figure 46. DAC triangle wave generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Figure 47. DAC conversion (SW trigger enabled) with triangle wave generation . . . . . . . . . . . . . . . 252
Figure 48. DMA block diagram in connectivity line devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
RM0008 List of figures
Doc ID 13902 Rev 13 33/1093

Figure 49. DMA block diagram in low-, medium- high- and XL-density devices . . . . . . . . . . . . . . . . 267
Figure 50. DMA1 request mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
Figure 51. DMA2 request mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Figure 52. Advanced-control timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
Figure 53. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 286
Figure 54. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 286
Figure 55. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
Figure 56. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
Figure 57. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
Figure 58. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
Figure 59. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . . 288
Figure 60. Counter timing diagram, update event when ARPE=1
(TIMx_ARR preloaded) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
Figure 61. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
Figure 62. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
Figure 63. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
Figure 64. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Figure 65. Counter timing diagram, update event when repetition counter
is not used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Figure 66. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . . . . . . . . . . . 292
Figure 67. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
Figure 68. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . . 293
Figure 69. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
Figure 70. Counter timing diagram, update event with ARPE=1 (counter underflow) . . . . . . . . . . . . 294
Figure 71. Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . . . . . . . . . . 294
Figure 72. Update rate examples depending on mode and TIMx_RCR register settings . . . . . . . . . 295
Figure 73. Control circuit in normal mode, internal clock divided by 1. . . . . . . . . . . . . . . . . . . . . . . . 296
Figure 74. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
Figure 75. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
Figure 76. External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
Figure 77. Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
Figure 78. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 299
Figure 79. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
Figure 80. Output stage of capture/compare channel (channel 1 to 3) . . . . . . . . . . . . . . . . . . . . . . . 300
Figure 81. Output stage of capture/compare channel (channel 4). . . . . . . . . . . . . . . . . . . . . . . . . . . 300
Figure 82. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
Figure 83. Output compare mode, toggle on OC1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
Figure 84. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
Figure 85. Center-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
Figure 86. Complementary output with dead-time insertion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
Figure 87. Dead-time waveforms with delay greater than the negative pulse. . . . . . . . . . . . . . . . . . 307
Figure 88. Dead-time waveforms with delay greater than the positive pulse. . . . . . . . . . . . . . . . . . . 308
Figure 89. Output behavior in response to a break.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
Figure 90. Clearing TIMx OCxREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
Figure 91. 6-step generation, COM example (OSSR=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
Figure 92. Example of one pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
Figure 93. Example of counter operation in encoder interface mode. . . . . . . . . . . . . . . . . . . . . . . . . 316
Figure 94. Example of encoder interface mode with TI1FP1 polarity inverted. . . . . . . . . . . . . . . . . . 316
Figure 95. Example of hall sensor interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
Figure 96. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
Figure 97. Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
Figure 98. Control circuit in trigger mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321

List of figures RM0008
34/1093 Doc ID 13902 Rev 13
Figure 99. Control circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . 322
Figure 100. General-purpose timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
Figure 101. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 352
Figure 102. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 353
Figure 103. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354
Figure 104. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354
Figure 105. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354
Figure 106. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
Figure 107. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded). . . . . 355
Figure 108. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded). . . . . . . . 356
Figure 109. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
Figure 110. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
Figure 111. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
Figure 112. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358
Figure 113. Counter timing diagram, Update event when repetition counter is not used . . . . . . . . . . 358
Figure 114. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . . . . . . . . . . . . 359
Figure 115. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
Figure 116. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . . 360
Figure 117. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
Figure 118. Counter timing diagram, Update event with ARPE=1 (counter underflow). . . . . . . . . . . . 361
Figure 119. Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . . . . . . . . . . 361
Figure 120. Control circuit in normal mode, internal clock divided by 1. . . . . . . . . . . . . . . . . . . . . . . . 362
Figure 121. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
Figure 122. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
Figure 123. External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
Figure 124. Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
Figure 125. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 365
Figure 126. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365
Figure 127. Output stage of capture/compare channel (channel 1). . . . . . . . . . . . . . . . . . . . . . . . . . . 366
Figure 128. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
Figure 129. Output compare mode, toggle on OC1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
Figure 130. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
Figure 131. Center-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
Figure 132. Example of one-pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
Figure 133. Clearing TIMx OCxREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375
Figure 134. Example of counter operation in encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . 376
Figure 135. Example of encoder interface mode with TI1FP1 polarity inverted . . . . . . . . . . . . . . . . . 377
Figure 136. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
Figure 137. Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379
Figure 138. Control circuit in trigger mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379
Figure 139. Control circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . 380
Figure 140. Master/Slave timer example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381
Figure 141. Gating timer 2 with OC1REF of timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382
Figure 142. Gating timer 2 with Enable of timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
Figure 143. Triggering timer 2 with update of timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
Figure 144. Triggering timer 2 with Enable of timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384
Figure 145. Triggering timer 1 and 2 with timer 1 TI1 input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385
Figure 146. General-purpose timer block diagram (TIM9 and TIM12) . . . . . . . . . . . . . . . . . . . . . . . . 409
Figure 147. General-purpose timer block diagram (TIM10/11/13/14) . . . . . . . . . . . . . . . . . . . . . . . . 410
Figure 148. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 412
Figure 149. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 412
Figure 150. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413
RM0008 List of figures
Doc ID 13902 Rev 13 35/1093

Figure 151. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413
Figure 152. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
Figure 153. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
Figure 154. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not
preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
Figure 155. Counter timing diagram, update event when ARPE=1 (TIMx_ARR
preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
Figure 156. Control circuit in normal mode, internal clock divided by 1. . . . . . . . . . . . . . . . . . . . . . . . 416
Figure 157. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416
Figure 158. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
Figure 159. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 417
Figure 160. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418
Figure 161. Output stage of capture/compare channel (channel 1). . . . . . . . . . . . . . . . . . . . . . . . . . . 418
Figure 162. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420
Figure 163. Output compare mode, toggle on OC1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422
Figure 164. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
Figure 165. Example of one pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
Figure 166. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
Figure 167. Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426
Figure 168. Control circuit in trigger mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426
Figure 169. Basic timer block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450
Figure 170. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 451
Figure 171. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 451
Figure 172. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452
Figure 173. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453
Figure 174. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453
Figure 175. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453
Figure 176. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not
preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454
Figure 177. Counter timing diagram, update event when ARPE=1 (TIMx_ARR
preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454
Figure 178. Control circuit in normal mode, internal clock divided by 1. . . . . . . . . . . . . . . . . . . . . . . . 455
Figure 179. RTC simplified block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463
Figure 180. RTC second and alarm waveform example with PR=0003, ALARM=00004 . . . . . . . . . . 465
Figure 181. RTC Overflow waveform example with PR=0003. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465
Figure 182. Independent watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474
Figure 183. Watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479
Figure 184. Window watchdog timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480
Figure 185. FSMC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487
Figure 186. FSMC memory banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489
Figure 187. Mode1 read accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496
Figure 188. Mode1 write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496
Figure 189. ModeA read accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498
Figure 190. ModeA write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498
Figure 191. Mode2/B read accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500
Figure 192. Mode2 write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500
Figure 193. ModeB write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501
Figure 194. ModeC read accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503
Figure 195. ModeC write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503
Figure 196. ModeD read accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505
Figure 197. Multiplexed read accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507
Figure 198. Multiplexed write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507

List of figures RM0008
36/1093 Doc ID 13902 Rev 13
Figure 199. Asynchronous wait during a read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509
Figure 200. Asynchronous wait during a write access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510
Figure 201. Wait configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512
Figure 202. Synchronous multiplexed read mode - NOR, PSRAM (CRAM) . . . . . . . . . . . . . . . . . . . . 513
Figure 203. Synchronous multiplexed write mode - PSRAM (CRAM) . . . . . . . . . . . . . . . . . . . . . . . . . 515
Figure 204. NAND/PC Card controller timing for common memory access . . . . . . . . . . . . . . . . . . . 526
Figure 205. Access to non CE dont care NAND-Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527
Figure 206. SDIO no response and no data operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540
Figure 207. SDIO (multiple) block read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540
Figure 208. SDIO (multiple) block write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541
Figure 209. SDIO sequential read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541
Figure 210. SDIO sequential write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541
Figure 211. SDIO block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542
Figure 212. SDIO adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543
Figure 213. Control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544
Figure 214. SDIO adapter command path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545
Figure 215. Command path state machine (CPSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546
Figure 216. SDIO command transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547
Figure 217. Data path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549
Figure 218. Data path state machine (DPSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550
Figure 219. USB peripheral block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596
Figure 220. Packet buffer areas with examples of buffer description table locations . . . . . . . . . . . . . 600
Figure 221. CAN network topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627
Figure 222. Dual CAN block diagram (connectivity devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629
Figure 223. bxCAN operating modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 631
Figure 224. bxCAN in silent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632
Figure 225. bxCAN in loop back mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632
Figure 226. bxCAN in combined mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633
Figure 227. Transmit mailbox states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634
Figure 228. Receive FIFO states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635
Figure 229. Filter bank scale configuration - register organization . . . . . . . . . . . . . . . . . . . . . . . . . . . 638
Figure 230. Example of filter numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639
Figure 231. Filtering mechanism - example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640
Figure 232. CAN error state diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641
Figure 233. Bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643
Figure 234. CAN frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 644
Figure 235. Event flags and interrupt generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645
Figure 236. SPI block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673
Figure 237. Single master/ single slave application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674
Figure 238. Data clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675
Figure 239. TXE/RXNE/BSY behavior in Master / full-duplex mode (BIDIMODE=0 and RXONLY=0)
in the case of continuous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 682
Figure 240. TXE/RXNE/BSY behavior in Slave / full-duplex mode (BIDIMODE=0, RXONLY=0) in the
case of continuous transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 682
Figure 241. TXE/BSY behavior in Master transmit-only mode (BIDIMODE=0 and RXONLY=0) in the
case of continuous transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 683
Figure 242. TXE/BSY in Slave transmit-only mode (BIDIMODE=0 and RXONLY=0) in the case of
continuous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 684
Figure 243. RXNE behavior in receive-only mode (BIDIRMODE=0 and RXONLY=1) in the case of
continuous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685
Figure 244. TXE/BSY behavior when transmitting (BIDIRMODE=0 and RXONLY=0) in the case of
discontinuous transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686
RM0008 List of figures
Doc ID 13902 Rev 13 37/1093

Figure 245. Transmission using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 690
Figure 246. Reception using DMA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691
Figure 247. I
2
S block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693
Figure 248. I
2
S Phillips protocol waveforms (16/32-bit full accuracy, CPOL = 0) . . . . . . . . . . . . . . . . 695
Figure 249. I
2
S Phillips standard waveforms (24-bit frame with CPOL = 0) . . . . . . . . . . . . . . . . . . . . 695
Figure 250. Transmitting 0x8EAA33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 696
Figure 251. Receiving 0x8EAA33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 696
Figure 252. I
2
S Phillips standard (16-bit extended to 32-bit packet frame with CPOL = 0) . . . . . . . . . 696
Figure 253. Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 697
Figure 254. MSB Justified 16-bit or 32-bit full-accuracy length with CPOL = 0 . . . . . . . . . . . . . . . . . . 697
Figure 255. MSB Justified 24-bit frame length with CPOL = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 698
Figure 256. MSB Justified 16-bit extended to 32-bit packet frame with CPOL = 0 . . . . . . . . . . . . . . . 698
Figure 257. LSB justified 16-bit or 32-bit full-accuracy with CPOL = 0 . . . . . . . . . . . . . . . . . . . . . . . . 698
Figure 258. LSB Justified 24-bit frame length with CPOL = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699
Figure 259. Operations required to transmit 0x3478AE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699
Figure 260. Operations required to receive 0x3478AE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699
Figure 261. LSB Justified 16-bit extended to 32-bit packet frame with CPOL = 0. . . . . . . . . . . . . . . . 700
Figure 262. Example of LSB justified 16-bit extended to 32-bit packet frame . . . . . . . . . . . . . . . . . . . 700
Figure 263. PCM standard waveforms (16-bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 701
Figure 264. PCM standard waveforms (16-bit extended to 32-bit packet frame). . . . . . . . . . . . . . . . . 701
Figure 265. Audio sampling frequency definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 702
Figure 266. I
2
S clock generator architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 702
Figure 267. I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723
Figure 268. I2C block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 724
Figure 269. Transfer sequence diagram for slave transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725
Figure 270. Transfer sequence diagram for slave receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726
Figure 271. Transfer sequence diagram for master transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 729
Figure 272. Method 1: transfer sequence diagram for master receiver . . . . . . . . . . . . . . . . . . . . . . . . 731
Figure 273. Method 2: transfer sequence diagram for master receiver when N>2 . . . . . . . . . . . . . . . 732
Figure 274. Method 2: transfer sequence diagram for master receiver when N=2 . . . . . . . . . . . . . . . 733
Figure 275. Method 2: transfer sequence diagram for master receiver when N=1 . . . . . . . . . . . . . . . 734
Figure 276. I2C interrupt mapping diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741
Figure 277. USART block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 759
Figure 278. Word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 760
Figure 279. Configurable stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762
Figure 280. TC/TXE behavior when transmitting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763
Figure 281. Start bit detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 764
Figure 282. Data sampling for noise detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766
Figure 283. Mute mode using Idle line detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 771
Figure 284. Mute mode using address mark detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 772
Figure 285. Break detection in LIN mode (11-bit break length - LBDL bit is set) . . . . . . . . . . . . . . . . . 774
Figure 286. Break detection in LIN mode vs. Framing error detection. . . . . . . . . . . . . . . . . . . . . . . . . 775
Figure 287. USART example of synchronous transmission. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 776
Figure 288. USART data clock timing diagram (M=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 776
Figure 289. USART data clock timing diagram (M=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 777
Figure 290. RX data setup/hold time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 777
Figure 291. ISO 7816-3 asynchronous protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 778
Figure 292. Parity error detection using the 1.5 stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 780
Figure 293. IrDA SIR ENDEC- block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 782
Figure 294. IrDA data modulation (3/16) -normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 782
Figure 295. Transmission using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 783
Figure 296. Reception using DMA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 784

List of figures RM0008
38/1093 Doc ID 13902 Rev 13
Figure 297. Hardware flow control between two USARTs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 785
Figure 298. RTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 785
Figure 299. CTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 786
Figure 300. USART interrupt mapping diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 787
Figure 301. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 801
Figure 302. OTG A-B device connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 802
Figure 303. USB peripheral-only connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 804
Figure 304. USB host-only connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 809
Figure 305. SOF connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 813
Figure 306. Updating OTG_FS_HFIR dynamically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 815
Figure 307. Device-mode FIFO address mapping and AHB FIFO access mapping . . . . . . . . . . . . . . 816
Figure 308. Host-mode FIFO address mapping and AHB FIFO access mapping. . . . . . . . . . . . . . . . 817
Figure 309. Interrupt hierarchy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 821
Figure 310. CSR memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 823
Figure 311. Transmit FIFO write task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 892
Figure 312. Receive FIFO read task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 893
Figure 313. Normal bulk/control OUT/SETUP and bulk/control IN transactions . . . . . . . . . . . . . . . . . 895
Figure 314. Bulk/control IN transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 898
Figure 315. Normal interrupt OUT/IN transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900
Figure 316. Normal isochronous OUT/IN transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 905
Figure 317. Receive FIFO packet read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 911
Figure 318. Processing a SETUP packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 913
Figure 319. Bulk OUT transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 919
Figure 320. TRDT max timing case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 928
Figure 321. A-device SRP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 929
Figure 322. B-device SRP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 930
Figure 323. A-device HNP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 931
Figure 324. B-device HNP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 933
Figure 325. ETH block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 939
Figure 326. SMI interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 940
Figure 327. MDIO timing and frame structure - Write cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 941
Figure 328. MDIO timing and frame structure - Read cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 942
Figure 329. Media independent interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 943
Figure 330. MII clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 945
Figure 331. Reduced media-independent interface signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 945
Figure 332. RMII clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 946
Figure 333. Clock scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 946
Figure 334. Address field format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 948
Figure 335. MAC frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 950
Figure 336. Tagged MAC frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 950
Figure 337. Transmission bit order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 956
Figure 338. Transmission with no collision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 957
Figure 339. Transmission with collision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 957
Figure 340. Frame transmission in MMI and RMII modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 958
Figure 341. Receive bit order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 962
Figure 342. Reception with no error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 962
Figure 343. Reception with errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 962
Figure 344. Reception with false carrier indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 963
Figure 345. MAC core interrupt masking scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 963
Figure 346. Wakeup frame filter register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 968
Figure 347. Networked time synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 971
Figure 348. System time update using the Fine correction method. . . . . . . . . . . . . . . . . . . . . . . . . . . 973
RM0008 List of figures
Doc ID 13902 Rev 13 39/1093

Figure 349. PTP trigger output to TIM2 ITR1 connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 975
Figure 350. PPS output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 976
Figure 351. Descriptor ring and chain structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 977
Figure 352. TxDMA operation in Default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 981
Figure 353. TxDMA operation in OSF mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 983
Figure 354. ransmit descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 984
Figure 355. Receive DMA operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 990
Figure 356. Rx DMA descriptor structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 992
Figure 357. Interrupt scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 998
Figure 358. Ethernet MAC remote wakeup frame filter register (ETH_MACRWUFFR). . . . . . . . . . . 1008
Figure 359. Block diagram of STM32 MCU and Cortex-M3-level debug support . . . . . . . . . . . . . . . 1046
Figure 360. SWJ debug port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1047
Figure 361. JTAG TAP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1052
Figure 362. TPIU block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1069

Overview of the manual RM0008
40/1093 Doc ID 13902 Rev 13
1 Overview of the manual
Legend for Table 1:
The section in each row applies to products in columns marked with "

Table 1. Sections related to each STM32F10xxx product
L
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s
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S
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3
2
F
1
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x
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-
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a
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a
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5
x
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S
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F
1
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7
x
x
Section 2:
Documentation
conventions

Section 3: Memory and
bus architecture

Section 4: CRC
calculation unit

Section 5: Power
control (PWR)

Section 6: Backup
registers (BKP)

Section 7: Low-,
medium-, high- and XL-
density reset and clock
control (RCC)

Section 8: Connectivity
line devices: reset and
clock control (RCC)

Section 9: General-
purpose and alternate-
function I/Os (GPIOs
and AFIOs)

Section 10: Interrupts
and events

Section 13: Direct
memory access
controller (DMA)

RM0008 Overview of the manual
Doc ID 13902 Rev 13 41/1093

Section 11: Analog-to-
digital converter (ADC)

Section 12: Digital-to-
analog converter (DAC)

Section 14: Advanced-
control timers
(TIM1&TIM8)

Section 15: General-
purpose timers (TIM2 to
TIM5)

Section 16: General-
purpose timers (TIM9 to
TIM14)

(1)

(1)
Section 17: Basic
timers (TIM6&TIM7)

Section 18: Real-time
clock (RTC)

Section 19:
Independent watchdog
(IWDG)

Section 20: Window
watchdog (WWDG)

Section 21: Flexible
static memory
controller (FSMC)

Section 28: Secure
digital input/output
interface (SDIO)

Section 23: Universal
serial bus full-speed
device interface (USB)

Section 24: Controller
area network (bxCAN)

Table 1. Sections related to each STM32F10xxx product (continued)
L
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Overview of the manual RM0008
42/1093 Doc ID 13902 Rev 13
Note: 1) Available only on XL-density devices
Section 25: Serial
peripheral interface
(SPI)

Section 26: Inter-
integrated circuit (I2C)
interface

Section 27: Universal
synchronous
asynchronous receiver
transmitter (USART)

Section 28: USB on-
the-go full-speed
(OTG_FS)

Section 29: Ethernet
(ETH): media access
control (MAC) with
DMA controller

Section 30: Device

electronic signature

Section 31: Debug
support (DBG)

Table 1. Sections related to each STM32F10xxx product (continued)
L
o
w
-
d
e
n
s
i
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y

S
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3
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F
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1
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x
H
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a
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X
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S
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x
L
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y

S
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1
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x
M
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1
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RM0008 Overview of the manual
Doc ID 13902 Rev 13 43/1093

Legend for Table 2:

The section in this row must be read when using the peripherals in columns
marked with "

The section in this row can optionally be read when using the peripherals in
columns marked with "
Table 2. Sections related to each peripheral
B
a
c
k
u
p

r
e
g
i
s
t
e
r
s

(
B
K
P
)
G
e
n
e
r
a
l
-
p
u
r
p
o
s
e

I
/
O
s

(
G
P
I
O
s
)
A
n
a
l
o
g
-
t
o
-
d
i
g
i
t
a
l

c
o
n
v
e
r
t
e
r

(
A
D
C
)
D
i
g
i
t
a
l
-
t
o
-
a
n
a
l
o
g

c
o
n
v
e
r
t
e
r

(
D
A
C
)

A
d
v
a
n
c
e
d
-
c
o
n
t
r
o
l

t
i
m
e
r
s

(
T
I
M
1
&
T
I
M
8
)
G
e
n
e
r
a
l
-
p
u
r
p
o
s
e

t
i
m
e
r
s

(
T
I
M
2

t
o

T
I
M
5
)
G
e
n
e
r
a
l
-
p
u
r
p
o
s
e

t
i
m
e
r
s

(
T
I
M
9

t
o

T
I
M
1
4
)
B
a
s
i
c

t
i
m
e
r
s

(
T
I
M
6
&
T
I
M
7
)
R
e
a
l
-
t
i
m
e

c
l
o
c
k

(
R
T
C
)
I
n
d
e
p
e
n
d
e
n
t

w
a
t
c
h
d
o
g

(
I
W
D
G
)
W
i
n
d
o
w

w
a
t
c
h
d
o
g

(
W
W
D
G
)
F
l
e
x
i
b
l
e

s
t
a
t
i
c

m
e
m
o
r
y

c
o
n
t
r
o
l
l
e
r

(
F
S
M
C
)
S
e
c
u
r
e

d
i
g
i
t
a
l

i
n
p
u
t
/
o
u
t
p
u
t

i
n
t
e
r
f
a
c
e

(
S
D
I
O
)
U
S
B

f
u
l
l
-
s
p
e
e
d

d
e
v
i
c
e

(
U
S
B
)
C
o
n
t
r
o
l
l
e
r

a
r
e
a

n
e
t
w
o
r
k

(
b
x
C
A
N
)
S
e
r
i
a
l

p
e
r
i
p
h
e
r
a
l

i
n
t
e
r
f
a
c
e

(
S
P
I
)
I
n
t
e
r
-
i
n
t
e
g
r
a
t
e
d

c
i
r
c
u
i
t

(
I
2
C
)

i
n
t
e
r
f
a
c
e
U
S
A
R
T
U
S
B

o
n
-
t
h
e
-
g
o

f
u
l
l
-
s
p
e
e
d

(
O
T
G
_
F
S
)
E
t
h
e
r
n
e
t

(
E
T
H
)
Section 2:
Documentation
conventions

Section 3: Memory and
bus architecture

Section 4: CRC
calculation unit
Section 5: Power
control (PWR)

Section 6: Backup
registers (BKP)

Section 7: Low-,
medium-, high- and XL-
density reset and clock
control (RCC)

Section 8: Connectivity
line devices: reset and
clock control (RCC)

Section 9: General-
purpose and alternate-
function I/Os (GPIOs
and AFIOs)

Section 10: Interrupts
and events


Overview of the manual RM0008
44/1093 Doc ID 13902 Rev 13
Section 13: Direct
memory access
controller (DMA)

Section 11: Analog-to-
digital converter (ADC)

Section 12: Digital-to-
analog converter (DAC)

Section 14: Advanced-

control timers
(TIM1&TIM8)

Section 15: General-
purpose timers (TIM2 to
TIM5)

Section 16: General-
purpose timers (TIM9 to
TIM14)

Section 17: Basic

timers (TIM6&TIM7)

Section 18: Real-time
clock (RTC)

Section 19:
Independent watchdog
(IWDG)

Section 20: Window

watchdog (WWDG)

Section 21: Flexible
static memory
controller (FSMC)

Section 28: Secure

digital input/output
interface (SDIO)

Table 2. Sections related to each peripheral

B
a
c
k
u
p

r
e
g
i
s
t
e
r
s

(
B
K
P
)
G
e
n
e
r
a
l
-
p
u
r
p
o
s
e

I
/
O
s

(
G
P
I
O
s
)
A
n
a
l
o
g
-
t
o
-
d
i
g
i
t
a
l

c
o
n
v
e
r
t
e
r

(
A
D
C
)
D
i
g
i
t
a
l
-
t
o
-
a
n
a
l
o
g

c
o
n
v
e
r
t
e
r

(
D
A
C
)

A
d
v
a
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c
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d
-
c
o
n
t
r
o
l

t
i
m
e
r
s

(
T
I
M
1
&
T
I
M
8
)
G
e
n
e
r
a
l
-
p
u
r
p
o
s
e

t
i
m
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s

(
T
I
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2

t
o

T
I
M
5
)
G
e
n
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r
a
l
-
p
u
r
p
o
s
e

t
i
m
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r
s

(
T
I
M
9

t
o

T
I
M
1
4
)
B
a
s
i
c

t
i
m
e
r
s

(
T
I
M
6
&
T
I
M
7
)
R
e
a
l
-
t
i
m
e

c
l
o
c
k

(
R
T
C
)
I
n
d
e
p
e
n
d
e
n
t

w
a
t
c
h
d
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g

(
I
W
D
G
)
W
i
n
d
o
w

w
a
t
c
h
d
o
g

(
W
W
D
G
)
F
l
e
x
i
b
l
e

s
t
a
t
i
c

m
e
m
o
r
y

c
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n
t
r
o
l
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r

(
F
S
M
C
)
S
e
c
u
r
e

d
i
g
i
t
a
l

i
n
p
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/
o
u
t
p
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n
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r
f
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(
S
D
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)
U
S
B

f
u
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l
-
s
p
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(
U
S
B
)
C
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n
t
r
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l
l
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r

a
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a

n
e
t
w
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k

(
b
x
C
A
N
)
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r
i
a
l

p
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p
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r
a
l

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f
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(
S
P
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)
I
n
t
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r
-
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g
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a
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d

c
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t

(
I
2
C
)

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n
t
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f
a
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S
A
R
T
U
S
B

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-
t
h
e
-
g
o

f
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l
-
s
p
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d

(
O
T
G
_
F
S
)
E
t
h
e
r
n
e
t

(
E
T
H
)
RM0008 Overview of the manual
Doc ID 13902 Rev 13 45/1093

Section 23: Universal
serial bus full-speed
device interface (USB)

Section 24: Controller

area network (bxCAN)

Section 25: Serial
peripheral interface
(SPI)

Section 26: Inter-

integrated circuit (I2C)
interface

Section 27: Universal

synchronous
asynchronous receiver
transmitter (USART)

Section 28: USB on-

the-go full-speed
(OTG_FS)

Section 29: Ethernet

(ETH): media access
control (MAC) with
DMA controller

Section 30: Device

electronic signature
Section 31: Debug
support (DBG)

Table 2. Sections related to each peripheral
B
a
c
k
u
p

r
e
g
i
s
t
e
r
s

(
B
K
P
)
G
e
n
e
r
a
l
-
p
u
r
p
o
s
e

I
/
O
s

(
G
P
I
O
s
)
A
n
a
l
o
g
-
t
o
-
d
i
g
i
t
a
l

c
o
n
v
e
r
t
e
r

(
A
D
C
)
D
i
g
i
t
a
l
-
t
o
-
a
n
a
l
o
g

c
o
n
v
e
r
t
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Documentation conventions RM0008
46/1093 Doc ID 13902 Rev 13
2 Documentation conventions
2.1 List of abbreviations for registers
The following abbreviations are used in register descriptions:

2.2 Glossary
Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx
microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx
microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
High-density devices are STM32F101xx and STM32F103xx microcontrollers where
the Flash memory density ranges between 256 and 512 Kbytes.
XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the
Flash memory density ranges between 768 Kbytes and 1 Mbyte.
Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
Word: data of 32-bit length.
Half-word: data of 16-bit length.
Byte: data of 8-bit length.
2.3 Peripheral availability
For peripheral availability and number across all STM32F10xxx sales types, please refer to
the low-, medium-, high- and XL-density STM32F101xx and STM32F103xx datasheets, to
the low- and medium-density STM32F102xx datasheets and to the connectivity line devices,
STM32F105xx/STM32F107xx.
read/write (rw) Software can read and write to these bits.
read-only (r) Software can only read these bits.
write-only (w) Software can only write to this bit. Reading the bit returns the reset value.
read/clear (rc_w1) Software can read as well as clear this bit by writing 1. Writing 0 has no effect on
the bit value.
read/clear (rc_w0) Software can read as well as clear this bit by writing 0. Writing 1 has no effect on
the bit value.
read/clear by read
(rc_r)
Software can read this bit. Reading this bit automatically clears it to 0. Writing 0
has no effect on the bit value.
read/set (rs) Software can read as well as set this bit. Writing 0 has no effect on the bit value.
read-only write
trigger (rt_w)
Software can read this bit. Writing 0 or 1 triggers an event but has no effect on
the bit value.
toggle (t) Software can only toggle this bit by writing 1. Writing 0 has no effect.
Reserved (Res.) Reserved bit, must be kept at reset value.
RM0008 Memory and bus architecture
Doc ID 13902 Rev 13 47/1093

3 Memory and bus architecture
3.1 System architecture
In low-, medium-, high- and XL-density devices, the main system consists of:
Four masters:
Cortex-M3 core DCode bus (D-bus) and System bus (S-bus)
GP-DMA1 & 2 (general-purpose DMA)
Four slaves:
Internal SRAM
Internal Flash memory
FSMC
AHB to APBx (APB1 or APB2), which connect all the APB peripherals
These are interconnected using a multilayer AHB bus architecture as shown in Figure 1:
Figure 1. System architecture
FLITF
Ch.1
Ch.2
Ch.7
Cortex-M3
DMA1
ICode
DCode
System
AHB system bus
DMA Request
APB1
Flash
Bridge 2
Bridge 1
Ch.1
Ch.2
Ch.5
DMA2
SRAM
FSMC
SDIO
APB2
DMA request
ADC3
GPIOC
USART1
TIM8
SPI1
TIM1
ADC2
ADC1
GPIOG
GPIOF
GPIOE
GPIOD
GPIOB
GPIOA
EXTI
AFIO
DAC SPI3/I2S
TIM2
PWR
BKP
bxCAN
USB
I2C2
I2C1
UART5
UART4
USART3
USART2
SPI2/I2S
IWDG
WWDG
RTC
TIM7
TIM6
TIM5
TIM4
TIM3
ai14800c
B
u
s

m
a
t
r
i
x
DMA
D
M
A Reset & clock
control (RCC)

Memory and bus architecture RM0008
48/1093 Doc ID 13902 Rev 13
In connectivity line devices the main system consists of:
Five masters:
Cortex-M3 core DCode bus (D-bus) and System bus (S-bus)
GP-DMA1 & 2 (general-purpose DMA)
Ethernet DMA
Three slaves:
Internal SRAM
Internal Flash memory
AHB to APB bridges (AHB to APBx), which connect all the APB peripherals
These are interconnected using a multilayer AHB bus architecture as shown in Figure 2:
Figure 2. System architecture in connectivity line devices
ICode bus
This bus connects the Instruction bus of the Cortex-M3 core to the Flash memory
instruction interface. Prefetching is performed on this bus.
FLITF
Ch.1
Ch.2
Ch.7
Cortex-M3
DMA1
ICode
DCode
System
DMA request
APB1
Flash
Bridge 2
Bridge 1
Ch.1
Ch.2
Ch.5
DMA2
SRAM
APB2
GPIOC
USART1
SPI1
TIM1
ADC2
ADC1
GPIOE
GPIOD
GPIOB
GPIOA
EXTI
AFIO
DAC SPI3/I2S
TIM2
PWR
BKP
CAN1
CAN2
I2C2
I2C1
UART5
UART4
USART3
USART2
SPI2/I2S
IWDG
WWDG
RTC
TIM7
TIM6
TIM5
TIM4
TIM3
ai15810
B
u
s

m
a
t
r
i
x
DMA
D
M
A
Reset & clock
control (RCC)
USB OTG FS
AHB system bus
Ethernet MAC
D
M
A
DMA request
RM0008 Memory and bus architecture
Doc ID 13902 Rev 13 49/1093

DCode bus
This bus connects the DCode bus (literal load and debug access) of the Cortex-M3 core
to the Flash memory Data interface.
System bus
This bus connects the system bus of the Cortex-M3 core (peripherals bus) to a BusMatrix
which manages the arbitration between the core and the DMA.
DMA bus
This bus connects the AHB master interface of the DMA to the BusMatrix which manages
the access of CPU DCode and DMA to SRAM, Flash memory and peripherals.
BusMatrix
The BusMatrix manages the access arbitration between the core system bus and the DMA
master bus. The arbitration uses a Round Robin algorithm. In connectivity line devices, the
BusMatrix is composed of five masters (CPU DCode, System bus, Ethernet DMA, DMA1
and DMA2 bus) and three slaves (FLITF, SRAM and AHB2APB bridges). In other devices,
the BusMatrix is composed of four masters (CPU DCode, System bus, DMA1 bus and
DMA2 bus) and four slaves (FLITF, SRAM, FSMC and AHB2APB bridges).
AHB peripherals are connected on system bus through a BusMatrix to allow DMA access.
AHB/APB bridges (APB)
The two AHB/APB bridges provide full synchronous connections between the AHB and the
2 APB buses. APB1 is limited to 36 MHz, APB2 operates at full speed (up to 72 MHz
depending on the device).
Refer to Table 3 on page 50 for the address mapping of the peripherals connected to each
bridge.
After each device reset, all peripheral clocks are disabled (except for the SRAM and FLITF).
Before using a peripheral you have to enable its clock in the RCC_AHBENR,
RCC_APB2ENR or RCC_APB1ENR register.
Note: When a 16- or 8-bit access is performed on an APB register, the access is transformed into
a 32-bit access: the bridge duplicates the 16- or 8-bit data to feed the 32-bit vector.
3.2 Memory organization
Program memory, data memory, registers and I/O ports are organized within the same linear
4-Gbyte address space.
The bytes are coded in memory in Little Endian format. The lowest numbered byte in a word
is considered the words least significant byte and the highest numbered byte the most
significant.
For the detailed mapping of peripheral registers, please refer to the related chapters.
The addressable memory space is divided into 8 main blocks, each of 512 MB.
All the memory areas that are not allocated to on-chip memories and peripherals are
considered Reserved). Refer to the Memory map figure in the corresponding product
datasheet.

Memory and bus architecture RM0008
50/1093 Doc ID 13902 Rev 13
3.3 Memory map
See the datasheet corresponding to your device for a comprehensive diagram of the
memory map. Table 3 gives the boundary addresses of the peripherals available in all
STM32F10xxx devices.

Table 3. Register boundary addresses
Boundary address Peripheral Bus Register map
0xA000 0000 - 0xA000 0FFF FSMC
AHB
Section 21.6.9 on page 537
0x5000 0000 - 0x5003 FFFF USB OTG FS Section 28.16.6 on page 882
0x4003 0000 - 0x4FFF FFFF Reserved
0x4002 8000 - 0x4002 9FFF Ethernet Section 29.8.5 on page 1039
0x4002 3400 - 0x4002 7FFF Reserved
0x4002 3000 - 0x4002 33FF CRC Section 4.4.4 on page 64
0x4002 2000 - 0x4002 23FF Flash memory interface
0x4002 1400 - 0x4002 1FFF Reserved
0x4002 1000 - 0x4002 13FF Reset and clock control RCC Section 7.3.11 on page 119
0x4002 0800 - 0x4002 0FFF Reserved
0x4002 0400 - 0x4002 07FF DMA2 Section 13.4.7 on page 280
0x4002 0000 - 0x4002 03FF DMA1 Section 13.4.7 on page 280
0x4001 8400 - 0x4001 7FFF Reserved
0x4001 8000 - 0x4001 83FF SDIO Section 28.9.16 on page 995
RM0008 Memory and bus architecture
Doc ID 13902 Rev 13 51/1093

0x4001 5800 - 0x4001 7FFF Reserved
APB2
0x4001 5400 - 0x4001 57FF TIM11 timer Section 16.6.11 on page 447
0x4001 5000 - 0x4001 53FF TIM10 timer Section 16.6.11 on page 447
0x4001 4C00 - 0x4001 4FFF TIM9 timer Section 16.5.13 on page 438
0x4001 4000 - 0x4001 4BFF Reserved
0x4001 3C00 - 0x4001 3FFF ADC3 Section 11.12.15 on page 243
0x4001 3800 - 0x4001 3BFF USART1 Section 27.6.8 on page 797
0x4001 3400 - 0x4001 37FF TIM8 timer Section 14.4.21 on page 347
0x4001 3000 - 0x4001 33FF SPI1 Section 25.5 on page 712
0x4001 2C00 - 0x4001 2FFF TIM1 timer Section 14.4.21 on page 347
0x4001 2800 - 0x4001 2BFF ADC2 Section 11.12.15 on page 243
0x4001 2400 - 0x4001 27FF ADC1 Section 11.12.15 on page 243
0x4001 2000 - 0x4001 23FF GPIO Port G Section 9.5 on page 188
0x4001 1C00 - 0x4001 1FFF GPIO Port F Section 9.5 on page 188
0x4001 1800 - 0x4001 1BFF GPIO Port E Section 9.5 on page 188
0x4001 1400 - 0x4001 17FF GPIO Port D Section 9.5 on page 188
0x4001 1000 - 0x4001 13FF GPIO Port C Section 9.5 on page 188
0x4001 0C00 - 0x4001 0FFF GPIO Port B Section 9.5 on page 188
0x4001 0800 - 0x4001 0BFF GPIO Port A Section 9.5 on page 188
0x4001 0400 - 0x4001 07FF EXTI Section 10.3.7 on page 205
0x4001 0000 - 0x4001 03FF AFIO Section 9.5 on page 188
Table 3. Register boundary addresses (continued)
Boundary address Peripheral Bus Register map

Memory and bus architecture RM0008
52/1093 Doc ID 13902 Rev 13
0x4000 7800 - 0x4000 FFFF Reserved
APB1
0x4000 7400 - 0x4000 77FF DAC Section 12.5.14 on page 264
0x4000 7000 - 0x4000 73FF Power control PWR Section 5.4.3 on page 78
0x4000 6C00 - 0x4000 6FFF Backup registers (BKP) Section 6.4.5 on page 83
0x4000 6800 - 0x4000 6BFF Reserved
0x4000 6400 - 0x4000 67FF bxCAN1 Section 24.9.5 on page 667
0x4000 6800 - 0x4000 6BFF bxCAN2 Section 24.9.5 on page 667
0x4000 6000
(1)
- 0x4000 63FF Shared USB/CAN SRAM 512 bytes
0x4000 5C00 - 0x4000 5FFF USB device FS registers Section 23.5.4 on page 624
0x4000 5800 - 0x4000 5BFF I2C2 Section 26.6.10 on page 754
0x4000 5400 - 0x4000 57FF I2C1 Section 26.6.10 on page 754
0x4000 5000 - 0x4000 53FF UART5 Section 27.6.8 on page 797
0x4000 4C00 - 0x4000 4FFF UART4 Section 27.6.8 on page 797
0x4000 4800 - 0x4000 4BFF USART3 Section 27.6.8 on page 797
0x4000 4400 - 0x4000 47FF USART2 Section 27.6.8 on page 797
0x4000 4000 - 0x4000 43FF Reserved
0x4000 3C00 - 0x4000 3FFF SPI3/I2S Section 25.5 on page 712
0x4000 3800 - 0x4000 3BFF SPI2/I2S Section 25.5 on page 712
0x4000 3400 - 0x4000 37FF Reserved
0x4000 3000 - 0x4000 33FF Independent watchdog (IWDG) Section 19.4.5 on page 477
0x4000 2C00 - 0x4000 2FFF Window watchdog (WWDG) Section 20.6.4 on page 484
0x4000 2800 - 0x4000 2BFF RTC Section 18.4.7 on page 472
0x4000 2400 - 0x4000 27FF Reserved
0x4000 2000 - 0x4000 23FF TIM14 timer Section 16.6.11 on page 447
0x4000 1C00 - 0x4000 1FFF TIM13 timer Section 16.6.11 on page 447
0x4000 1800 - 0x4000 1BFF TIM12 timer Section 16.5.13 on page 438
0x4000 1400 - 0x4000 17FF TIM7 timer Section 17.4.9 on page 460
0x4000 1000 - 0x4000 13FF TIM6 timer Section 17.4.9 on page 460
0x4000 0C00 - 0x4000 0FFF TIM5 timer Section 15.4.19 on page 405
0x4000 0800 - 0x4000 0BFF TIM4 timer Section 15.4.19 on page 405
0x4000 0400 - 0x4000 07FF TIM3 timer Section 15.4.19 on page 405
0x4000 0000 - 0x4000 03FF TIM2 timer Section 15.4.19 on page 405
1. This shared SRAM can be fully accessed only in low-, medium-, high- and XL-density devices, not in connectivity line
devices.
Table 3. Register boundary addresses (continued)
Boundary address Peripheral Bus Register map
RM0008 Memory and bus architecture
Doc ID 13902 Rev 13 53/1093

3.3.1 Embedded SRAM
The STM32F10xxx features up to 96 Kbytes of static SRAM. It can be accessed as bytes,
half-words (16 bits) or full words (32 bits). The SRAM start address is 0x2000 0000.
3.3.2 Bit banding
The Cortex-M3 memory map includes two bit-band regions. These regions map each
word in an alias region of memory to a bit in a bit-band region of memory. Writing to a word
in the alias region has the same effect as a read-modify-write operation on the targeted bit in
the bit-band region.
In the STM32F10xxx both peripheral registers and SRAM are mapped in a bit-band region.
This allows single bit-band write and read operations to be performed. The operations are
only available for Cortex-M3 accesses, not from other bus masters (e.g. DMA).
A mapping formula shows how to reference each word in the alias region to a corresponding
bit in the bit-band region. The mapping formula is:
bit_word_addr = bit_band_base + (byte_offset x 32) + (bit_number 4)
where:
bit_word_addr is the address of the word in the alias memory region that maps to the
targeted bit.
bit_band_base is the starting address of the alias region
byte_offset is the number of the byte in the bit-band region that contains the targeted bit
bit_number is the bit position (0-7) of the targeted bit.
Example:
The following example shows how to map bit 2 of the byte located at SRAM address
0x20000300 in the alias region:
0x22006008 = 0x22000000 + (0x300*32) + (2*4).
Writing to address 0x22006008 has the same effect as a read-modify-write operation on bit
2 of the byte at SRAM address 0x20000300.
Reading address 0x22006008 returns the value (0x01 or 0x00) of bit 2 of the byte at SRAM
address 0x20000300 (0x01: bit set; 0x00: bit reset).
For more information on Bit-Banding, please refer to the Cortex-M3 Technical Reference
Manual.

Memory and bus architecture RM0008
54/1093 Doc ID 13902 Rev 13
3.3.3 Embedded Flash memory
The high-performance Flash memory module has the following key features:
For XL-density devices: density of up to 1 Mbyte with dual bank architecture for read-
while-write (RWW) capability:
bank 1: fixed size of 512 Kbytes
bank 2: up to 512 Kbytes
For other devices: density of up to 512 Kbytes
Memory organization: the Flash memory is organized as a main block and an
information block:
Main memory block of size:
up to 128 Kbytes 64 bits divided into 512 pages of 2 Kbytes each (see Table 8)
for XL-density devices
up to 4 Kb 64 bits divided into 32 pages of 1 Kbyte each for low-density devices
(see Table 4)
up to 16 Kb 64 bits divided into 128 pages of 1 Kbyte each for medium-density
devices (see Table 5)
up to 64 Kb 64 bits divided into 256 pages of 2 Kbytes each (see Table 6) for
high-density devices
up to 32 Kbit 64 bits divided into 128 pages of 2 Kbytes each (see Table 7) for
connectivity line devices
Information block of size:
770 64 bits for XL-density devices (see Table 8)
2360 64 bits for connectivity line devices (see Table 7)
258 64 bits for other devices (see Table 4, Table 5 and Table 6)
The Flash memory interface (FLITF) features:
Read interface with prefetch buffer (2x64-bit words)
Option byte Loader
Flash Program / Erase operation
Read / Write protection

Table 4. Flash module organization (low-density devices)
Block Name Base addresses Size (bytes)
Main memory
Page 0 0x0800 0000 - 0x0800 03FF 1 Kbyte
Page 1 0x0800 0400 - 0x0800 07FF 1 Kbyte
Page 2 0x0800 0800 - 0x0800 0BFF 1 Kbyte
Page 3 0x0800 0C00 - 0x0800 0FFF 1 Kbyte
Page 4 0x0800 1000 - 0x0800 13FF 1 Kbyte
.
.
.
.
.
.
.
.
.
Page 31 0x0800 7C00 - 0x0800 7FFF 1 Kbyte
RM0008 Memory and bus architecture
Doc ID 13902 Rev 13 55/1093


Information block
System memory 0x1FFF F000 - 0x1FFF F7FF 2 Kbytes
Option Bytes 0x1FFF F800 - 0x1FFF F80F 16
Flash memory
interface
registers
FLASH_ACR 0x4002 2000 - 0x4002 2003 4
FLASH_KEYR 0x4002 2004 - 0x4002 2007 4
FLASH_OPTKEYR 0x4002 2008 - 0x4002 200B 4
FLASH_SR 0x4002 200C - 0x4002 200F 4
FLASH_CR 0x4002 2010 - 0x4002 2013 4
FLASH_AR 0x4002 2014 - 0x4002 2017 4
Reserved 0x4002 2018 - 0x4002 201B 4
FLASH_OBR 0x4002 201C - 0x4002 201F 4
FLASH_WRPR 0x4002 2020 - 0x4002 2023 4
Table 5. Flash module organization (medium-density devices)
Block Name Base addresses Size (bytes)
Main memory
Page 0 0x0800 0000 - 0x0800 03FF 1 Kbyte
Page 1 0x0800 0400 - 0x0800 07FF 1 Kbyte
Page 2 0x0800 0800 - 0x0800 0BFF 1 Kbyte
Page 3 0x0800 0C00 - 0x0800 0FFF 1 Kbyte
Page 4 0x0800 1000 - 0x0800 13FF 1 Kbyte
.
.
.
.
.
.
.
.
.
Page 127 0x0801 FC00 - 0x0801 FFFF 1 Kbyte
Information block
System memory 0x1FFF F000 - 0x1FFF F7FF 2 Kbytes
Option Bytes 0x1FFF F800 - 0x1FFF F80F 16
Flash memory
interface
registers
FLASH_ACR 0x4002 2000 - 0x4002 2003 4
FLASH_KEYR 0x4002 2004 - 0x4002 2007 4
FLASH_OPTKEYR 0x4002 2008 - 0x4002 200B 4
FLASH_SR 0x4002 200C - 0x4002 200F 4
FLASH_CR 0x4002 2010 - 0x4002 2013 4
FLASH_AR 0x4002 2014 - 0x4002 2017 4
Reserved 0x4002 2018 - 0x4002 201B 4
FLASH_OBR 0x4002 201C - 0x4002 201F 4
FLASH_WRPR 0x4002 2020 - 0x4002 2023 4
Table 4. Flash module organization (low-density devices) (continued)
Block Name Base addresses Size (bytes)

Memory and bus architecture RM0008
56/1093 Doc ID 13902 Rev 13

Table 6. Flash module organization (high-density devices)
Block Name Base addresses Size (bytes)
Main memory
Page 0 0x0800 0000 - 0x0800 07FF 2 Kbytes
Page 1 0x0800 0800 - 0x0800 0FFF 2 Kbytes
Page 2 0x0800 1000 - 0x0800 17FF 2 Kbytes
Page 3 0x0800 1800 - 0x0800 1FFF 2 Kbytes
.
.
.
.
.
.
.
.
.
Page 255 0x0807 F800 - 0x0807 FFFF 2 Kbytes
Information block
System memory 0x1FFF F000 - 0x1FFF F7FF 2 Kbytes
Option Bytes 0x1FFF F800 - 0x1FFF F80F 16
Flash memory
interface
registers
FLASH_ACR 0x4002 2000 - 0x4002 2003 4
FLASH_KEYR 0x4002 2004 - 0x4002 2007 4
FLASH_OPTKEYR 0x4002 2008 - 0x4002 200B 4
FLASH_SR 0x4002 200C - 0x4002 200F 4
FLASH_CR 0x4002 2010 - 0x4002 2013 4
FLASH_AR 0x4002 2014 - 0x4002 2017 4
Reserved 0x4002 2018 - 0x4002 201B 4
FLASH_OBR 0x4002 201C - 0x4002 201F 4
FLASH_WRPR 0x4002 2020 - 0x4002 2023 4
RM0008 Memory and bus architecture
Doc ID 13902 Rev 13 57/1093



Table 7. Flash module organization (connectivity line devices)
Block Name Base addresses Size (bytes)
Main memory
Page 0 0x0800 0000 - 0x0800 07FF 2 Kbytes
Page 1 0x0800 0800 - 0x0800 0FFF 2 Kbytes
Page 2 0x0800 1000 - 0x0800 17FF 2 Kbytes
Page 3 0x0800 1800 - 0x0800 1FFF 2 Kbytes
.
.
.
.
.
.
.
.
.
Page 127 0x0803 F800 - 0x0803 FFFF 2 Kbytes
Information block
System memory 0x1FFF B000 - 0x1FFF F7FF 18 Kbytes
Option Bytes 0x1FFF F800 - 0x1FFF F80F 16
Flash memory
interface
registers
FLASH_ACR 0x4002 2000 - 0x4002 2003 4
FLASH_KEYR 0x4002 2004 - 0x4002 2007 4
FLASH_OPTKEYR 0x4002 2008 - 0x4002 200B 4
FLASH_SR 0x4002 200C - 0x4002 200F 4
FLASH_CR 0x4002 2010 - 0x4002 2013 4
FLASH_AR 0x4002 2014 - 0x4002 2017 4
Reserved 0x4002 2018 - 0x4002 201B 4
FLASH_OBR 0x4002 201C - 0x4002 201F 4
FLASH_WRPR 0x4002 2020 - 0x4002 2023 4
Table 8. XL-density Flash module organization
Block Name Base addresses Size (bytes)
Main memory
Bank 1
Page 0 0x0800 0000 - 0x0800 07FF 2 Kbytes
Page 1 0x0800 0800 - 0x0800 0FFF 2 Kbytes
... ... ...
Page 255 0x0807 F800 - 0x0807 FFFF 2 Kbytes
Bank 2
Page 256 0x0808 0000 - 0x0808 07FF 2 Kbytes
Page 257 0x0808 0800 - 0x0808 0FFF 2 Kbytes
.
.
.
.
.
.
.
.
.
Page 511 0x080F F800 - 0x080F FFFF 2 Kbytes
Information block
System memory 0x1FFF E000 - 0x1FFF F7FF 6 Kbytes
Option bytes 0x1FFF F800 - 0x1FFF F80F 16

Memory and bus architecture RM0008
58/1093 Doc ID 13902 Rev 13
Note: For further information on the Flash memory interface registers, please refer to the:
STM32F10xxx XL-density Flash programming manual (PM0068) for XL-density
devices
STM32F10xxx Flash programming manual (PM0042) for other devices
Reading the Flash memory
Flash memory instructions and data access are performed through the AHB bus. The
prefetch block is used for instruction fetches through the ICode bus. Arbitration is performed
in the Flash memory interface, and priority is given to data access on the DCode bus.
Read accesses can be performed with the following configuration options:
Latency: number of wait states for a read operation programmed on-the-fly
Prefetch buffer (2 x 64-bit blocks): it is enabled after reset; a whole block can be
replaced with a single read from the Flash memory as the size of the block matches the
bandwidth of the Flash memory. Thanks to the prefetch buffer, faster CPU execution is
possible as the CPU fetches one word at a time with the next word readily available in
the prefetch buffer
Half cycle: for power optimization
Flash memory interface
registers
FLASH_ACR 0x4002 2000 - 0x4002 2003 4
FLASH_KEYR 0x4002 2004 - 0x4002 2007 4
FLASH_OPTKEYR 0x4002 2008 - 0x4002 200B 4
FLASH_SR 0x4002 200C - 0x4002 200F 4
FLASH_CR 0x4002 2010 - 0x4002 2013 4
FLASH_AR 0x4002 2014 - 0x4002 2017 4
Reserved 0x4002 2018 - 0x4002 201B 4
FLASH_OBR 0x4002 201C - 0x4002 201F 4
FLASH_WRPR 0x4002 2020 - 0x4002 2023 4
Reserved 0x4002 2024 - 0x4002 2043 32
FLASH_KEYR2 0x4002 2044 - 0x4002 2047 4
Reserved 0x4002 2048 - 0x4002 204B 4
FLASH_SR2 0x4002 204C - 0x4002 204F 4
FLASH_CR2 0x4002 2050 - 0x4002 2053 4
FLASH_AR2 0x4002 2054 - 0x4002 2057 4
Table 8. XL-density Flash module organization (continued)
Block Name Base addresses Size (bytes)
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Note: 1 These options should be used in accordance with the Flash memory access time. The wait
states represent the ratio of the SYSCLK (system clock) period to the Flash memory access
time:
zero wait state, if 0 < SYSCLK 24 MHz
one wait state, if 24 MHz < SYSCLK 48 MHz
two wait states, if 48 MHz < SYSCLK 72 MHz
2 Half cycle configuration is not available in combination with a prescaler on the AHB. The
system clock (SYSCLK) should be equal to the HCLK clock. This feature can therefore be
used only with a low-frequency clock of 8 MHz or less. It can be generated from the HSI or
the HSE but not from the PLL.
3 The prefetch buffer must be kept on when using a prescaler different from 1 on the AHB
clock.
4 The prefetch buffer must be switched on/off only when SYSCLK is lower than 24 MHz and
no prescaler is applied on the AHB clock (SYSCLK must be equal to HCLK). The prefetch
buffer is usually switched on/off during the initialization routine, while the microcontroller is
running on the internal 8 MHz RC (HSI) oscillator.
5 Using DMA: DMA accesses Flash memory on the DCode bus and has priority over ICode
instructions. The DMA provides one free cycle after each transfer. Some instructions can be
performed together with DMA transfer.
Programming and erasing the Flash memory
The Flash memory can be programmed 16 bits (half words) at a time.
For write and erase operations on the Flash memory (write/erase), the internal RC oscillator
(HSI) must be ON.
The Flash memory erase operation can be performed at page level or on the whole Flash
area (mass-erase). The mass-erase does not affect the information blocks.
To ensure that there is no over-programming, the Flash Programming and Erase Controller
blocks are clocked by a fixed clock.
The End of write operation (programming or erasing) can trigger an interrupt. This interrupt
can be used to exit from WFI mode, only if the FLITF clock is enabled. Otherwise, the
interrupt is served only after an exit from WFI.
The FLASH_ACR register is used to enable/disable prefetch and half cycle access, and to
control the Flash memory access time according to the CPU frequency. The tables below
provide the bit map and bit descriptions for this register.
For complete information on Flash memory operations and register configurations, please
refer to the STM32F10xxx Flash programming manual (PM0042) or to the XL
STM32F10xxx Flash programming manual (PM0068).

Memory and bus architecture RM0008
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Flash access control register (FLASH_ACR)
Address offset: 0x00
Reset value: 0x0000 0030

3.4 Boot configuration
In the STM32F10xxx, 3 different boot modes can be selected through BOOT[1:0] pins as
shown in Table 9.

The values on the BOOT pins are latched on the 4th rising edge of SYSCLK after a reset. It
is up to the user to set the BOOT1 and BOOT0 pins after Reset to select the required boot
mode.
The BOOT pins are also re-sampled when exiting from Standby mode. Consequently they
must be kept in the required Boot mode configuration in Standby mode. After this startup
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
PRFTBS PRFTBE HLFCYA LATENCY
r rw rw rw rw rw
Bits 31:6 Reserved, must be kept at reset value.
Bit 5 PRFTBS: Prefetch buffer status
This bit provides the status of the prefetch buffer.
0: Prefetch buffer is disabled
1: Prefetch buffer is enabled
Bit 4 PRFTBE: Prefetch buffer enable
0: Prefetch is disabled
1: Prefetch is enabled
Bit 3 HLFCYA: Flash half cycle access enable
0: Half cycle is disabled
1: Half cycle is enabled
Bits 2:0 LATENCY: Latency
These bits represent the ratio of the SYSCLK (system clock) period to the Flash access
time.
000 Zero wait state, if 0 < SYSCLK 24 MHz
001 One wait state, if 24 MHz < SYSCLK 48 MHz
010 Two wait states, if 48 MHz < SYSCLK 72 MHz
Table 9. Boot modes
Boot mode selection pins
Boot mode Aliasing
BOOT1 BOOT0
x 0 Main Flash memory Main Flash memory is selected as boot space
0 1 System memory System memory is selected as boot space
1 1 Embedded SRAM Embedded SRAM is selected as boot space
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delay has elapsed, the CPU fetches the top-of-stack value from address 0x0000 0000, then
starts code execution from the boot memory starting from 0x0000 0004.
Due to its fixed memory map, the code area starts from address 0x0000 0000 (accessed
through the ICode/DCode buses) while the data area (SRAM) starts from address
0x2000 0000 (accessed through the system bus). The Cortex-M3 CPU always fetches the
reset vector on the ICode bus, which implies to have the boot space available only in the
code area (typically, Flash memory). STM32F10xxx microcontrollers implement a special
mechanism to be able to boot also from SRAM and not only from main Flash memory and
System memory.
Depending on the selected boot mode, main Flash memory, system memory or SRAM is
accessible as follows:
Boot from main Flash memory: the main Flash memory is aliased in the boot memory
space (0x0000 0000), but still accessible from its original memory space (0x800 0000).
In other words, the Flash memory contents can be accessed starting from address
0x0000 0000 or 0x800 0000.
Boot from system memory: the system memory is aliased in the boot memory space
(0x0000 0000), but still accessible from its original memory space (0x1FFF B000 in
connectivity line devices, 0x1FFF F000 in other devices).
Boot from the embedded SRAM: SRAM is accessible only at address 0x2000 0000.
Note: When booting from SRAM, in the application initialization code, you have to relocate the
vector table in SRAM using the NVIC exception table and offset register.
For XL-density devices, when booting from the main Flash memory, you have an option to
boot from any of two memory banks. By default, boot from Flash memory bank 1 is selected.
You can choose to boot from Flash memory bank 2 by clearing the BFB2 bit in the user
option bytes. When this bit is cleared and the boot pins are in the boot from main Flash
memory configuration, the device boots from system memory, and the boot loader jumps to
execute the user application programmed in Flash memory bank 2. For further details,
please refer to AN2606.
Note: When booting from Bank2, in the applications initialization code, you have to relocate the
vector table to the Bank2 base address. (0x0808 0000) using the NVIC exception table and
offset register.
Embedded boot loader
The embedded boot loader is located in the System memory, programmed by ST during
production. It is used to reprogram the Flash memory with one of the available serial
interfaces:
In low-, medium- and high-density devices the bootoader is activated through the
USART1 interface.
In XL-density devices the boot loader is activated through the following interfaces:
USART1 or USART2 (remapped).
In connectivity line devices the boot loader can be activated through one of the
following interfaces: USART1, USART2 (remapped), CAN2 (remapped) or USB OTG
FS in Device mode (DFU: device firmware upgrade).
The USART peripheral operates with the internal 8 MHz oscillator (HSI). The CAN and
USB OTG FS, however, can only function if an external 8 MHz, 14.7456 MHz or
25 MHz clock (HSE) is present.
Note: For further details, please refer to AN2606.
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4 CRC calculation unit
Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx
microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx
microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
High-density devices are STM32F101xx and STM32F103xx microcontrollers where the
Flash memory density ranges between 256 and 512 Kbytes.
XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the
Flash memory density ranges between 768 Kbytes and 1 Mbyte.
Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
This section applies to the whole STM32F10xxx family, unless otherwise specified.
4.1 CRC introduction
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a fixed generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link-
time and stored at a given memory location.
4.2 CRC main features
Uses CRC-32 (Ethernet) polynomial: 0x4C11DB7
X
32
+ X
26
+ X
23
+ X
22
+ X
16
+ X
12
+ X
11
+ X
10
+X
8
+ X
7
+ X
5
+ X
4
+ X
2
+ X +1
Single input/output 32-bit data register
CRC computation done in 4 AHB clock cycles (HCLK)
General-purpose 8-bit register (can be used for temporary storage)
The block diagram is shown in Figure 3.
Figure 3. CRC calculation unit block diagram
AHB bus
32-bit (read access)
Data register (output)
CRC computation (polynomial: 0x4C11DB7)
32-bit (write access)
Data register (input)
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4.3 CRC functional description
The CRC calculation unit mainly consists of a single 32-bit data register, which:
is used as an input register to enter new data in the CRC calculator (when writing into
the register)
holds the result of the previous CRC calculation (when reading the register)
Each write operation into the data register creates a combination of the previous CRC value
and the new one (CRC computation is done on the whole 32-bit data word, and not byte per
byte).
The write operation is stalled until the end of the CRC computation, thus allowing back-to-
back write accesses or consecutive write and read accesses.
The CRC calculator can be reset to 0xFFFF FFFF with the RESET control bit in the
CRC_CR register. This operation does not affect the contents of the CRC_IDR register.
4.4 CRC registers
The CRC calculation unit contains two data registers and a control register.
4.4.1 Data register (CRC_DR)
Address offset: 0x00
Reset value: 0xFFFF FFFF

4.4.2 Independent data register (CRC_IDR)
Address offset: 0x04
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DR [31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR [15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:0 Data register bits
Used as an input register when writing new data into the CRC calculator.
Holds the previous CRC calculation result when it is read.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
IDR[7:0]
rw rw rw rw rw rw rw rw
Bits 31:8 Reserved, must be kept at reset value.
CRC calculation unit RM0008
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4.4.3 Control register (CRC_CR)
Address offset: 0x08
Reset value: 0x0000 0000

4.4.4 CRC register map
The following table provides the CRC register map and reset values.

Bits 7:0 General-purpose 8-bit data register bits
Can be used as a temporary storage location for one byte.
This register is not affected by CRC resets generated by the RESET bit in the CRC_CR
register.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
RESET
w
Bits 31:1 Reserved, must be kept at reset value.
Bit 0 RESET bit
Resets the CRC calculation unit and sets the data register to 0xFFFF FFFF.
This bit can only be set, it is automatically cleared by hardware.
Table 10. CRC calculation unit register map and reset values
Offset Register 31-24 23-16 15-8 7 6 5 4 3 2 1 0
0x00
CRC_DR
Reset value
Data register
0xFFFF FFFF
0x04
CRC_IDR
Reset value
Reserved
Independent data register
0x00
0x08
CRC_CR
Reset value
Reserved
RESET
0
RM0008 Power control (PWR)
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5 Power control (PWR)
Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx
microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx
microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
High-density devices are STM32F101xx and STM32F103xx microcontrollers where the
Flash memory density ranges between 256 and 512 Kbytes.
XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the
Flash memory density ranges between 768 Kbytes and 1 Mbyte.
Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
This section applies to the whole STM32F101xx family, unless otherwise specified.
5.1 Power supplies
The device requires a 2.0-to-3.6 V operating voltage supply (V
DD
). An embedded regulator
is used to supply the internal 1.8 V digital power.
The real-time clock (RTC) and backup registers can be powered from the V
BAT
voltage when
the main V
DD
supply is powered off.

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Figure 4. Power supply overview
Note: 1 V
DDA
and V
SSA
must be connected to V
DD
and V
SS
, respectively.
5.1.1 Independent A/D and D/A converter supply and reference voltage
To improve conversion accuracy, the ADC and the DAC have an independent power supply
which can be separately filtered and shielded from noise on the PCB.
The ADC and DAC voltage supply input is available on a separate V
DDA
pin.
An isolated supply ground connection is provided on pin V
SSA
.
When available (according to package), V
REF-
must be tied to V
SSA
.
On 100-pin and 144-pin packages
To ensure a better accuracy on low-voltage inputs and outputs, the user can connect a
separate external reference voltage on V
REF+
. V
REF+
is the highest voltage, represented by
the full scale value, for an analog input (ADC) or output (DAC) signal. The voltage on V
REF+

can range from 2.4 V to V
DDA
.
On 64-pin packages and packages with less pins
The V
REF+
and V
REF-
pins are not available, they are internally connected to the ADC
voltage supply (V
DDA
) and ground (V
SSA
).
A/D converter
V
DDA
V
DD
V
SSA
V
REF+
V
BAT
V
SS
I/O Ring

(V
DD
)
(from 2.4 V up to V
DDA
)
BKP registers
Temp. sensor
Reset block
Standby circuitry
PLL
(Wakeup logic,
IWDG)
RTC
Voltage Regulator
Core
Memories
digital
peripherals
Low voltage detector
V
REF-
V
DDA
domain
V
DD
domain 1.8 V domain
Backup domain
LSE crystal 32K osc
RCC BDCR register
(V
SSA
)
(V
SS
)
D/A converter
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5.1.2 Battery backup domain
To retain the content of the Backup registers and supply the RTC function when V
DD
is
turned off, V
BAT
pin can be connected to an optional standby voltage supplied by a battery or
by another source.
The V
BAT
pin powers the RTC unit, the LSE oscillator and the PC13 to PC15 IOs, allowing
the RTC to operate even when the main digital supply (V
DD
) is turned off. The switch to the
V
BAT
supply is controlled by the Power Down Reset embedded in the Reset block.
Warning: During t
RSTTEMPO
(temporization at V
DD
startup) or after a PDR
is detected, the power switch between V
BAT
and V
DD
remains
connected to V
BAT
.
During the startup phase, if V
DD
is established in less than
t
RSTTEMPO
(Refer to the datasheet for the value of t
RSTTEMPO
)
and V
DD
> V
BAT
+ 0.6 V, a current may be injected into V
BAT

through an internal diode connected between V
DD
and the
power switch (V
BAT
).
If the power supply/battery connected to the V
BAT
pin cannot
support this current injection, it is strongly recommended to
connect an external low-drop diode between this power
supply and the V
BAT
pin.
If no external battery is used in the application, it is recommended to connect V
BAT
externally to V
DD
with a 100 nF external ceramic decoupling capacitor (for more details refer
to AN2586).
When the backup domain is supplied by V
DD
(analog switch connected to V
DD
), the
following functions are available:
PC14 and PC15 can be used as either GPIO or LSE pins
PC13 can be used as GPIO, TAMPER pin, RTC Calibration Clock, RTC Alarm or
second output (refer to Section 6: Backup registers (BKP) on page 79)
Note: Due to the fact that the switch only sinks a limited amount of current (3 mA), the use of
GPIOs PC13 to PC15 in output mode is restricted: the speed has to be limited to 2 MHz with
a maximum load of 30 pF and these IOs must not be used as a current source (e.g. to drive
an LED).
When the backup domain is supplied by V
BAT
(analog switch connected to V
BAT
because
V
DD
is not present), the following functions are available:
PC14 and PC15 can be used as LSE pins only
PC13 can be used as TAMPER pin, RTC Alarm or Second output (refer to section
Section 6.4.2: RTC clock calibration register (BKP_RTCCR) on page 81).

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5.1.3 Voltage regulator
The voltage regulator is always enabled after Reset. It works in three different modes
depending on the application modes.
In Run mode, the regulator supplies full power to the 1.8 V domain (core, memories
and digital peripherals).
In Stop mode the regulator supplies low-power to the 1.8 V domain, preserving
contents of registers and SRAM
In Standby Mode, the regulator is powered off. The contents of the registers and SRAM
are lost except for the Standby circuitry and the Backup Domain.
5.2 Power supply supervisor
5.2.1 Power on reset (POR)/power down reset (PDR)
The device has an integrated POR/PDR circuitry that allows proper operation starting
from/down to 2 V.
The device remains in Reset mode when V
DD
/V
DDA
is below a specified threshold,
V
POR/PDR
, without the need for an external reset circuit. For more details concerning the
power on/power down reset threshold, refer to the electrical characteristics of the datasheet.
Figure 5. Power on reset/power down reset waveform
5.2.2 Programmable voltage detector (PVD)
You can use the PVD to monitor the V
DD
/V
DDA
power supply by comparing it to a threshold
selected by the PLS[2:0] bits in the Power control register (PWR_CR).
The PVD is enabled by setting the PVDE bit.
A PVDO flag is available, in the Power control/status register (PWR_CSR), to indicate if
V
DD
/V
DDA
is higher or lower than the PVD threshold. This event is internally connected to
the EXTI line16 and can generate an interrupt if enabled through the EXTI registers. The
V
DD
/V
DDA
Reset
40 mV
hysteresis
POR
PDR
Temporization
t
RSTTEMPO

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PVD output interrupt can be generated when V
DD
/V
DDA
drops below the PVD threshold
and/or when V
DD
/V
DDA
rises above the PVD threshold depending on EXTI line16
rising/falling edge configuration. As an example the service routine could perform
emergency shutdown tasks.
Figure 6. PVD thresholds
V
DD
/V
DDA
PVD output
100 mV
hysteresis
PVD threshold

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5.3 Low-power modes
By default, the microcontroller is in Run mode after a system or a power Reset. Several low-
power modes are available to save power when the CPU does not need to be kept running,
for example when waiting for an external event. It is up to the user to select the mode that
gives the best compromise between low-power consumption, short startup time and
available wakeup sources.
The STM32F10xxx devices feature three low-power modes:
Sleep mode (CPU clock off, all peripherals including Cortex-M3 core peripherals like
NVIC, SysTick, etc. are kept running)
Stop mode (all clocks are stopped)
Standby mode (1.8V domain powered-off)
In addition, the power consumption in Run mode can be reduce by one of the following
means:
Slowing down the system clocks
Gating the clocks to the APB and AHB peripherals when they are unused.

5.3.1 Slowing down system clocks
In Run mode the speed of the system clocks (SYSCLK, HCLK, PCLK1, PCLK2) can be
reduced by programming the prescaler registers. These prescalers can also be used to slow
down peripherals before entering Sleep mode.
For more details refer to Section 7.3.2: Clock configuration register (RCC_CFGR).
Table 11. Low-power mode summary
Mode name Entry wakeup
Effect on 1.8V
domain clocks
Effect on
V
DD

domain
clocks
Voltage
regulator
Sleep
(Sleep now or
Sleep-on -
exit)
WFI Any interrupt CPU clock OFF
no effect on other
clocks or analog
clock sources
None ON
WFE Wakeup event
Stop
PDDS and LPDS
bits +
SLEEPDEEP bit
+ WFI or WFE
Any EXTI line
(configured in the
EXTI registers)
All 1.8V domain
clocks OFF
HSI and
HSE
oscillators
OFF
ON or in low-
power mode
(depends on
Power control
register
(PWR_CR))
Standby
PDDS bit +
SLEEPDEEP bit
+ WFI or WFE
WKUP pin rising
edge, RTC alarm,
external reset in
NRST pin,
IWDG reset
OFF
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5.3.2 Peripheral clock gating
In Run mode, the HCLK and PCLKx for individual peripherals and memories can be stopped
at any time to reduce power consumption.
To further reduce power consumption in Sleep mode the peripheral clocks can be disabled
prior to executing the WFI or WFE instructions.
Peripheral clock gating is controlled by the AHB peripheral clock enable register
(RCC_AHBENR), APB1 peripheral clock enable register (RCC_APB1ENR) and APB2
peripheral clock enable register (RCC_APB2ENR).
5.3.3 Sleep mode
Entering Sleep mode
The Sleep mode is entered by executing the WFI (Wait For Interrupt) or WFE (Wait for
Event) instructions. Two options are available to select the Sleep mode entry mechanism,
depending on the SLEEPONEXIT bit in the Cortex-M3 System Control register:
Sleep-now: if the SLEEPONEXIT bit is cleared, the MCU enters Sleep mode as soon
as WFI or WFE instruction is executed.
Sleep-on-exit: if the SLEEPONEXIT bit is set, the MCU enters Sleep mode as soon as
it exits the lowest priority ISR.
In the Sleep mode, all I/O pins keep the same state as in the Run mode.
Refer to Table 12 and Table 13 for details on how to enter Sleep mode.
Exiting Sleep mode
If the WFI instruction is used to enter Sleep mode, any peripheral interrupt acknowledged by
the nested vectored interrupt controller (NVIC) can wake up the device from Sleep mode.
If the WFE instruction is used to enter Sleep mode, the MCU exits Sleep mode as soon as
an event occurs. The wakeup event can be generated either by:
enabling an interrupt in the peripheral control register but not in the NVIC, and enabling
the SEVONPEND bit in the Cortex-M3 System Control register. When the MCU
resumes from WFE, the peripheral interrupt pending bit and the peripheral NVIC IRQ
channel pending bit (in the NVIC interrupt clear pending register) have to be cleared.
or configuring an external or internal EXTI line in event mode. When the CPU resumes
from WFE, it is not necessary to clear the peripheral interrupt pending bit or the NVIC
IRQ channel pending bit as the pending bit corresponding to the event line is not set.
This mode offers the lowest wakeup time as no time is wasted in interrupt entry/exit.
Refer to Table 12 and Table 13 for more details on how to exit Sleep mode.

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5.3.4 Stop mode
The Stop mode is based on the Cortex-M3 deepsleep mode combined with peripheral clock
gating. The voltage regulator can be configured either in normal or low-power mode. In Stop
mode, all clocks in the 1.8 V domain are stopped, the PLL, the HSI and the HSE RC
oscillators are disabled. SRAM and register contents are preserved.
In the Stop mode, all I/O pins keep the same state as in the Run mode.
Entering Stop mode
Refer to Table 14 for details on how to enter the Stop mode.
To further reduce power consumption in Stop mode, the internal voltage regulator can be
put in low-power mode. This is configured by the LPDS bit of the Power control register
(PWR_CR).
If Flash memory programming is ongoing, the Stop mode entry is delayed until the memory
access is finished.
If an access to the APB domain is ongoing, The Stop mode entry is delayed until the APB
access is finished.
In Stop mode, the following features can be selected by programming individual control bits:
Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by
hardware option. Once started it cannot be stopped except by a Reset. See
Section 19.3: IWDG functional description in Section 19: Independent watchdog
(IWDG).
Table 12. Sleep-now
Sleep-now mode Description
Mode entry
WFI (Wait for Interrupt) or WFE (Wait for Event) while:
SLEEPDEEP = 0 and
SLEEPONEXIT = 0
Refer to the Cortex-M3 System Control register.
Mode exit
If WFI was used for entry:
Interrupt: Refer to Table 63: Vector table for other STM32F10xxx devices
If WFE was used for entry
Wakeup event: Refer to Section 10.2.3: Wakeup event management
Wakeup latency None
Table 13. Sleep-on-exit
Sleep-on-exit Description
Mode entry
WFI (wait for interrupt) while:
SLEEPDEEP = 0 and
SLEEPONEXIT = 1
Refer to the Cortex-M3 System Control register.
Mode exit Interrupt: refer to Table 63: Vector table for other STM32F10xxx devices.
Wakeup latency None
RM0008 Power control (PWR)
Doc ID 13902 Rev 13 73/1093

real-time clock (RTC): this is configured by the RTCEN bit in the Backup domain control
register (RCC_BDCR)
Internal RC oscillator (LSI RC): this is configured by the LSION bit in the Control/status
register (RCC_CSR).
External 32.768 kHz oscillator (LSE OSC): this is configured by the LSEON bit in the
Backup domain control register (RCC_BDCR).
The ADC or DAC can also consume power during the Stop mode, unless they are disabled
before entering it. To disable them, the ADON bit in the ADC_CR2 register and the ENx bit
in the DAC_CR register must both be written to 0.
Exiting Stop mode
Refer to Table 14 for more details on how to exit Stop mode.
When exiting Stop mode by issuing an interrupt or a wakeup event, the HSI RC oscillator is
selected as system clock.
When the voltage regulator operates in low-power mode, an additional startup delay is
incurred when waking up from Stop mode. By keeping the internal regulator ON during Stop
mode, the consumption is higher although the startup time is reduced.

5.3.5 Standby mode
The Standby mode allows to achieve the lowest power consumption. It is based on the
Cortex-M3 deepsleep mode, with the voltage regulator disabled. The 1.8 V domain is
consequently powered off. The PLL, the HSI oscillator and the HSE oscillator are also
switched off. SRAM and register contents are lost except for registers in the Backup domain
and Standby circuitry (see Figure 4).
Table 14. Stop mode
Stop mode Description
Mode entry
WFI (Wait for Interrupt) or WFE (Wait for Event) while:
Set SLEEPDEEP bit in Cortex-M3 System Control register
Clear PDDS bit in Power Control register (PWR_CR)
Select the voltage regulator mode by configuring LPDS bit in PWR_CR
Note: To enter Stop mode, all EXTI Line pending bits (in Pending register
(EXTI_PR)) and RTC Alarm flag must be reset. Otherwise, the Stop mode
entry procedure is ignored and program execution continues.
Mode exit
If WFI was used for entry:
Any EXTI Line configured in Interrupt mode (the corresponding EXTI
Interrupt vector must be enabled in the NVIC). Refer to Table 63: Vector
table for other STM32F10xxx devices on page 196.
If WFE was used for entry:
Any EXTI Line configured in event mode. Refer to Section 10.2.3:
Wakeup event management on page 199
Wakeup latency HSI RC wakeup time + regulator wakeup time from Low-power mode

Power control (PWR) RM0008
74/1093 Doc ID 13902 Rev 13
Entering Standby mode
Refer to Table 15 for more details on how to enter Standby mode.
In Standby mode, the following features can be selected by programming individual control
bits:
Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by
hardware option. Once started it cannot be stopped except by a reset. See
Section 19.3: IWDG functional description in Section 19: Independent watchdog
(IWDG).
real-time clock (RTC): this is configured by the RTCEN bit in the Backup domain control
register (RCC_BDCR)
Internal RC oscillator (LSI RC): this is configured by the LSION bit in the Control/status
register (RCC_CSR).
External 32.768 kHz oscillator (LSE OSC): this is configured by the LSEON bit in the
Backup domain control register (RCC_BDCR)
Exiting Standby mode
The microcontroller exits the Standby mode when an external reset (NRST pin), an IWDG
reset, a rising edge on the WKUP pin or the rising edge of an RTC alarm occurs (see
Figure 179: RTC simplified block diagram). All registers are reset after wakeup from
Standby except for Power control/status register (PWR_CSR).
After waking up from Standby mode, program execution restarts in the same way as after a
Reset (boot pins sampling, vector reset is fetched, etc.). The SBF status flag in the Power
control/status register (PWR_CSR) indicates that the MCU was in Standby mode.
Refer to Table 15 for more details on how to exit Standby mode.

I/O states in Standby mode
In Standby mode, all I/O pins are high impedance except:
Reset pad (still available)
TAMPER pin if configured for tamper or calibration out
WKUP pin, if enabled
Table 15. Standby mode
Standby mode Description
Mode entry
WFI (Wait for Interrupt) or WFE (Wait for Event) while:
Set SLEEPDEEP in Cortex-M3 System Control register
Set PDDS bit in Power Control register (PWR_CR)
Clear WUF bit in Power Control/Status register (PWR_CSR)
Mode exit
WKUP pin rising edge, RTC alarm events rising edge, external Reset in
NRST pin, IWDG Reset.
Wakeup latency Reset phase
RM0008 Power control (PWR)
Doc ID 13902 Rev 13 75/1093

Debug mode
By default, the debug connection is lost if the application puts the MCU in Stop or Standby
mode while the debug features are used. This is due to the fact that the Cortex-M3 core is
no longer clocked.
However, by setting some configuration bits in the DBGMCU_CR register, the software can
be debugged even when using the low-power modes extensively. For more details, refer to
Section 31.16.1: Debug support for low-power modes.
5.3.6 Auto-wakeup (AWU) from low-power mode
The RTC can be used to wakeup the MCU from low-power mode without depending on an
external interrupt (Auto-wakeup mode). The RTC provides a programmable time base for
waking up from Stop or Standby mode at regular intervals. For this purpose, two of the three
alternative RTC clock sources can be selected by programming the RTCSEL[1:0] bits in the
Backup domain control register (RCC_BDCR):
Low-power 32.768 kHz external crystal oscillator (LSE OSC).
This clock source provides a precise time base with very low-power consumption (less
than 1A added consumption in typical conditions)
Low-power internal RC Oscillator (LSI RC)
This clock source has the advantage of saving the cost of the 32.768 kHz crystal. This
internal RC Oscillator is designed to add minimum power consumption.
To wakeup from Stop mode with an RTC alarm event, it is necessary to:
Configure the EXTI Line 17 to be sensitive to rising edge
Configure the RTC to generate the RTC alarm
To wakeup from Standby mode, there is no need to configure the EXTI Line 17.
5.4 Power control registers
The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).
5.4.1 Power control register (PWR_CR)
Address offset: 0x00
Reset value: 0x0000 0000 (reset by wakeup from Standby mode)


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
DBP PLS[2:0] PVDE CSBF CWUF PDDS LPDS
rw rw rw rw rw rc_w1 rc_w1 rw rw
Bits 31:9 Reserved, must be kept at reset value..

Power control (PWR) RM0008
76/1093 Doc ID 13902 Rev 13
Bit 8 DBP: Disable backup domain write protection.
In reset state, the RTC and backup registers are protected against parasitic write access.
This bit must be set to enable write access to these registers.
0: Access to RTC and Backup registers disabled
1: Access to RTC and Backup registers enabled
Note: If the HSE divided by 128 is used as the RTC clock, this bit must remain set to 1.
Bits 7:5 PLS[2:0]: PVD level selection.
These bits are written by software to select the voltage threshold detected by the Power
Voltage Detector
000: 2.2V
001: 2.3V
010: 2.4V
011: 2.5V
100: 2.6V
101: 2.7V
110: 2.8V
111: 2.9V
Note: Refer to the electrical characteristics of the datasheet for more details.
Bit 4 PVDE: Power voltage detector enable.
This bit is set and cleared by software.
0: PVD disabled
1: PVD enabled
Bit 3 CSBF: Clear standby flag.
This bit is always read as 0.
0: No effect
1: Clear the SBF Standby Flag (write).
Bit 2 CWUF: Clear wakeup flag.
This bit is always read as 0.
0: No effect
1: Clear the WUF Wakeup Flag after 2 System clock cycles. (write)
Bit 1 PDDS: Power down deepsleep.
This bit is set and cleared by software. It works together with the LPDS bit.
0: Enter Stop mode when the CPU enters Deepsleep. The regulator status depends on the
LPDS bit.
1: Enter Standby mode when the CPU enters Deepsleep.
Bit 0 LPDS: Low-power deepsleep.
This bit is set and cleared by software. It works together with the PDDS bit.
0: Voltage regulator on during Stop mode
1: Voltage regulator in low-power mode during Stop mode
RM0008 Power control (PWR)
Doc ID 13902 Rev 13 77/1093

5.4.2 Power control/status register (PWR_CSR)
Address offset: 0x04
Reset value: 0x0000 0000 (not reset by wakeup from Standby mode)
Additional APB cycles are needed to read this register versus a standard APB read.


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
EWUP
Reserved
PVDO SBF WUF
rw r r r
Bits 31:9 Reserved, must be kept at reset value.
Bit 8 EWUP: Enable WKUP pin
This bit is set and cleared by software.
0: WKUP pin is used for general purpose I/O. An event on the WKUP pin does not wakeup
the device from Standby mode.
1: WKUP pin is used for wakeup from Standby mode and forced in input pull down
configuration (rising edge on WKUP pin wakes-up the system from Standby mode).
Note: This bit is reset by a system Reset.
Bits 7:3 Reserved, must be kept at reset value.
Bit 2 PVDO: PVD output
This bit is set and cleared by hardware. It is valid only if PVD is enabled by the PVDE bit.
0: V
DD
/V
DDA
is higher than the PVD threshold selected with the PLS[2:0] bits.
1: V
DD
/V
DDA
is lower than the PVD threshold selected with the PLS[2:0] bits.
Note: The PVD is stopped by Standby mode. For this reason, this bit is equal to 0 after
Standby or reset until the PVDE bit is set.
Bit 1 SBF: Standby flag
This bit is set by hardware and cleared only by a POR/PDR (power on reset/power down reset)
or by setting the CSBF bit in the Power control register (PWR_CR)
0: Device has not been in Standby mode
1: Device has been in Standby mode
Bit 0 WUF: Wakeup flag
This bit is set by hardware and cleared only by a POR/PDR (power on reset/power down
reset) or by setting the CWUF bit in the Power control register (PWR_CR)
0: No wakeup event occurred
1: A wakeup event was received from the WKUP pin or from the RTC alarm
Note: An additional wakeup event is detected if the WKUP pin is enabled (by setting the
EWUP bit) when the WKUP pin level is already high.

Power control (PWR) RM0008
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5.4.3 PWR register map
The following table summarizes the PWR registers.

Refer to Table 3 on page 50 for the register boundary addresses.
Table 16. PWR register map and reset values
Offset Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9 8 7 6 5 4 3 2 1 0
0x000
PWR_CR
Reserved
D
B
P
PLS[2:0]
P
V
D
E
C
S
B
F
C
W
U
F
P
D
D
S
L
P
D
S
Reset value 0 0 0 0 0 0 0 0 0
0x004
PWR_CSR
Reserved
E
W
U
P
Reserved
P
V
D
O
S
B
F
W
U
F
Reset value 0 0 0 0
RM0008 Backup registers (BKP)
Doc ID 13902 Rev 13 79/1093
6 Backup registers (BKP)
Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx
microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx
microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
High-density devices are STM32F101xx and STM32F103xx microcontrollers where the
Flash memory density ranges between 256 and 512 Kbytes.
XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the
Flash memory density ranges between 768 Kbytes and 1 Mbyte.
Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
This section applies to the whole STM32F101xx family, unless otherwise specified.
6.1 BKP introduction
The backup registers are forty two 16-bit registers for storing 84 bytes of user application
data.
They are implemented in the backup domain that remains powered on by V
BAT
when the
V
DD
power is switched off. They are not reset when the device wakes up from Standby
mode or by a system reset or power reset.
In addition, the BKP control registers are used to manage the Tamper detection feature and
RTC calibration.
After reset, access to the Backup registers and RTC is disabled and the Backup domain
(BKP) is protected against possible parasitic write access. To enable access to the Backup
registers and the RTC, proceed as follows:
enable the power and backup interface clocks by setting the PWREN and BKPEN bits
in the RCC_APB1ENR register
set the DBP bit the Power Control Register (PWR_CR) to enable access to the Backup
registers and RTC.
6.2 BKP main features
20-byte data registers (in medium-density and low-density devices) or 84-byte data
registers (in high-density, XL-density and connectivity line devices)
Status/control register for managing tamper detection with interrupt capability
Calibration register for storing the RTC calibration value
Possibility to output the RTC Calibration Clock, RTC Alarm pulse or Second pulse on
TAMPER pin PC13 (when this pin is not used for tamper detection)
Backup registers (BKP) RM0008
80/1093 Doc ID 13902 Rev 13
6.3 BKP functional description
6.3.1 Tamper detection
The TAMPER pin generates a Tamper detection event when the pin changes from 0 to 1 or
from 1 to 0 depending on the TPAL bit in the Backup control register (BKP_CR). A tamper
detection event resets all data backup registers.
However to avoid losing Tamper events, the signal used for edge detection is logically
ANDed with the Tamper enable in order to detect a Tamper event in case it occurs before
the TAMPER pin is enabled.
When TPAL=0: If the TAMPER pin is already high before it is enabled (by setting TPE
bit), an extra Tamper event is detected as soon as the TAMPER pin is enabled (while
there was no rising edge on the TAMPER pin after TPE was set)
When TPAL=1: If the TAMPER pin is already low before it is enabled (by setting the
TPE bit), an extra Tamper event is detected as soon as the TAMPER pin is enabled
(while there was no falling edge on the TAMPER pin after TPE was set)
By setting the TPIE bit in the BKP_CSR register, an interrupt is generated when a Tamper
detection event occurs.
After a Tamper event has been detected and cleared, the TAMPER pin should be disabled
and then re-enabled with TPE before writing to the backup data registers (BKP_DRx) again.
This prevents software from writing to the backup data registers (BKP_DRx), while the
TAMPER pin value still indicates a Tamper detection. This is equivalent to a level detection
on the TAMPER pin.
Note: Tamper detection is still active when V
DD
power is switched off. To avoid unwanted resetting
of the data backup registers, the TAMPER pin should be externally tied to the correct level.
6.3.2 RTC calibration
For measurement purposes, the RTC clock with a frequency divided by 64 can be output on
the TAMPER pin. This is enabled by setting the CCO bit in the RTC clock calibration register
(BKP_RTCCR).
The clock can be slowed down by up to 121 ppm by configuring CAL[6:0] bits.
For more details about RTC calibration and how to use it to improve timekeeping accuracy,
please refer to AN2604 "STM32F101xx and STM32F103xx RTC calibration.
RM0008 Backup registers (BKP)
Doc ID 13902 Rev 13 81/1093
6.4 BKP registers
Refer to Section 2.1 on page 46 for a list of abbreviations used in register descriptions.
The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).
6.4.1 Backup data register x (BKP_DRx) (x = 1 ..42)
Address offset: 0x04 to 0x28, 0x40 to 0xBC
Reset value: 0x0000 0000

6.4.2 RTC clock calibration register (BKP_RTCCR)
Address offset: 0x2C
Reset value: 0x0000 0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
D[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 15:0 D[15:0] Backup data
These bits can be written with user data.
Note: The BKP_DRx registers are not reset by a System reset or Power reset or when the
device wakes up from Standby mode.
They are reset by a Backup Domain reset or by a TAMPER pin event (if the TAMPER
pin function is activated).
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
ASOS ASOE CCO CAL[6:0]
rw rw rw rw rw rw rw rw rw rw
Bits 15:10 Reserved, must be kept at reset value.
Bit 9 ASOS: Alarm or second output selection
When the ASOE bit is set, the ASOS bit can be used to select whether the signal output on
the TAMPER pin is the RTC Second pulse signal or the Alarm pulse signal:
0: RTC Alarm pulse output selected
1: RTC Second pulse output selected
Note: This bit is reset only by a Backup domain reset.
Bit 8 ASOE: Alarm or second output enable
Setting this bit outputs either the RTC Alarm pulse signal or the Second pulse signal on the
TAMPER pin depending on the ASOS bit.
The output pulse duration is one RTC clock period. The TAMPER pin must not be enabled
while the ASOE bit is set.
Note: This bit is reset only by a Backup domain reset.
Bit 7 CCO: Calibration clock output
0: No effect
1: Setting this bit outputs the RTC clock with a frequency divided by 64 on the TAMPER pin.
The TAMPER pin must not be enabled while the CCO bit is set in order to avoid unwanted
Tamper detection.
Note: This bit is reset when the V
DD
supply is powered off.
Backup registers (BKP) RM0008
82/1093 Doc ID 13902 Rev 13
6.4.3 Backup control register (BKP_CR)
Address offset: 0x30
Reset value: 0x0000 0000

Note: Setting the TPAL and TPE bits at the same time is always safe, however resetting both at
the same time can generate a spurious Tamper event. For this reason it is recommended to
change the TPAL bit only when the TPE bit is reset.
6.4.4 Backup control/status register (BKP_CSR)
Address offset: 0x34
Reset value: 0x0000 0000

Bit 6:0 CAL[6:0]: Calibration value
This value indicates the number of clock pulses that will be ignored every 2^20 clock pulses.
This allows the calibration of the RTC, slowing down the clock by steps of 1000000/2^20
PPM.
The clock of the RTC can be slowed down from 0 to 121PPM.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
TPAL TPE
rw rw
Bits 15:2 Reserved, must be kept at reset value.
Bit 1 TPAL: TAMPER pin active level
0: A high level on the TAMPER pin resets all data backup registers (if TPE bit is set).
1: A low level on the TAMPER pin resets all data backup registers (if TPE bit is set).
Bit 0 TPE: TAMPER pin enable
0: The TAMPER pin is free for general purpose I/O
1: Tamper alternate I/O function is activated.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
TIF TEF
Reserved
TPIE CTI CTE
r r rw w w
Bits 15:10 Reserved, must be kept at reset value.
Bit 9 TIF: Tamper interrupt flag
This bit is set by hardware when a Tamper event is detected and the TPIE bit is set. It is
cleared by writing 1 to the CTI bit (also clears the interrupt). It is also cleared if the TPIE bit is
reset.
0: No Tamper interrupt
1: A Tamper interrupt occurred
Note: This bit is reset only by a system reset and wakeup from Standby mode.
RM0008 Backup registers (BKP)
Doc ID 13902 Rev 13 83/1093
6.4.5 BKP register map
BKP registers are mapped as 16-bit addressable registers as described in the table below:

Bit 8 TEF: Tamper event flag
This bit is set by hardware when a Tamper event is detected. It is cleared by writing 1 to the
CTE bit.
0: No Tamper event
1: A Tamper event occurred
Note: A Tamper event resets all the BKP_DRx registers. They are held in reset as long as the
TEF bit is set. If a write to the BKP_DRx registers is performed while this bit is set, the
value will not be stored.
Bits 7:3 Reserved, must be kept at reset value.
Bit 2 TPIE: TAMPER pin interrupt enable
0: Tamper interrupt disabled
1: Tamper interrupt enabled (the TPE bit must also be set in the BKP_CR register
Note: 1: A Tamper interrupt does not wake up the core from low-power modes.
2: This bit is reset only by a system reset and wakeup from Standby mode.
Bit 1 CTI: Clear tamper interrupt
This bit is write only, and is always read as 0.
0: No effect
1: Clear the Tamper interrupt and the TIF Tamper interrupt flag.
Bit 0 CTE: Clear tamper event
This bit is write only, and is always read as 0.
0: No effect
1: Reset the TEF Tamper event flag (and the Tamper detector)
Table 17. BKP register map and reset values
Offset Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9 8 7 6 5 4 3 2 1 0
0x00 Reserved
0x04
BKP_DR1
Reserved
D[15:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x08
BKP_DR2
Reserved
D[15:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x0C
BKP_DR3
Reserved
D[15:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x10
BKP_DR4
Reserved
D[15:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x14
BKP_DR5
Reserved
D[15:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x18
BKP_DR6
Reserved
D[15:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Backup registers (BKP) RM0008
84/1093 Doc ID 13902 Rev 13
0x1C
BKP_DR7
Reserved
D[15:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x20
BKP_DR8
Reserved
D[15:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x24
BKP_DR9
Reserved
D[15:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x28
BKP_DR10
Reserved
D[15:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x2
BKP_RTCCR
Reserved
A
S
O
S
A
S
O
E
C
C
O
CAL[6:0]
Reset value 0 0 0 0 0 0 0 0 0 0
0x30
BKP_CR
Reserved
T
P
A
L
T
P
E
Reset value 0 0
0x34
BKP_CSR
Reserved T
I
F
T
E
F
Reserved
T
P
I
E
C
T
I
C
T
E
Reset value 0 0 0 0 0
0x38 Reserved
0x3C Reserved
0x40
BKP_DR11
Reserved
D[15:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x44
BKP_DR12
Reserved
D[15:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x48
BKP_DR13
Reserved
D[15:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x4C
BKP_DR14
Reserved
D[15:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x50
BKP_DR15
Reserved
D[15:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x54
BKP_DR16
Reserved
D[15:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x58
BKP_DR17
Reserved
D[15:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x5C
BKP_DR18
Reserved
D[15:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x60 BKP_DR19
Reserved
D[15:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 17. BKP register map and reset values (continued)
Offset Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9 8 7 6 5 4 3 2 1 0
RM0008 Backup registers (BKP)
Doc ID 13902 Rev 13 85/1093
0x64
BKP_DR20
Reserved
D[15:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x68
BKP_DR21
Reserved
D[15:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x6C
BKP_DR22
Reserved
D[15:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x70
BKP_DR23
Reserved
D[15:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x74
BKP_DR24
Reserved
D[15:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x78
BKP_DR25
Reserved
D[15:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x7C
BKP_DR26
Reserved
D[15:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x80
BKP_DR27
Reserved
D[15:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x84
BKP_DR28
Reserved
D[15:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x88 BKP_DR29
Reserved
D[15:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x8C
BKP_DR30
Reserved
D[15:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x90
BKP_DR31
Reserved
D[15:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x94
BKP_DR32
Reserved
D[15:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x98
BKP_DR33
Reserved
D[15:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x9C
BKP_DR34
Reserved
D[15:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0xA0
BKP_DR35
Reserved
D[15:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0xA4
BKP_DR36
Reserved
D[15:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 17. BKP register map and reset values (continued)
Offset Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9 8 7 6 5 4 3 2 1 0
Backup registers (BKP) RM0008
86/1093 Doc ID 13902 Rev 13
Refer to Table 3 on page 50 for the register boundary addresses.
0xA8
BKP_DR37
Reserved
D[15:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0xAC
BKP_DR38
Reserved
D[15:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0xB0 BKP_DR39
Reserved
D[15:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0xB4
BKP_DR40
Reserved
D[15:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0xB8 BKP_DR41
Reserved
D[15:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0xBC
BKP_DR42
Reserved
D[15:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 17. BKP register map and reset values (continued)
Offset Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9 8 7 6 5 4 3 2 1 0
RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC)
Doc ID 13902 Rev 13 87/1093
7 Low-, medium-, high- and XL-density reset and clock
control (RCC)
Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx
microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx
microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
High-density devices are STM32F101xx and STM32F103xx microcontrollers where the
Flash memory density ranges between 256 and 512 Kbytes.
XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the
Flash memory density ranges between 768 Kbytes and 1 Mbyte.
Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
This Section applies to low-, medium-, high- and XL-density STM32F10xxx devices.
Connectivity line devices are discussed in a separate section (refer to Connectivity line
devices: reset and clock control (RCC) on page 120).
7.1 Reset
There are three types of reset, defined as system reset, power reset and backup domain
reset.
7.1.1 System reset
A system reset sets all registers to their reset values except the reset flags in the clock
controller CSR register and the registers in the Backup domain (see Figure 4).
A system reset is generated when one of the following events occurs:
1. A low level on the NRST pin (external reset)
2. Window watchdog end of count condition (WWDG reset)
3. Independent watchdog end of count condition (IWDG reset)
4. A software reset (SW reset) (see Software reset)
5. Low-power management reset (see Low-power management reset)
The reset source can be identified by checking the reset flags in the Control/Status register,
RCC_CSR (see Section 7.3.10: Control/status register (RCC_CSR)).
Software reset
The SYSRESETREQ bit in Cortex-M3 Application Interrupt and Reset Control Register
must be set to force a software reset on the device. Refer to the STM32F10xxx Cortex-M3
programming manual (see Related documents on page 1) for more details.
Low-power management reset
There are two ways to generate a low-power management reset:
Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008
88/1093 Doc ID 13902 Rev 13
1. Reset generated when entering Standby mode:
This type of reset is enabled by resetting nRST_STDBY bit in User Option Bytes. In this
case, whenever a Standby mode entry sequence is successfully executed, the device
is reset instead of entering Standby mode.
2. Reset when entering Stop mode:
This type of reset is enabled by resetting nRST_STOP bit in User Option Bytes. In this
case, whenever a Stop mode entry sequence is successfully executed, the device is
reset instead of entering Stop mode.
For further information on the User Option Bytes, refer to the STM32F10xxx Flash
programming manual.
7.1.2 Power reset
A power reset is generated when one of the following events occurs:
1. Power-on/power-down reset (POR/PDR reset)
2. When exiting Standby mode
A power reset sets all registers to their reset values except the Backup domain (see
Figure 4)
These sources act on the NRST pin and it is always kept low during the delay phase. The
RESET service routine vector is fixed at address 0x0000_0004 in the memory map.
The system reset signal provided to the device is output on the NRST pin. The pulse
generator guarantees a minimum reset pulse duration of 20 s for each reset source
(external or internal reset). In case of an external reset, the reset pulse is generated while
the NRST pin is asserted low.
Figure 7. Simplified diagram of the reset circuit
7.1.3 Backup domain reset
The backup domain has two specific resets that affect only the backup domain (see
Figure 4).
A backup domain reset is generated when one of the following events occurs:
1. Software reset, triggered by setting the BDRST bit in the Backup domain control
register (RCC_BDCR).
2. V
DD
or V
BAT
power on, if both supplies have previously been powered off.
NRST
R
PU
V
DD
/V
DDA
WWDG reset
WDG reset
Pulse
generator
Power reset
External
reset
(min 20 s)
System reset
Filter
Software reset
Low-power management reset
ai16095b
RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC)
Doc ID 13902 Rev 13 89/1093
7.2 Clocks
Three different clock sources can be used to drive the system clock (SYSCLK):
HSI oscillator clock
HSE oscillator clock
PLL clock
The devices have the following two secondary clock sources:
40 kHz low speed internal RC (LSI RC) which drives the independent watchdog and
optionally the RTC used for Auto-wakeup from Stop/Standby mode.
32.768 kHz low speed external crystal (LSE crystal) which optionally drives the real-
time clock (RTCCLK)
Each clock source can be switched on or off independently when it is not used, to optimize
power consumption.
Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008
90/1093 Doc ID 13902 Rev 13
Figure 8. Clock tree
1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is
64 MHz.
2. For full details about the internal and external clock source characteristics, please refer to the Electrical
characteristics section in your device datasheet.
Several prescalers allow the configuration of the AHB frequency, the high speed APB
(APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and
the APB2 domains is 72 MHz. The maximum allowed frequency of the APB1 domain is
36 MHz. The SDIO AHB interface is clocked with a fixed frequency equal to HCLK/2
The RCC feeds the Cortex System Timer (SysTick) external clock with the AHB clock
(HCLK) divided by 8. The SysTick can work either with this clock or with the Cortex clock
(HCLK), configurable in the SysTick Control and Status Register. The ADCs are clocked by
the clock of the High Speed domain (APB2) divided by 2, 4, 6 or 8.
The Flash memory programming interface clock (FLITFCLK) is always the HSI clock.
HSE OSC
4-16 MHz
OSC_N
OSC_OUT
OSC32_N
OSC32_OUT
LSE OSC
32.768 kHz
HS RC
8 MHz
LS RC
40 kHz
to ndependent Watchdog (WDG)
PLL
x2, x3, x4
PLLMUL
HSE = High-speed external clock signal
LSE = Low -speed external clock signal
LS = Low-speed internal clock signal
HS = High-speed internal clock signal
Legend:
MCO
Clock Output
Main
PLLXTPRE
/2
..., x16
AHB
Prescaler
/1, 2..512
/2 PLLCLK
HS
HSE
APB1
Prescaler
/1, 2, 4, 8, 16
ADC
Prescaler
/2, 4, 6, 8
ADCCLK 14 MHz max
PCLK1
HCLK
PLLCLK
to AHB bus, core,
memory and DMA
USBCLK
to USB interface
USB
Prescaler
/1, 1.5
to ADC1, 2 or 3
LSE
LS
HS
/128
/2
HS
HSE
peripherals
to APB1
Peripheral Clock
Enable
Enable
Peripheral Clock
APB2
Prescaler
/1, 2, 4, 8, 16
PCLK2
TM1,8,9,10,11 timers
to TM1,8,9,10 and 11
peripherals to APB2
Peripheral Clock
Enable
Enable
Peripheral Clock
48 MHz
72 MHz max
72 MHz
72 MHz max
36 MHz max
to RTC
PLLSRC
SW
MCO
CSS
to Cortex System timer /8
Clock
Enable
SYSCLK
max
RTCCLK
RTCSEL[1:0]
TMxCLK
TMXCLK
WDGCLK
SYSCLK
FCLK Cortex
free running clock
/2
TM2,3,4,5,6,7,12,13,14
to TM2,3,4,5,6,7,12,13,14
To SDO AHB interface
Peripheral clock
enable
HCLK/2
to FSMC
FSMCCLK
to SDO
Peripheral clock
enable
Peripheral clock
enable
to 2S3
to 2S2
Peripheral clock
enable
Peripheral clock
enable
2S3CLK
2S2CLK
SDOCLK
ai14752e
f (APB1 prescaler =1) x1
else x2
f (APB2 prescaler =1) x1
else x2
FLTFCLK
to Flash programming interface
RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC)
Doc ID 13902 Rev 13 91/1093
The timer clock frequencies are automatically fixed by hardware. There are two cases:
1. if the APB prescaler is 1, the timer clock frequencies are set to the same frequency as
that of the APB domain to which the timers are connected.
2. otherwise, they are set to twice (2) the frequency of the APB domain to which the
timers are connected.
FCLK acts as Cortex-M3s free-running clock. For more details refer to the ARM Cortex-
M3 r1p1 Technical Reference Manual (TRM).
7.2.1 HSE clock
The high speed external clock signal (HSE) can be generated from two possible clock
sources:
HSE external crystal/ceramic resonator
HSE user external clock
The resonator and the load capacitors have to be placed as close as possible to the
oscillator pins in order to minimize output distortion and startup stabilization time. The
loading capacitance values must be adjusted according to the selected oscillator.

Figure 9. HSE/ LSE clock sources
Clock source Hardware configuration
External clock
Crystal/Ceramic
resonators
OSC_OUT
External
source
(HiZ)
OSC_IN OSC_OUT
Load
capacitors
C
L2
C
L1
Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008
92/1093 Doc ID 13902 Rev 13
External source (HSE bypass)
In this mode, an external clock source must be provided. It can have a frequency of up to
25 MHz. You select this mode by setting the HSEBYP and HSEON bits in the Clock control
register (RCC_CR). The external clock signal (square, sinus or triangle) with ~50% duty
cycle has to drive the OSC_IN pin while the OSC_OUT pin should be left hi-Z. See Figure 9.
External crystal/ceramic resonator (HSE crystal)
The 4 to 16 MHz external oscillator has the advantage of producing a very accurate rate on
the main clock.
The associated hardware configuration is shown in Figure 9. Refer to the electrical
characteristics section of the datasheet for more details.
The HSERDY flag in the Clock control register (RCC_CR) indicates if the high-speed
external oscillator is stable or not. At startup, the clock is not released until this bit is set by
hardware. An interrupt can be generated if enabled in the Clock interrupt register
(RCC_CIR).
The HSE Crystal can be switched on and off using the HSEON bit in the Clock control
register (RCC_CR).
7.2.2 HSI clock
The HSI clock signal is generated from an internal 8 MHz RC Oscillator and can be used
directly as a system clock or divided by 2 to be used as PLL input.
The HSI RC oscillator has the advantage of providing a clock source at low cost (no external
components). It also has a faster startup time than the HSE crystal oscillator however, even
with calibration the frequency is less accurate than an external crystal oscillator or ceramic
resonator.
Calibration
RC oscillator frequencies can vary from one chip to another due to manufacturing process
variations, this is why each device is factory calibrated by ST for 1% accuracy at T
A
=25C.
After reset, the factory calibration value is loaded in the HSICAL[7:0] bits in the Clock control
register (RCC_CR).
If the application is subject to voltage or temperature variations this may affect the RC
oscillator speed. You can trim the HSI frequency in the application using the HSITRIM[4:0]
bits in the Clock control register (RCC_CR).
The HSIRDY flag in the Clock control register (RCC_CR) indicates if the HSI RC is stable or
not. At startup, the HSI RC output clock is not released until this bit is set by hardware.
The HSI RC can be switched on and off using the HSION bit in the Clock control register
(RCC_CR).
The HSI signal can also be used as a backup source (Auxiliary clock) if the HSE crystal
oscillator fails. Refer to Section 7.2.7: Clock security system (CSS) on page 94.
RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC)
Doc ID 13902 Rev 13 93/1093
7.2.3 PLL
The internal PLL can be used to multiply the HSI RC output or HSE crystal output clock
frequency. Refer to Figure 8 and Clock control register (RCC_CR).
The PLL configuration (selection of HSI oscillator divided by 2 or HSE oscillator for PLL
input clock, and multiplication factor) must be done before enabling the PLL. Once the PLL
enabled, these parameters cannot be changed.
An interrupt can be generated when the PLL is ready if enabled in the Clock interrupt
register (RCC_CIR).
If the USB interface is used in the application, the PLL must be programmed to output 48 or
72 MHz. This is needed to provide a 48 MHz USBCLK.
7.2.4 LSE clock
The LSE crystal is a 32.768 kHz Low Speed External crystal or ceramic resonator. It has the
advantage providing a low-power but highly accurate clock source to the real-time clock
peripheral (RTC) for clock/calendar or other timing functions.
The LSE crystal is switched on and off using the LSEON bit in Backup domain control
register (RCC_BDCR).
The LSERDY flag in the Backup domain control register (RCC_BDCR) indicates if the LSE
crystal is stable or not. At startup, the LSE crystal output clock signal is not released until
this bit is set by hardware. An interrupt can be generated if enabled in the Clock interrupt
register (RCC_CIR).
External source (LSE bypass)
In this mode, an external clock source must be provided. It can have a frequency of up to
1 MHz. You select this mode by setting the LSEBYP and LSEON bits in the Backup domain
control register (RCC_BDCR). The external clock signal (square, sinus or triangle) with
~50% duty cycle has to drive the OSC32_IN pin while the OSC32_OUT pin should be left
Hi-Z. See Figure 9.
7.2.5 LSI clock
The LSI RC acts as an low-power clock source that can be kept running in Stop and
Standby mode for the independent watchdog (IWDG) and Auto-wakeup unit (AWU). The
clock frequency is around 40 kHz (between 30 kHz and 60 kHz). For more details, refer to
the electrical characteristics section of the datasheets.
The LSI RC can be switched on and off using the LSION bit in the Control/status register
(RCC_CSR).
The LSIRDY flag in the Control/status register (RCC_CSR) indicates if the low-speed
internal oscillator is stable or not. At startup, the clock is not released until this bit is set by
hardware. An interrupt can be generated if enabled in the Clock interrupt register
(RCC_CIR).
Note: LSI calibration is only available on high-density, XL-density and connectivity line devices.
Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008
94/1093 Doc ID 13902 Rev 13
LSI calibration
The frequency dispersion of the Low Speed Internal RC (LSI) oscillator can be calibrated to
have accurate RTC time base and/or IWDG timeout (when LSI is used as clock source for
these peripherals) with an acceptable accuracy.
This calibration is performed by measuring the LSI clock frequency with respect to TIM5
input clock (TIM5CLK). According to this measurement done at the precision of the HSE
oscillator, the software can adjust the programmable 20-bit prescaler of the RTC to get an
accurate time base or can compute accurate IWDG timeout.
Use the following procedure to calibrate the LSI:
1. Enable TIM5 timer and configure channel4 in input capture mode
2. Set the TIM5CH4_IREMAP bit in the AFIO_MAPR register to connect the LSI clock
internally to TIM5 channel4 input capture for calibration purpose.
3. Measure the frequency of LSI clock using the TIM5 Capture/compare 4 event or
interrupt.
4. Use the measured LSI frequency to update the 20-bit prescaler of the RTC depending
on the desired time base and/or to compute the IWDG timeout.
7.2.6 System clock (SYSCLK) selection
After a system reset, the HSI oscillator is selected as system clock. When a clock source is
used directly or through the PLL as system clock, it is not possible to stop it.
A switch from one clock source to another occurs only if the target clock source is ready
(clock stable after startup delay or PLL locked). If a clock source which is not yet ready is
selected, the switch will occur when the clock source will be ready. Status bits in the Clock
control register (RCC_CR) indicate which clock(s) is (are) ready and which clock is currently
used as system clock.
7.2.7 Clock security system (CSS)
Clock Security System can be activated by software. In this case, the clock detector is
enabled after the HSE oscillator startup delay, and disabled when this oscillator is stopped.
If a failure is detected on the HSE clock, the HSE oscillator is automatically disabled, a clock
failure event is sent to the break input of the advanced-control timers (TIM1 and TIM8) and
an interrupt is generated to inform the software about the failure (Clock Security System
Interrupt CSSI), allowing the MCU to perform rescue operations. The CSSI is linked to the
Cortex-M3 NMI (Non-Maskable Interrupt) exception vector.
Note: Once the CSS is enabled and if the HSE clock fails, the CSS interrupt occurs and an NMI is
automatically generated. The NMI will be executed indefinitely unless the CSS interrupt
pending bit is cleared. As a consequence, in the NMI ISR user must clear the CSS interrupt
by setting the CSSC bit in the Clock interrupt register (RCC_CIR).
If the HSE oscillator is used directly or indirectly as the system clock (indirectly means: it is
used as PLL input clock, and the PLL clock is used as system clock), a detected failure
causes a switch of the system clock to the HSI oscillator and the disabling of the HSE
oscillator. If the HSE clock (divided or not) is the clock entry of the PLL used as system clock
when the failure occurs, the PLL is disabled too.
RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC)
Doc ID 13902 Rev 13 95/1093
7.2.8 RTC clock
The RTCCLK clock source can be either the HSE/128, LSE or LSI clocks. This is selected
by programming the RTCSEL[1:0] bits in the Backup domain control register (RCC_BDCR).
This selection cannot be modified without resetting the Backup domain.
The LSE clock is in the Backup domain, whereas the HSE and LSI clocks are not.
Consequently:
If LSE is selected as RTC clock:
The RTC continues to work even if the V
DD
supply is switched off, provided the
V
BAT
supply is maintained.
If LSI is selected as Auto-Wakeup unit (AWU) clock:
The AWU state is not guaranteed if the V
DD
supply is powered off. Refer to
Section 7.2.5: LSI clock on page 93 for more details on LSI calibration.
If the HSE clock divided by 128 is used as the RTC clock:
The RTC state is not guaranteed if the V
DD
supply is powered off or if the internal
voltage regulator is powered off (removing power from the 1.8 V domain).
The DPB bit (disable backup domain write protection) in the Power controller
register must be set to 1 (refer to Section 5.4.1: Power control register
(PWR_CR)).
7.2.9 Watchdog clock
If the Independent watchdog (IWDG) is started by either hardware option or software
access, the LSI oscillator is forced ON and cannot be disabled. After the LSI oscillator
temporization, the clock is provided to the IWDG.
7.2.10 Clock-out capability
The microcontroller clock output (MCO) capability allows the clock to be output onto the
external MCO pin. The configuration registers of the corresponding GPIO port must be
programmed in alternate function mode. One of 4 clock signals can be selected as the MCO
clock.
SYSCLK
HSI
HSE
PLL clock divided by 2
The selection is controlled by the MCO[2:0] bits of the Clock configuration register
(RCC_CFGR).
Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008
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7.3 RCC registers
Refer to Section 2.1 on page 46 for a list of abbreviations used in register descriptions.
7.3.1 Clock control register (RCC_CR)
Address offset: 0x00
Reset value: 0x0000 XX83 where X is undefined.
Access: no wait state, word, half-word and byte access


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
PLL
RDY
PLLON
Reserved
CSS
ON
HSE
BYP
HSE
RDY
HSE
ON
r rw rw rw r rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSICAL[7:0] HSITRIM[4:0]
Res.
HSI
RDY
HSION
r r r r r r r r rw rw rw rw rw r rw
Bits 31:26 Reserved, must be kept at reset value.
Bit 25 PLLRDY: PLL clock ready flag
Set by hardware to indicate that the PLL is locked.
0: PLL unlocked
1: PLL locked
Bit 24 PLLON: PLL enable
Set and cleared by software to enable PLL.
Cleared by hardware when entering Stop or Standby mode. This bit can not be reset if the
PLL clock is used as system clock or is selected to become the system clock.
0: PLL OFF
1: PLL ON
Bits 23:20 Reserved, must be kept at reset value.
Bit 19 CSSON: Clock security system enable
Set and cleared by software to enable the clock security system. When CSSON is set, the
clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by
hardware if a HSE clock failure is detected.
0: Clock detector OFF
1: Clock detector ON (Clock detector ON if the HSE oscillator is ready , OFF if not).
Bit 18 HSEBYP: External high-speed clock bypass
Set and cleared by software to bypass the oscillator with an external clock. The external
clock must be enabled with the HSEON bit set, to be used by the device. The HSEBYP bit
can be written only if the HSE oscillator is disabled.
0: external 4-16 MHz oscillator not bypassed
1: external 4-16 MHz oscillator bypassed with external clock
RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC)
Doc ID 13902 Rev 13 97/1093
Bit 17 HSERDY: External high-speed clock ready flag
Set by hardware to indicate that the HSE oscillator is stable. This bit needs 6 cycles of the
HSE oscillator clock to fall down after HSEON reset.
0: HSE oscillator not ready
1: HSE oscillator ready
Bit 16 HSEON: HSE clock enable
Set and cleared by software.
Cleared by hardware to stop the HSE oscillator when entering Stop or Standby mode. This
bit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock.
0: HSE oscillator OFF
1: HSE oscillator ON
Bits 15:8 HSICAL[7:0]: Internal high-speed clock calibration
These bits are initialized automatically at startup.
Bits 7:3 HSITRIM[4:0]: Internal high-speed clock trimming
These bits provide an additional user-programmable trimming value that is added to the
HSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature
that influence the frequency of the internal HSI RC.
The default value is 16, which, when added to the HSICAL value, should trim the HSI to 8
MHz 1%. The trimming step (F
hsitrim
) is around 40 kHz between two consecutive HSICAL
steps.
Bit 2 Reserved, must be kept at reset value.
Bit 1 HSIRDY: Internal high-speed clock ready flag
Set by hardware to indicate that internal 8 MHz RC oscillator is stable. After the HSION bit is
cleared, HSIRDY goes low after 6 internal 8 MHz RC oscillator clock cycles.
0: internal 8 MHz RC oscillator not ready
1: internal 8 MHz RC oscillator ready
Bit 0 HSION: Internal high-speed clock enable
Set and cleared by software.
Set by hardware to force the internal 8 MHz RC oscillator ON when leaving Stop or Standby
mode or in case of failure of the external 4-16 MHz oscillator used directly or indirectly as
system clock. This bit cannot be reset if the internal 8 MHz RC is used directly or indirectly
as system clock or is selected to become the system clock.
0: internal 8 MHz RC oscillator OFF
1: internal 8 MHz RC oscillator ON
Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008
98/1093 Doc ID 13902 Rev 13
7.3.2 Clock configuration register (RCC_CFGR)
Address offset: 0x04
Reset value: 0x0000 0000
Access: 0 wait state 2, word, half-word and byte access
1 or 2 wait states inserted only if the access occurs during clock source switch.


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
MCO[2:0]
Res.
USB
PRE
PLLMUL[3:0]
PLL
XTPRE
PLL
SRC
rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADCPRE[1:0] PPRE2[2:0] PPRE1[2:0] HPRE[3:0] SWS[1:0] SW[1:0]
rw rw rw rw rw rw rw rw rw rw rw rw r r rw rw
Bits 31:27 Reserved, must be kept at reset value.
Bits 26:24 MCO: Microcontroller clock output
Set and cleared by software.
0xx: No clock
100: System clock (SYSCLK) selected
101: HSI clock selected
110: HSE clock selected
111: PLL clock divided by 2 selected
Note: This clock output may have some truncated cycles at startup or during MCO clock
source switching.
When the System Clock is selected to output to the MCO pin, make sure that this clock
does not exceed 50 MHz (the maximum IO speed).
Bit 22 USBPRE: USB prescaler
Set and cleared by software to generate 48 MHz USB clock. This bit must be valid before
enabling the USB clock in the RCC_APB1ENR register. This bit cant be reset if the USB
clock is enabled.
0: PLL clock is divided by 1.5
1: PLL clock is not divided
RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC)
Doc ID 13902 Rev 13 99/1093
Bits 21:18 PLLMUL: PLL multiplication factor
These bits are written by software to define the PLL multiplication factor. These bits can be
written only when PLL is disabled.
Caution: The PLL output frequency must not exceed 72 MHz.
0000: PLL input clock x 2
0001: PLL input clock x 3
0010: PLL input clock x 4
0011: PLL input clock x 5
0100: PLL input clock x 6
0101: PLL input clock x 7
0110: PLL input clock x 8
0111: PLL input clock x 9
1000: PLL input clock x 10
1001: PLL input clock x 11
1010: PLL input clock x 12
1011: PLL input clock x 13
1100: PLL input clock x 14
1101: PLL input clock x 15
1110: PLL input clock x 16
1111: PLL input clock x 16
Bit 17 PLLXTPRE: HSE divider for PLL entry
Set and cleared by software to divide HSE before PLL entry. This bit can be written only
when PLL is disabled.
0: HSE clock not divided
1: HSE clock divided by 2
Bit 16 PLLSRC: PLL entry clock source
Set and cleared by software to select PLL clock source. This bit can be written only when
PLL is disabled.
0: HSI oscillator clock / 2 selected as PLL input clock
1: HSE oscillator clock selected as PLL input clock
Bits 15:14 ADCPRE: ADC prescaler
Set and cleared by software to select the frequency of the clock to the ADCs.
00: PCLK2 divided by 2
01: PCLK2 divided by 4
10: PCLK2 divided by 6
11: PCLK2 divided by 8
Bits 13:11 PPRE2: APB high-speed prescaler (APB2)
Set and cleared by software to control the division factor of the APB high-speed clock
(PCLK2).
0xx: HCLK not divided
100: HCLK divided by 2
101: HCLK divided by 4
110: HCLK divided by 8
111: HCLK divided by 16
Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008
100/1093 Doc ID 13902 Rev 13
Bits 10:8 PPRE1: APB low-speed prescaler (APB1)
Set and cleared by software to control the division factor of the APB low-speed clock
(PCLK1).
Warning: the software has to set correctly these bits to not exceed 36 MHz on this domain.
0xx: HCLK not divided
100: HCLK divided by 2
101: HCLK divided by 4
110: HCLK divided by 8
111: HCLK divided by 16
Bits 7:4 HPRE: AHB prescaler
Set and cleared by software to control the division factor of the AHB clock.
0xxx: SYSCLK not divided
1000: SYSCLK divided by 2
1001: SYSCLK divided by 4
1010: SYSCLK divided by 8
1011: SYSCLK divided by 16
1100: SYSCLK divided by 64
1101: SYSCLK divided by 128
1110: SYSCLK divided by 256
1111: SYSCLK divided by 512
Note: The prefetch buffer must be kept on when using a prescaler different from 1 on the
AHB clock. Refer to Reading the Flash memory on page 58 section for more details.
Bits 3:2 SWS: System clock switch status
Set and cleared by hardware to indicate which clock source is used as system clock.
00: HSI oscillator used as system clock
01: HSE oscillator used as system clock
10: PLL used as system clock
11: not applicable
Bits 1:0 SW: System clock switch
Set and cleared by software to select SYSCLK source.
Set by hardware to force HSI selection when leaving Stop and Standby mode or in case of
failure of the HSE oscillator used directly or indirectly as system clock (if the Clock Security
System is enabled).
00: HSI selected as system clock
01: HSE selected as system clock
10: PLL selected as system clock
11: not allowed
RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC)
Doc ID 13902 Rev 13 101/1093
7.3.3 Clock interrupt register (RCC_CIR)
Address offset: 0x08
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
CSSC
Reserved
PLL
RDYC
HSE
RDYC
HSI
RDYC
LSE
RDYC
LSI
RDYC
w w w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
PLL
RDYIE
HSE
RDYIE
HSI
RDYIE
LSE
RDYIE
LSI
RDYIE
CSSF
Reserved
PLL
RDYF
HSE
RDYF
HSI
RDYF
LSE
RDYF
LSI
RDYF
rw rw rw rw rw r r r r r r
Bits 31:24 Reserved, must be kept at reset value.
Bit 23 CSSC: Clock security system interrupt clear
This bit is set by software to clear the CSSF flag.
0: No effect
1: Clear CSSF flag
Bits 22:21 Reserved, must be kept at reset value.
Bit 20 PLLRDYC: PLL ready interrupt clear
This bit is set by software to clear the PLLRDYF flag.
0: No effect
1: PLLRDYF cleared
Bit 19 HSERDYC: HSE ready interrupt clear
This bit is set by software to clear the HSERDYF flag.
0: No effect
1: HSERDYF cleared
Bit 18 HSIRDYC: HSI ready interrupt clear
This bit is set software to clear the HSIRDYF flag.
0: No effect
1: HSIRDYF cleared
Bit 17 LSERDYC: LSE ready interrupt clear
This bit is set by software to clear the LSERDYF flag.
0: No effect
1: LSERDYF cleared
Bit 16 LSIRDYC: LSI ready interrupt clear
This bit is set by software to clear the LSIRDYF flag.
0: No effect
1: LSIRDYF cleared
Bits 15:13 Reserved, must be kept at reset value.
Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008
102/1093 Doc ID 13902 Rev 13
Bit 12 PLLRDYIE: PLL ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by PLL lock.
0: PLL lock interrupt disabled
1: PLL lock interrupt enabled
Bit 11 HSERDYIE: HSE ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by the external 4-16 MHz
oscillator stabilization.
0: HSE ready interrupt disabled
1: HSE ready interrupt enabled
Bit 10 HSIRDYIE: HSI ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by the internal 8 MHz RC
oscillator stabilization.
0: HSI ready interrupt disabled
1: HSI ready interrupt enabled
Bit 9 LSERDYIE: LSE ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by the external 32 kHz
oscillator stabilization.
0: LSE ready interrupt disabled
1: LSE ready interrupt enabled
Bit 8 LSIRDYIE: LSI ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by internal RC 40 kHz
oscillator stabilization.
0: LSI ready interrupt disabled
1: LSI ready interrupt enabled
Bit 7 CSSF: Clock security system interrupt flag
Set by hardware when a failure is detected in the external 4-16 MHz oscillator.
Cleared by software setting the CSSC bit.
0: No clock security interrupt caused by HSE clock failure
1: Clock security interrupt caused by HSE clock failure
Bits 6:5 Reserved, must be kept at reset value.
Bit 4 PLLRDYF: PLL ready interrupt flag
Set by hardware when the PLL locks and PLLRDYDIE is set.
Cleared by software setting the PLLRDYC bit.
0: No clock ready interrupt caused by PLL lock
1: Clock ready interrupt caused by PLL lock
Bit3 HSERDYF: HSE ready interrupt flag
Set by hardware when External Low Speed clock becomes stable and HSERDYDIE is set.
Cleared by software setting the HSERDYC bit.
0: No clock ready interrupt caused by the external 4-16 MHz oscillator
1: Clock ready interrupt caused by the external 4-16 MHz oscillator
Bit 2 HSIRDYF: HSI ready interrupt flag
Set by hardware when the Internal High Speed clock becomes stable and HSIRDYDIE is
set.
Cleared by software setting the HSIRDYC bit.
0: No clock ready interrupt caused by the internal 8 MHz RC oscillator
1: Clock ready interrupt caused by the internal 8 MHz RC oscillator
RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC)
Doc ID 13902 Rev 13 103/1093
7.3.4 APB2 peripheral reset register (RCC_APB2RSTR)
Address offset: 0x0C
Reset value: 0x00000 0000
Access: no wait state, word, half-word and byte access


Bit 1 LSERDYF: LSE ready interrupt flag
Set by hardware when the External Low Speed clock becomes stable and LSERDYDIE is
set.
Cleared by software setting the LSERDYC bit.
0: No clock ready interrupt caused by the external 32 kHz oscillator
1: Clock ready interrupt caused by the external 32 kHz oscillator
Bit 0 LSIRDYF: LSI ready interrupt flag
Set by hardware when the internal low speed clock becomes stable and LSIRDYDIE is set.
Cleared by software setting the LSIRDYC bit.
0: No clock ready interrupt caused by the internal RC 40 kHz oscillator
1: Clock ready interrupt caused by the internal RC 40 kHz oscillator
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
TIM11
RST
TIM10
RST
TIM9
RST
Reserved
rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADC3
RST
USART1
RST
TIM8
RST
SPI1
RST
TIM1
RST
ADC2
RST
ADC1
RST
IOPG
RST
IOPF
RST
IOPE
RST
IOPD
RST
IOPC
RST
IOPB
RST
IOPA
RST
Res.
AFIO
RST
rw rw rw rw rw rw rw rw rw rw rw rw rw rw Res. rw
Bits 31:22 Reserved, must be kept at reset value.
Bit 21 TIM11RST: TIM11 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM11 timer
Bit 20 TIM10RST: TIM10 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM10 timer
Bit 19 TIM9RST: TIM9 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM9 timer
Bits 18:16 Reserved, always read as 0.
Bit 15 ADC3RST: ADC3 interface reset
Set and cleared by software.
0: No effect
1: Reset ADC3 interface
Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008
104/1093 Doc ID 13902 Rev 13
Bit 14 USART1RST: USART1 reset
Set and cleared by software.
0: No effect
1: Reset USART1
ADC1RST: ADC1 interface reset
Set and cleared by software.
0: No effect
1: Reset ADC1 interface
Bit 13 TIM8RST: TIM8 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM8 timer
Bit 12 SPI1RST: SPI1 reset
Set and cleared by software.
0: No effect
1: Reset SPI1
Bit 11 TIM1RST: TIM1 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM1 timer
Bit 10 ADC2RST: ADC 2 interface reset
Set and cleared by software.
0: No effect
1: Reset ADC 2 interface
Bit 9 ADC1RST: ADC 1 interface reset
Set and cleared by software.
0: No effect
1: Reset ADC 1 interface
Bit 8 IOPGRST: IO port G reset
Set and cleared by software.
0: No effect
1: Reset IO port G
Bit 7 IOPFRST: IO port F reset
Set and cleared by software.
0: No effect
1: Reset IO port F
Bit 6 IOPERST: IO port E reset
Set and cleared by software.
0: No effect
1: Reset IO port E
Bit 5 IOPDRST: IO port D reset
Set and cleared by software.
0: No effect
1: Reset IO port D
RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC)
Doc ID 13902 Rev 13 105/1093
Bit 4 IOPCRST: IO port C reset
Set and cleared by software.
0: No effect
1: Reset IO port C
Bit 3 IOPBRST: IO port B reset
Set and cleared by software.
0: No effect
1: Reset IO port B
Bit 2 IOPARST: IO port A reset
Set and cleared by software.
0: No effect
1: Reset IO port A
Bit 1 Reserved, must be kept at reset value.
Bit 0 AFIORST: Alternate function IO reset
Set and cleared by software.
0: No effect
1: Reset Alternate Function
Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008
106/1093 Doc ID 13902 Rev 13
7.3.5 APB1 peripheral reset register (RCC_APB1RSTR)
Address offset: 0x10
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
DAC
RST
PWR
RST
BKP
RST
Res.
CAN
RST
Res.
USB
RST
I2C2
RST
I2C1
RST
UART
5
RST
UART
4
RST
USART
3
RST
USART
2
RST Res.
rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI3
RST
SPI2
RST
Reserved
WWD
GRST
Reserved
TIM14
RST
TIM13
RST
TIM12
RST
TIM7
RST
TIM6
RST
TIM5
RST
TIM4
RST
TIM3
RST
TIM2
RST
rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:30 Reserved, must be kept at reset value.
Bit 29 DACRST: DAC interface reset
Set and cleared by software.
0: No effect
1: Reset DAC interface
Bit 28 PWRRST: Power interface reset
Set and cleared by software.
0: No effect
1: Reset power interface
Bit 27 BKPRST: Backup interface reset
Set and cleared by software.
0: No effect
1: Reset backup interface
Bit 26 Reserved, must be kept at reset value.
Bit 25 CANRST: CAN reset
Set and cleared by software.
0: No effect
1: Reset CAN
Bit 24 Reserved, always read as 0.
Bit 23 USBRST: USB reset
Set and cleared by software.
0: No effect
1: Reset USB
Bit 22 I2C2RST: I2C2 reset
Set and cleared by software.
0: No effect
1: Reset I2C2
RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC)
Doc ID 13902 Rev 13 107/1093
Bit 21 I2C1RST: I2C1 reset
Set and cleared by software.
0: No effect
1: Reset I2C1
Bit 20 UART5RST: USART5 reset
Set and cleared by software.
0: No effect
1: Reset USART5
Bit 19 UART4RST: USART4 reset
Set and cleared by software.
0: No effect
1: Reset USART4
Bit 18 USART3RST: USART3 reset
Set and cleared by software.
0: No effect
1: Reset USART3
Bit 17 USART2RST: USART2 reset
Set and cleared by software.
0: No effect
1: Reset USART2
Bit 16 Reserved, must be kept at reset value.
Bit 15 SPI3RST: SPI3 reset
Set and cleared by software.
0: No effect
1: Reset SPI3
Bit 14 SPI2RST: SPI2 reset
Set and cleared by software.
0: No effect
1: Reset SPI2
Bits 13:12 Reserved, must be kept at reset value.
Bit 11 WWDGRST: Window watchdog reset
Set and cleared by software.
0: No effect
1: Reset window watchdog
Bits 10:9 Reserved, must be kept at reset value.
Bit 8 TIM14RST: TIM14 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM14
Bit 7 TIM13RST: TIM13 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM13
Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008
108/1093 Doc ID 13902 Rev 13
7.3.6 AHB peripheral clock enable register (RCC_AHBENR)
Address offset: 0x14
Reset value: 0x0000 0014
Access: no wait state, word, half-word and byte access
Note: When the peripheral clock is not active, the peripheral register values may not be readable
by software and the returned value is always 0x0.


Bit 6 TIM12RST: TIM12 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM12
Bit 5 TIM7RST: TIM7 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM7
Bit 4 TIM6RST: TIM6 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM6
Bit 3 TIM5RST: TIM5 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM5
Bit 2 TIM4RST: TIM4 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM4
Bit 1 TIM3RST: TIM3 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM3
Bit 0 TIM2RST: TIM2 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
SDIO
EN
Res.
FSMC
EN
Res.
CRCE
N
Res.
FLITF
EN
Res.
SRAM
EN
DMA2
EN
DMA1
EN
rw rw rw rw rw rw rw
Bits 31:11 Reserved, must be kept at reset value.
RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC)
Doc ID 13902 Rev 13 109/1093
7.3.7 APB2 peripheral clock enable register (RCC_APB2ENR)
Address: 0x18
Reset value: 0x0000 0000
Access: word, half-word and byte access
No wait states, except if the access occurs while an access to a peripheral in the APB2
domain is on going. In this case, wait states are inserted until the access to APB2 peripheral
is finished.
Note: When the peripheral clock is not active, the peripheral register values may not be readable
by software and the returned value is always 0x0.
Bit 10 SDIOEN: SDIO clock enable
Set and cleared by software.
0: SDIO clock disabled
1: SDIO clock enabled
Bits 9 Reserved, always read as 0.
Bit 8 FSMCEN: FSMC clock enable
Set and cleared by software.
0: FSMC clock disabled
1: FSMC clock enabled
Bit 7 Reserved, always read as 0.
Bit 6 CRCEN: CRC clock enable
Set and cleared by software.
0: CRC clock disabled
1: CRC clock enabled
Bit 5 Reserved, must be kept at reset value.
Bit 4 FLITFEN: FLITF clock enable
Set and cleared by software to disable/enable FLITF clock during Sleep mode.
0: FLITF clock disabled during Sleep mode
1: FLITF clock enabled during Sleep mode
Bit 3 Reserved, must be kept at reset value.
Bit 2 SRAMEN: SRAM interface clock enable
Set and cleared by software to disable/enable SRAM interface clock during Sleep mode.
0: SRAM interface clock disabled during Sleep mode.
1: SRAM interface clock enabled during Sleep mode
Bit 1 DMA2EN: DMA2 clock enable
Set and cleared by software.
0: DMA2 clock disabled
1: DMA2 clock enabled
Bit 0 DMA1EN: DMA1 clock enable
Set and cleared by software.
0: DMA1 clock disabled
1: DMA1 clock enabled
Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008
110/1093 Doc ID 13902 Rev 13


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
TIM11
EN
TIM10
EN
TIM9
EN
Reserved
rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADC3
EN
USAR
T1EN
TIM8
EN
SPI1
EN
TIM1
EN
ADC2
EN
ADC1
EN
IOPG
EN
IOPF
EN
IOPE
EN
IOPD
EN
IOPC
EN
IOPB
EN
IOPA
EN
Res.
AFIO
EN
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:22 Reserved, must be kept at reset value.
Bit 21 TIM11EN: TIM11 timer clock enable
Set and cleared by software.
0: TIM11 timer clock disabled
1: TIM11 timer clock enabled
Bit 20 TIM10EN: TIM10 timer clock enable
Set and cleared by software.
0: TIM10 timer clock disabled
1: TIM10 timer clock enabled
Bit 19 TIM9EN: TIM9 timer clock enable
Set and cleared by software.
0: TIM9 timer clock disabled
1: TIM9 timer clock enabled
Bits 18:16 Reserved, always read as 0.
Bit 15 ADC3EN: ADC3 interface clock enable
Set and cleared by software.
0: ADC3 interface clock disabled
1: ADC3 interface clock enabled
Bit 14 USART1EN: USART1 clock enable
Set and cleared by software.
0: USART1 clock disabled
1: USART1 clock enabled
Bit 13 TIM8EN: TIM8 Timer clock enable
Set and cleared by software.
0: TIM8 timer clock disabled
1: TIM8 timer clock enabled
Bit 12 SPI1EN: SPI1 clock enable
Set and cleared by software.
0: SPI1 clock disabled
1: SPI1 clock enabled
Bit 11 TIM1EN: TIM1 timer clock enable
Set and cleared by software.
0: TIM1 timer clock disabled
1: TIM1 timer clock enabled
RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC)
Doc ID 13902 Rev 13 111/1093
7.3.8 APB1 peripheral clock enable register (RCC_APB1ENR)
Address: 0x1C
Reset value: 0x0000 0000
Bit 10 ADC2EN: ADC 2 interface clock enable
Set and cleared by software.
0: ADC 2 interface clock disabled
1: ADC 2 interface clock enabled
Bit 9 ADC1EN: ADC 1 interface clock enable
Set and cleared by software.
0: ADC 1 interface disabled
1: ADC 1 interface clock enabled
Bit 8 IOPGEN: IO port G clock enable
Set and cleared by software.
0: IO port G clock disabled
1: IO port G clock enabled
Bit 7 IOPFEN: IO port F clock enable
Set and cleared by software.
0: IO port F clock disabled
1: IO port F clock enabled
Bit 6 IOPEEN: IO port E clock enable
Set and cleared by software.
0: IO port E clock disabled
1: IO port E clock enabled
Bit 5 IOPDEN: IO port D clock enable
Set and cleared by software.
0: IO port D clock disabled
1: IO port D clock enabled
Bit 4 IOPCEN: IO port C clock enable
Set and cleared by software.
0: IO port C clock disabled
1: IO port C clock enabled
Bit 3 IOPBEN: IO port B clock enable
Set and cleared by software.
0: IO port B clock disabled
1: IO port B clock enabled
Bit 2 IOPAEN: IO port A clock enable
Set and cleared by software.
0: IO port A clock disabled
1: IO port A clock enabled
Bit 1 Reserved, must be kept at reset value.
Bit 0 AFIOEN: Alternate function IO clock enable
Set and cleared by software.
0: Alternate Function IO clock disabled
1: Alternate Function IO clock enabled
Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008
112/1093 Doc ID 13902 Rev 13
Access: word, half-word and byte access
No wait state, except if the access occurs while an access to a peripheral on APB1 domain
is on going. In this case, wait states are inserted until this access to APB1 peripheral is
finished.
Note: When the peripheral clock is not active, the peripheral register values may not be readable
by software and the returned value is always 0x0.


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
DAC
EN
PWR
EN
BKP
EN
Res.
CAN
EN
Res.
USB
EN
I2C2
EN
I2C1
EN
UART5E
N
UART4
EN
USART
3EN
USART
2EN
Res.
rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI3
EN
SPI2
EN
Reserved
WWD
GEN
Reserved
TIM14
EN
TIM13
EN
TIM12
EN
TIM7
EN
TIM6
EN
TIM5
EN
TIM4
EN
TIM3
EN
TIM2
EN
rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:30 Reserved, must be kept at reset value.
Bit 29 DACEN: DAC interface clock enable
Set and cleared by software.
0: DAC interface clock disabled
1: DAC interface clock enable
Bit 28 PWREN: Power interface clock enable
Set and cleared by software.
0: Power interface clock disabled
1: Power interface clock enable
Bit 27 BKPEN: Backup interface clock enable
Set and cleared by software.
0: Backup interface clock disabled
1: Backup interface clock enabled
Bit 26 Reserved, must be kept at reset value.
Bit 25 CANEN: CAN clock enable
Set and cleared by software.
0: CAN clock disabled
1: CAN clock enabled
Bit 24 Reserved, always read as 0.
Bit 23 USBEN: USB clock enable
Set and cleared by software.
0: USB clock disabled
1: USB clock enabled
Bit 22 I2C2EN: I2C2 clock enable
Set and cleared by software.
0: I2C2 clock disabled
1: I2C2 clock enabled
RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC)
Doc ID 13902 Rev 13 113/1093
Bit 21 I2C1EN: I2C1 clock enable
Set and cleared by software.
0: I2C1 clock disabled
1: I2C1 clock enabled
Bit 20 UART5EN: USART5 clock enable
Set and cleared by software.
0: USART5 clock disabled
1: USART5 clock enabled
Bit 19 UART4EN: USART4 clock enable
Set and cleared by software.
0: USART4 clock disabled
1: USART4 clock enabled
Bit 18 USART3EN: USART3 clock enable
Set and cleared by software.
0: USART3 clock disabled
1: USART3 clock enabled
Bit 17 USART2EN: USART2 clock enable
Set and cleared by software.
0: USART2 clock disabled
1: USART2 clock enabled
Bits 16 Reserved, always read as 0.
Bit 15 SPI3EN: SPI 3 clock enable
Set and cleared by software.
0: SPI 3 clock disabled
1: SPI 3 clock enabled
Bit 14 SPI2EN: SPI2 clock enable
Set and cleared by software.
0: SPI2 clock disabled
1: SPI2 clock enabled
Bits 13:12 Reserved, must be kept at reset value.
Bit 11 WWDGEN: Window watchdog clock enable
Set and cleared by software.
0: Window watchdog clock disabled
1: Window watchdog clock enabled
Bits 10:9 Reserved, must be kept at reset value.
Bit 8 TIM14EN: TIM14 timer clock enable
Set and cleared by software.
0: TIM14 clock disabled
1: TIM14 clock enabled
Bit 7 TIM13EN: TIM13 timer clock enable
Set and cleared by software.
0: TIM13 clock disabled
1: TIM13 clock enabled
Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008
114/1093 Doc ID 13902 Rev 13
Bit 6 TIM12EN: TIM12 timer clock enable
Set and cleared by software.
0: TIM12 clock disabled
1: TIM12 clock enabled
Bit 5 TIM7EN: TIM7 timer clock enable
Set and cleared by software.
0: TIM7 clock disabled
1: TIM7 clock enabled
Bit 4 TIM6EN: TIM6 timer clock enable
Set and cleared by software.
0: TIM6 clock disabled
1: TIM6 clock enabled
Bit 3 TIM5EN: TIM5 timer clock enable
Set and cleared by software.
0: TIM5 clock disabled
1: TIM5 clock enabled
Bit 2 TIM4EN: TIM4 timer clock enable
Set and cleared by software.
0: TIM4 clock disabled
1: TIM4 clock enabled
Bit 1 TIM3EN: TIM3 timer clock enable
Set and cleared by software.
0: TIM3 clock disabled
1: TIM3 clock enabled
Bit 0 TIM2EN: TIM2 timer clock enable
Set and cleared by software.
0: TIM2 clock disabled
1: TIM2 clock enabled
RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC)
Doc ID 13902 Rev 13 115/1093
7.3.9 Backup domain control register (RCC_BDCR)
Address offset: 0x20
Reset value: 0x0000 0000, reset by Backup domain Reset.
Access: 0 wait state 3, word, half-word and byte access
Wait states are inserted in case of successive accesses to this register.
Note: The LSEON, LSEBYP, RTCSEL and RTCEN bits of the Backup domain control register
(RCC_BDCR) are in the Backup domain. As a result, after Reset, these bits are write-
protected and the DBP bit in the Power control register (PWR_CR) has to be set before
these can be modified. Refer to Section 5 on page 44 for further information. These bits are
only reset after a Backup domain Reset (see Section 7.1.3: Backup domain reset). Any
internal or external Reset will not have any effect on these bits.


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
BDRST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTC
EN
Reserved
RTCSEL[1:0]
Reserved
LSE
BYP
LSE
RDY
LSEON
rw rw rw rw r rw
Bits 31:17 Reserved, must be kept at reset value.
Bit 16 BDRST: Backup domain software reset
Set and cleared by software.
0: Reset not activated
1: Resets the entire Backup domain
Bit 15 RTCEN: RTC clock enable
Set and cleared by software.
0: RTC clock disabled
1: RTC clock enabled
Bits 14:10 Reserved, must be kept at reset value.
Bits 9:8 RTCSEL[1:0]: RTC clock source selection
Set by software to select the clock source for the RTC. Once the RTC clock source has been
selected, it cannot be changed anymore unless the Backup domain is reset. The BDRST bit
can be used to reset them.
00: No clock
01: LSE oscillator clock used as RTC clock10: LSI oscillator clock used as RTC clock
11: HSE oscillator clock divided by 128 used as RTC clock
Bits 7:3 Reserved, must be kept at reset value.
Bit 2 LSEBYP: External low-speed oscillator bypass
Set and cleared by software to bypass oscillator in debug mode. This bit can be written only
when the external 32 kHz oscillator is disabled.
0: LSE oscillator not bypassed
1: LSE oscillator bypassed
Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008
116/1093 Doc ID 13902 Rev 13
Bit 1 LSERDY: External low-speed oscillator ready
Set and cleared by hardware to indicate when the external 32 kHz oscillator is stable. After
the LSEON bit is cleared, LSERDY goes low after 6 external low-speed oscillator clock
cycles.
0: External 32 kHz oscillator not ready
1: External 32 kHz oscillator ready
Bit 0 LSEON: External low-speed oscillator enable
Set and cleared by software.
0: External 32 kHz oscillator OFF
1: External 32 kHz oscillator ON
RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC)
Doc ID 13902 Rev 13 117/1093
7.3.10 Control/status register (RCC_CSR)
Address: 0x24
Reset value: 0x0C00 0000, reset by system Reset, except reset flags by power Reset only.
Access: 0 wait state 3, word, half-word and byte access
Wait states are inserted in case of successive accesses to this register.


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPWR
RSTF
WWDG
RSTF
IWDG
RSTF
SFT
RSTF
POR
RSTF
PIN
RSTF
Res.
RMVF
Reserved
rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
LSI
RDY
LSION
r rw
Bit 31 LPWRRSTF: Low-power reset flag
Set by hardware when a Low-power management reset occurs.
Cleared by writing to the RMVF bit.
0: No Low-power management reset occurred
1: Low-power management reset occurred
For further information on Low-power management reset, refer to Low-power management
reset.
Bit 30 WWDGRSTF: Window watchdog reset flag
Set by hardware when a window watchdog reset occurs.
Cleared by writing to the RMVF bit.
0: No window watchdog reset occurred
1: Window watchdog reset occurred
Bit 29 IWDGRSTF: Independent watchdog reset flag
Set by hardware when an independent watchdog reset from V
DD
domain occurs.
Cleared by writing to the RMVF bit.
0: No watchdog reset occurred
1: Watchdog reset occurred
Bit 28 SFTRSTF: Software reset flag
Set by hardware when a software reset occurs.
Cleared by writing to the RMVF bit.
0: No software reset occurred
1: Software reset occurred
Bit 27 PORRSTF: POR/PDR reset flag
Set by hardware when a POR/PDR reset occurs.
Cleared by writing to the RMVF bit.
0: No POR/PDR reset occurred
1: POR/PDR reset occurred
Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008
118/1093 Doc ID 13902 Rev 13
Bit 26 PINRSTF: PIN reset flag
Set by hardware when a reset from the NRST pin occurs.
Cleared by writing to the RMVF bit.
0: No reset from NRST pin occurred
1: Reset from NRST pin occurred
Bit 25 Reserved, must be kept at reset value.
Bit 24 RMVF: Remove reset flag
Set by software to clear the reset flags.
0: No effect
1: Clear the reset flags
Bits 23:2 Reserved, must be kept at reset value.
Bit 1 LSIRDY: Internal low-speed oscillator ready
Set and cleared by hardware to indicate when the internal RC 40 kHz oscillator is stable.
After the LSION bit is cleared, LSIRDY goes low after 3 internal RC 40 kHz oscillator clock
cycles.
0: Internal RC 40 kHz oscillator not ready
1: Internal RC 40 kHz oscillator ready
Bit 0 LSION: Internal low-speed oscillator enable
Set and cleared by software.
0: Internal RC 40 kHz oscillator OFF
1: Internal RC 40 kHz oscillator ON
RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC)
Doc ID 13902 Rev 13 119/1093
7.3.11 RCC register map
The following table gives the RCC register map and the reset values.

Refer to Table 1 on page 24 for the register boundary addresses.
Table 18. RCC register map and reset values
Offset Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9 8 7 6 5 4 3 2 1 0
0x00
RCC_CR
Reserved
P
L
L

R
D
Y
P
L
L

O
N
Reserved
C
S
S
O
N
H
S
E
B
Y
P
H
S
E
R
D
Y
H
S
E
O
N
HSICAL[7:0] HSITRIM[4:0]
R
e
s
e
r
v
e
d
H
S
I
R
D
Y
H
S
I
O
N
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1
0x04
RCC_CFGR
Reserved
MCO [2:0]
R
e
s
e
r
v
e
d
U
S
B
P
R
E
PLLMUL[3:0]
P
L
L
X
T
P
R
E
P
L
L
S
R
C
ADC
PRE
[1:0]
PPRE2
[2:0]
PPRE1
[2:0]
HPRE[3:0]
SWS
[1:0]
SW
[1:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x08
RCC_CIR
Reserved
C
S
S
C
R
e
s
e
r
v
e
d
P
L
L
R
D
Y
C
H
S
E
R
D
Y
C
H
S
I
R
D
Y
C
L
S
E
R
D
Y
C
L
S
I
R
D
Y
C
R
e
s
e
r
v
e
d
P
L
L
R
D
Y
I
E
H
S
E
R
D
Y
I
E
H
S
I
R
D
Y
I
E
L
S
E
R
D
Y
I
E
L
S
I
R
D
Y
I
E
C
S
S
F
R
e
s
e
r
v
e
d
P
L
L
R
D
Y
F
H
S
E
R
D
Y
F
H
S
I
R
D
Y
F
L
S
E
R
D
Y
F
L
S
I
R
D
Y
F
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x0C
RCC_APB2RSTR
Reserved
T
I
M
1
1
R
S
T
T
I
M
1
0
R
S
T
T
I
M
9
R
S
T
R
e
s
e
r
v
e
d
A
D
C
3
R
S
T
U
S
A
R
T
1
R
S
T
T
I
M
8
R
S
T
S
P
I
1
R
S
T
T
I
M
1
R
S
T
A
D
C
2
R
S
T
A
D
C
1
R
S
T
I
O
P
G
R
S
T
I
O
P
F
R
S
T
I
O
P
E
R
S
T
I
O
P
D
R
S
T
I
O
P
C
R
S
T
I
O
P
B
R
S
T
I
O
P
A
R
S
T
R
e
s
e
r
v
e
d
A
F
I
O
R
S
T
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x010
RCC_APB1RSTR
R
e
s
e
r
v
e
d
D
A
C
R
S
T
P
W
R
R
S
T
B
K
P
R
S
T
R
e
s
e
r
v
e
d
C
A
N
R
S
T
R
e
s
e
r
v
e
d
U
S
B
R
S
T
I
2
C
2
R
S
T
I
2
C
1
R
S
T
U
A
R
T
5
R
S
T
U
A
R
T
4
R
S
T
U
S
A
R
T
3
R
S
T
U
S
A
R
T
2
R
S
T
R
e
s
e
r
v
e
d
S
P
I
3
R
S
T
S
P
I
2
R
S
T
R
e
s
e
r
v
e
d
W
W
D
G
R
S
T
Reser
ved
T
I
M
1
4
R
S
T
T
I
M
1
3
R
S
T
T
I
M
1
2
R
S
T
T
M
7
R
S
T
T
M
6
R
S
T
T
M
5
R
S
T
T
I
M
4
R
S
T
T
I
M
3
R
S
T
T
I
M
2
R
S
T
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x14
RCC_AHBENR
Reserved
S
D
I
O
E
N
R
e
s
e
r
v
e
d
F
S
M
C
E
N
R
e
s
e
r
v
e
d
C
R
C
E
N
R
e
s
e
r
v
e
d
F
L
I
T
F
E
N
R
e
s
e
r
v
e
d
S
R
A
M
E
N
D
M
2
A
E
N
D
M
1
A
E
N
Reset value 0 0 0 1 1 0 0
0x18
RCC_APB2ENR
Reserved
T
I
M
1
1

E
N
T
I
M
1
0

E
N
T
I
M
9

E
N
Reserved
A
D
C
3
E
N
U
S
A
R
T
1
E
N
T
I
M
8
E
N
S
P
I
1
E
N
T
I
M
1
E
N
A
D
C
2
E
N
A
D
C
1
E
N
I
O
P
G
E
N
I
O
P
F
E
N
I
O
P
E
E
N
I
O
P
D
E
N
I
O
P
C
E
N
I
O
P
B
E
N
I
O
P
A
E
N
R
e
s
e
r
v
e
d
A
F
I
O
E
N
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x1C
RCC_APB1ENR
R
e
s
e
r
v
e
d
D
A
C
E
N
P
W
R
E
N
B
K
P
E
N
R
e
s
e
r
v
e
d
C
A
N
E
N
R
e
s
e
r
v
e
d
U
S
B
E
N
I
2
C
2
E
N
I
2
C
1
E
N
U
A
R
T
5
E
N
U
A
R
T
4
E
N
U
S
A
R
T
3
E
N
U
S
A
R
T
2
E
N
R
e
s
e
r
v
e
d
S
P
I
3
E
N
S
P
I
2
E
N
R
e
s
e
r
v
e
d
W
W
D
G
E
N
R
e
s
e
r
v
e
d
T
I
M
1
4
E
N
T
I
M
1
3
E
N
T
I
M
1
2
E
N
T
I
M
7
E
N
T
I
M
6
E
N
T
I
M
5
E
N
T
I
M
4
E
N
T
I
M
3
E
N
T
I
M
2
E
N
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x20
RCC_BDCR
Reserved
B
D
R
S
T
R
T
C
E
N
Reserved
RTC
SEL
[1:0]
Reserved
L
S
E
B
Y
P
L
S
E
R
D
Y
L
S
E
O
N
Reset value 0 0 0 0 0 0 0
0x24
RCC_CSR
L
P
W
R
S
T
F
W
W
D
G
R
S
T
F
I
W
D
G
R
S
T
F
S
F
T
R
S
T
F
P
O
R
R
S
T
F
P
I
N
R
S
T
F
R
e
s
e
r
v
e
d
R
M
V
F
Reserved
L
S
I
R
D
Y
L
S
I
O
N
Reset value 0 0 0 0 1 1 0 0 0

Connectivity line devices: reset and clock control (RCC) RM0008
120/1093 Doc ID 13902 Rev 13
8 Connectivity line devices: reset and clock control
(RCC)
Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx
microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx
microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
High-density devices are STM32F101xx and STM32F103xx microcontrollers where the
Flash memory density ranges between 256 and 512 Kbytes.
XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the
Flash memory density ranges between 768 Kbytes and 1 Mbyte.
Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
This Section applies to all connectivity line devices, unless otherwise specified.
8.1 Reset
There are three types of reset, defined as system reset, power reset and backup domain
reset.
8.1.1 System reset
A system reset sets all registers to their reset values except the reset flags in the clock
controller CSR register and the registers in the Backup domain (see Figure 4).
A system reset is generated when one of the following events occurs:
1. A low level on the NRST pin (external reset)
2. Window watchdog end of count condition (WWDG reset)
3. Independent watchdog end of count condition (IWDG reset)
4. A software reset (SW reset) (see Software reset)
5. Low-power management reset (see Low-power management reset)
The reset source can be identified by checking the reset flags in the Control/Status register,
RCC_CSR (see Section 8.3.10: Control/status register (RCC_CSR)).
Software reset
The SYSRESETREQ bit in Cortex-M3 Application Interrupt and Reset Control Register
must be set to force a software reset on the device. Refer to the STM32F10xxx Cortex-M3
programming manual (see Related documents on page 1) for more details.
RM0008 Connectivity line devices: reset and clock control (RCC)
Doc ID 13902 Rev 13 121/1093

Low-power management reset
There are two ways to generate a low-power management reset:
1. Reset generated when entering Standby mode:
This type of reset is enabled by resetting nRST_STDBY bit in User Option Bytes. In this
case, whenever a Standby mode entry sequence is successfully executed, the device
is reset instead of entering Standby mode.
2. Reset when entering Stop mode:
This type of reset is enabled by resetting nRST_STOP bit in User Option Bytes. In this
case, whenever a Stop mode entry sequence is successfully executed, the device is
reset instead of entering Stop mode.
For further information on the User Option Bytes, refer to the STM32F10xxx Flash
programming manual.
8.1.2 Power reset
A power reset is generated when one of the following events occurs:
1. Power-on/power-down reset (POR/PDR reset)
2. When exiting Standby mode
A power reset sets all registers to their reset values except the Backup domain (see
Figure 4)
These sources act on the NRST pin and it is always kept low during the delay phase. The
RESET service routine vector is fixed at address 0x0000_0004 in the memory map. For more
details, refer to Table 63: Vector table for other STM32F10xxx devices on page 196.
The system reset signal provided to the device is output on the NRST pin. The pulse
generator guarantees a minimum reset pulse duration of 20 s for each reset source
(external or internal reset). In case of an external reset, the reset pulse is generated while
the NRST pin is asserted low.
Figure 10. Simplified diagram of the reset circuit
NRST
R
PU
V
DD
/V
DDA
WWDG reset
WDG reset
Pulse
generator
Power reset
External
reset
(min 20 s)
System reset
Filter
Software reset
Low-power management reset
ai16095b

Connectivity line devices: reset and clock control (RCC) RM0008
122/1093 Doc ID 13902 Rev 13
8.1.3 Backup domain reset
The backup domain has two specific resets that affect only the backup domain (see
Figure 4).
A backup domain reset is generated when one of the following events occurs:
1. Software reset, triggered by setting the BDRST bit in the Backup domain control
register (RCC_BDCR).
2. V
DD
or V
BAT
power on, if both supplies have previously been powered off.
8.2 Clocks
Three different clock sources can be used to drive the system clock (SYSCLK):
HSI oscillator clock
HSE oscillator clock
PLL clock
The devices have the following two secondary clock sources:
40 kHz low speed internal RC (LSI RC) which drives the independent watchdog and
optionally the RTC used for Auto-wakeup from Stop/Standby mode.
32.768 kHz low speed external crystal (LSE crystal) which optionally drives the real-
time clock (RTCCLK)
Each clock source can be switched on or off independently when it is not used, to optimize
power consumption.
RM0008 Connectivity line devices: reset and clock control (RCC)
Doc ID 13902 Rev 13 123/1093

Figure 11. Clock tree
1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is
36 MHz.
2. For full details about the internal and external clock source characteristics, please refer to the Electrical
characteristics section in your device datasheet.
The advanced clock controller features 3 PLLs to provide a high degree of flexibility to the
application in the choice of the external crystal or oscillator to run the core and peripherals
at the highest frequency and guarantee the appropriate frequency for the Ethernet and USB
OTG FS.
A single 25 MHz crystal can clock the entire system and all peripherals including the
Ethernet and USB OTG FS peripherals. In order to achieve high-quality audio performance,
an audio crystal can be used. In this case, the I2S master clock can generate all standard
sampling frequencies from 8 kHz to 96 kHz with less than 0.5% accuracy.
For more details about clock configuration for applications requiring Ethernet, USB OTG FS
and/or I
2
S (audio), please refer to "Appendix A Applicative block diagrams" in your
connectivity line device datasheet.
PLLMUL
PLL2MUL
PLL3MUL
PLLCLK
PLL2CLK
PLL3CLK to MCO
PREDIV1SCR
PREDIV2
x4, x5,... x9,
x6.5
x8, x9,... x14,
x16, x20
x8, x9,... x14,
x16, x20
/1,2,3....
..../15, /16
/1,2,3....
..../15, /16
HSE
OSC
8 MHz
HSI RC
/2
HSI
HSE
SW
SYSCLK
/128
PREDIV1
PLLSCR
CSS
LSE
OSC
LSI
RC
/2,3
USB prescaler
RTCSEL[1:0]
LSE
LSI
IWDGCLK
to independent watchdog
to RTC
RTCCLK
OTGFSCLK
48 MHz
to USB OTG FS
3-25 MHz
32.768 kHz
40 kHz
to I2S3 interface
to I2S2 interface
to MCO
OSC32_IN
OSC32_OUT
OSC_IN
OSC_OUT
XT1 to MCO
AHB prescaler
/1,/2 ../512
APB1 prescaler
/1, 2, 4, 8, 16
APB2 prescaler
/1, 2, 4, 8, 16
TIM2,3,4,5,6,7
If(APB1 prescaler =1) x1
else x2
TIM1
If(APB2 prescaler =1) x1
else x2
ADC prescaler
/2, 4, 6, 8
TIMxCLK
to TIM2,3,4,5,
6 & 7
Peripheral clock enable
36 MHz max
PCLK1
to APB1 peripherals
Peripheral clock enable
72 MHz max
PCLK2
to APB2 peripherals
TIMxCLK
to TIM1
Peripheral clock enable
Peripheral clock enable
HCLK to AHB bus, core memory and DMA
/8 to Cortex System timer
FCLK Cortex free running clock
ADCCLK
to ADC1,2
SYSCLK
72 MHz max.
HSE
HSI
PLLCLK/2
PLL2CLK
PLL3CLK/2
PLL3CLK
XT1
MCO[3:0]
MCO
Ethernet
PHY
ETH_MII_TX_CLK
ETH_MII_RX_CLK
/2, /20
to Ethernet MAC
MACTXCLK
MACRXCLK
MACRMIICLK
(see note1)
system clock
to Flash prog. IF FLITFCLK
PLLVCO (2 PLLCLK)
MII_RMII_SEL
in AFIO_MAPR
ai15699d
14 MHz max

PLL3VCO
(2 PLL3CLK)

Connectivity line devices: reset and clock control (RCC) RM0008
124/1093 Doc ID 13902 Rev 13
Several prescalers allow the configuration of the AHB frequency, the high speed APB
(APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and
the APB2 domains is 72 MHz. The maximum allowed frequency of the APB1 domain is
36 MHz.
All peripheral clocks are derived from the system clock (SYSCLK) except:
The Flash memory programming interface clock (FLITFCLK) is always the HSI clock
The USB OTG FS 48 MHz clock which is derived from the PLL VCO clock (2
PLLCLK), followed by a programmable prescaler (divide by 3 or 2). This selection is
made through the OTGFSPRE bit in the RCC_CFGR register. For proper USB OTG FS
operation, the PLL should be configured to output 72 MHz or 48 MHz.
The I2S2 and I2S3 clocks which can be derived from the system clock (SYSCLK) or the
PLL3 VCO clock (2 PLL3CLK). This selection is made through the I2SxSRC bit in the
RCC_CFGR2 register. For more information on PLL3 and how to configure the I2S
clock to achieve high-quality audio performance, please refer to Section 25.4.3: Clock
generator.
The Ethernet MAC clocks (TX, RX and RMII) which are provided from the external
PHY. For further information on the Ethernet configuration, please refer to
Section 29.4.4: MII/RMII selection.
When the Ethernet is used, the AHB clock frequency must be at least 25 MHz.
The RCC feeds the Cortex System Timer (SysTick) external clock with the AHB clock
(HCLK) divided by 8. The SysTick can work either with this clock or with the Cortex clock
(HCLK), configurable in the SysTick Control and Status Register. The ADCs are clocked by
the clock of the High Speed domain (APB2) divided by 2, 4, 6 or 8.
The timer clock frequencies are automatically fixed by hardware. There are two cases:
1. if the APB prescaler is 1, the timer clock frequencies are set to the same frequency as
that of the APB domain to which the timers are connected.
2. otherwise, they are set to twice (2) the frequency of the APB domain to which the
timers are connected.
FCLK acts as Cortex-M3s free-running clock. For more details refer to the ARM Cortex-
M3 r1p1 Technical Reference Manual (TRM).
8.2.1 HSE clock
The high speed external clock signal (HSE) can be generated from two possible clock
sources:
HSE external crystal/ceramic resonator
HSE user external clock
The resonator and the load capacitors have to be placed as close as possible to the
oscillator pins in order to minimize output distortion and startup stabilization time. The
loading capacitance values must be adjusted according to the selected oscillator.
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External source (HSE bypass)
In this mode, an external clock source must be provided. It can have a frequency of up to
50 MHz. You select this mode by setting the HSEBYP and HSEON bits in the Clock control
register (RCC_CR). The external clock signal (square, sinus or triangle) with ~50% duty
cycle has to drive the OSC_IN pin while the OSC_OUT pin should be left hi-Z. See
Figure 12.
External crystal/ceramic resonator (HSE crystal)
The 3 to 25 MHz external oscillator has the advantage of producing a very accurate rate on
the main clock.
The associated hardware configuration is shown in Figure 12. Refer to the electrical
characteristics section of the datasheet for more details.
The HSERDY flag in the Clock control register (RCC_CR) indicates if the high-speed
external oscillator is stable or not. At startup, the clock is not released until this bit is set by
hardware. An interrupt can be generated if enabled in the Clock interrupt register
(RCC_CIR).
The HSE crystal can be switched on and off using the HSEON bit in the Clock control
register (RCC_CR).
8.2.2 HSI clock
The HSI clock signal is generated from an internal 8 MHz RC Oscillator and can be used
directly as a system clock or divided by 2 to be used as PLL input.
The HSI RC oscillator has the advantage of providing a clock source at low cost (no external
components). It also has a faster startup time than the HSE crystal oscillator however, even
with calibration the frequency is less accurate than an external crystal oscillator or ceramic
resonator.
Figure 12. HSE/ LSE clock sources
Clock source Hardware configuration
External clock
Crystal/ceramic
resonators
OSC_OUT
External
source
(HiZ)
OSC_IN OSC_OUT
Load
capacitors
C
L2
C
L1

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Calibration
RC oscillator frequencies can vary from one chip to another due to manufacturing process
variations, this is why each device is factory calibrated by ST for 1% accuracy at T
A
= 25 C.
After reset, the factory calibration value is loaded in the HSICAL[7:0] bits in the Clock control
register (RCC_CR).
If the application is subject to voltage or temperature variations this may affect the RC
oscillator speed. You can trim the HSI frequency in the application using the HSITRIM[4:0]
bits in the Clock control register (RCC_CR).
The HSIRDY flag in the Clock control register (RCC_CR) indicates if the HSI RC is stable or
not. At startup, the HSI RC output clock is not released until this bit is set by hardware.
The HSI RC can be switched on and off using the HSION bit in the Clock control register
(RCC_CR).
The HSI signal can also be used as a backup source (Auxiliary clock) if the HSE crystal
oscillator fails. Refer to Section 8.2.7: Clock security system (CSS) on page 128.
8.2.3 PLLs
The main PLL provides a frequency multiplier starting from one of the following clock
sources:
HSI clock divided by 2
HSE or PLL2 clock through a configurable divider
Refer to Figure 11 and Clock control register (RCC_CR).
PLL2 and PLL3 are clocked by HSE through a specific configurable divider. Refer to
Figure 11 and Clock configuration register2 (RCC_CFGR2)
The configuration of each PLL (selection of clock source, predivision factor and
multiplication factor) must be done before enabling the PLL. Each PLL should be enabled
after its input clock becomes stable (ready flag). Once the PLL is enabled, these parameters
can not be changed.
When changing the entry clock source of the main PLL, the original clock source must be
switched off only after the selection of the new clock source (done through bit PLLSRC in
the Clock configuration register (RCC_CFGR)).
An interrupt can be generated when the PLL is ready if enabled in the Clock interrupt
register (RCC_CIR).
8.2.4 LSE clock
The LSE crystal is a 32.768 kHz Low Speed External crystal or ceramic resonator. It has the
advantage providing a low-power but highly accurate clock source to the real-time clock
peripheral (RTC) for clock/calendar or other timing functions.
The LSE crystal is switched on and off using the LSEON bit in Backup domain control
register (RCC_BDCR).
The LSERDY flag in the Backup domain control register (RCC_BDCR) indicates if the LSE
crystal is stable or not. At startup, the LSE crystal output clock signal is not released until
this bit is set by hardware. An interrupt can be generated if enabled in the Clock interrupt
register (RCC_CIR).
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External source (LSE bypass)
In this mode, an external clock source must be provided. It can have a frequency of up to
1 MHz. You select this mode by setting the LSEBYP and LSEON bits in the Backup domain
control register (RCC_BDCR). The external clock signal (square, sinus or triangle) with
~50% duty cycle has to drive the OSC32_IN pin while the OSC32_OUT pin should be left
Hi-Z. See Figure 12.
8.2.5 LSI clock
The LSI RC acts as an low-power clock source that can be kept running in Stop and
Standby mode for the independent watchdog (IWDG) and Auto-wakeup unit (AWU). The
clock frequency is around 40 kHz (between 30 kHz and 60 kHz). For more details, refer to
the electrical characteristics section of the datasheets.
The LSI RC can be switched on and off using the LSION bit in the Control/status register
(RCC_CSR).
The LSIRDY flag in the Control/status register (RCC_CSR) indicates if the low-speed
internal oscillator is stable or not. At startup, the clock is not released until this bit is set by
hardware. An interrupt can be generated if enabled in the Clock interrupt register
(RCC_CIR).
LSI calibration
The frequency dispersion of the Low Speed Internal RC (LSI) oscillator can be calibrated to
have accurate RTC time base and/or IWDG timeout (when LSI is used as clock source for
these peripherals) with an acceptable accuracy.
This calibration is performed by measuring the LSI clock frequency with respect to TIM5
input clock (TIM5CLK). According to this measurement done at the precision of the HSE
oscillator, the software can adjust the programmable 20-bit prescaler of the RTC to get an
accurate time base or can compute accurate IWDG timeout.
Use the following procedure to calibrate the LSI:
1. Enable TIM5 timer and configure channel4 in input capture mode
2. Set the TIM5CH4_IREMAP bit in the AFIO_MAPR register to connect the LSI clock
internally to TIM5 channel4 input capture for calibration purpose.
3. Measure the frequency of LSI clock using the TIM5 Capture/compare 4 event or
interrupt.
4. Use the measured LSI frequency to update the 20-bit prescaler of the RTC depending
on the desired time base and/or to compute the IWDG timeout.
8.2.6 System clock (SYSCLK) selection
After a system reset, the HSI oscillator is selected as system clock. When a clock source is
used directly or through the PLL as the system clock, it is not possible to stop it.
A switch from one clock source to another occurs only if the target clock source is ready
(clock stable after startup delay or PLL locked). If a clock source which is not yet ready is
selected, the switch will occur when the clock source will be ready. Status bits in the Clock
control register (RCC_CR) indicate which clock(s) is (are) ready and which clock is currently
used as system clock.

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8.2.7 Clock security system (CSS)
Clock Security System can be activated by software. In this case, the clock detector is
enabled after the HSE oscillator startup delay, and disabled when this oscillator is stopped.
a failure is detected on the HSE clock, the HSE Oscillator is automatically disabled, a clock
failure event is sent to the break input of the TIM1 Advanced control timer and an interrupt is
generated to inform the software about the failure (Clock Security System Interrupt CSSI),
allowing the MCU to perform rescue operations. The CSSI is linked to the Cortex-M3 NMI
(Non-Maskable Interrupt) exception vector.
Note: Once the CSS is enabled and if the HSE clock fails, the CSS interrupt occurs and an NMI is
automatically generated. The NMI will be executed indefinitely unless the CSS interrupt
pending bit is cleared. As a consequence, in the NMI ISR user must clear the CSS interrupt
by setting the CSSC bit in the Clock interrupt register (RCC_CIR).
If the HSE oscillator is used directly or indirectly as the system clock (indirectly means: it is
used as PLL input clock directly or through PLL2, and the PLL clock is used as system
clock), a detected failure causes a switch of the system clock to the HSI oscillator and the
disabling of the external HSE oscillator. If the HSE oscillator clock (divided or not) is the
clock entry of the PLL (directly or through PLL2) used as system clock when the failure
occurs, the PLL is disabled too.
8.2.8 RTC clock
The RTCCLK clock source can be either the HSE/128, LSE or LSI clocks. This is selected
by programming the RTCSEL[1:0] bits in the Backup domain control register (RCC_BDCR).
This selection cannot be modified without resetting the Backup domain.
The LSE clock is in the Backup domain, whereas the HSE and LSI clocks are not.
Consequently:
If LSE is selected as RTC clock:
The RTC continues to work even if the V
DD
supply is switched off, provided the
V
BAT
supply is maintained.
If LSI is selected as Auto-Wakeup unit (AWU) clock:
The AWU state is not guaranteed if the V
DD
supply is powered off. Refer to
Section 8.2.5: LSI clock on page 127 for more details on LSI calibration.
If the HSE clock divided by 128 is used as RTC clock:
The RTC state is not guaranteed if the V
DD
supply is powered off or if the internal
voltage regulator is powered off (removing power from the 1.8 V domain).
The DPB bit (Disable backup domain write protection) in the Power controller
register must be set to 1 (refer to Section 5.4.1: Power control register
(PWR_CR)).
8.2.9 Watchdog clock
If the Independent watchdog (IWDG) is started by either hardware option or software
access, the LSI oscillator is forced ON and cannot be disabled. After the LSI oscillator
temporization, the clock is provided to the IWDG.
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8.2.10 Clock-out capability
The microcontroller clock output (MCO) capability allows the clock to be output onto the
external MCO pin. The configuration registers of the corresponding GPIO port must be
programmed in alternate function mode. One of 8 clock signals can be selected as the MCO
clock.
SYSCLK
HSI
HSE
PLL clock divided by 2 selected
PLL2 clock selected
PLL3 clock divided by 2 selected
XT1 external 3-25 MHz oscillator clock selected (for Ethernet)
PLL3 clock selected (for Ethernet)
The selected clock to output onto MCO must not exceed 50 MHz (the maximum I/O speed).
The selection is controlled by the MCO[3:0] bits of the Clock configuration register
(RCC_CFGR).
8.3 RCC registers
Refer to Section 2.1 on page 46 for a list of abbreviations used in register descriptions.
8.3.1 Clock control register (RCC_CR)
Address offset: 0x00
Reset value: 0x0000 XX83 where X is undefined.
Access: no wait state, word, half-word and byte access


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
PLL3
RDY
PLL3
ON
PLL2
RDY
PLL2
ON
PLLRDY PLLON
Reserved
CSSON HSEBYP HSERDY HSEON
r rw r rw r rw rw rw r rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSICAL[7:0] HSITRIM[4:0]
Res.
HSIRDY HSION
r r r r r r r r rw rw rw rw rw r rw
Bits 31:30 Reserved, must be kept at reset value.
Bit 29 PLL3RDY: PLL3 clock ready flag
Set by hardware to indicate that the PLL3 is locked.
0: PLL3 unlocked
1: PLL3 locked
Bit 28 PLL3ON: PLL3 enable
Set and cleared by software to enable PLL3.
Cleared by hardware when entering Stop or Standby mode.
0: PLL3 OFF
1: PLL3 ON

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Bit 27 PLL2RDY: PLL2 clock ready flag
Set by hardware to indicate that the PLL2 is locked.
0: PLL2 unlocked
1: PLL2 locked
Bit 26 PLL2ON: PLL2 enable
Set and cleared by software to enable PLL2.
Cleared by hardware when entering Stop or Standby mode. This bit can not be cleared if
the PLL2 clock is used indirectly as system clock (i.e. it is used as PLL clock entry that is
used as system clock).
0: PLL2 OFF
1: PLL2 ON
Bit 25 PLLRDY: PLL clock ready flag
Set by hardware to indicate that the PLL is locked.
0: PLL unlocked
1: PLL locked
Bit 24 PLLON: PLL enable
Set and cleared by software to enable PLL.
Cleared by hardware when entering Stop or Standby mode. This bit can not be reset if the
PLL clock is used as system clock or is selected to become the system clock. Software
must disable the USB OTG FS clock before clearing this bit.
0: PLL OFF
1: PLL ON
Bits 23:20 Reserved, must be kept at reset value.
Bit 19 CSSON: Clock security system enable
Set and cleared by software to enable the clock security system. When CSSON is set, the
clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by
hardware if a HSE clock failure is detected.
0: Clock detector OFF
1: Clock detector ON (Clock detector ON if the HSE oscillator is ready, OFF if not)
Bit 18 HSEBYP: External high-speed clock bypass
Set and cleared by software to bypass the oscillator with an external clock. The external
clock must be enabled with the HSEON bit set, to be used by the device. The HSEBYP bit
can be written only if the HSE oscillator is disabled.
0: external 3-25 MHz oscillator not bypassed
1: external 3-25 MHz oscillator bypassed with external clock
Bit 17 HSERDY: External high-speed clock ready flag
Set by hardware to indicate that the HSE oscillator is stable. This bit needs 6 cycles of the
HSE oscillator clock to fall down after HSEON reset.
0: HSE oscillator not ready
1: HSE oscillator ready
Bit 16 HSEON: HSE clock enable
Set and cleared by software.
Cleared by hardware to stop the HSE oscillator when entering Stop or Standby mode. This
bit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock.
0: HSE oscillator OFF
1: HSE oscillator ON
Bits 15:8 HSICAL[7:0]: Internal high-speed clock calibration
These bits are initialized automatically at startup.
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8.3.2 Clock configuration register (RCC_CFGR)
Address offset: 0x04
Reset value: 0x0000 0000
Access: 0 wait state 2, word, half-word and byte access
1 or 2 wait states inserted only if the access occurs during a clock source switch.


Bits 7:3 HSITRIM[4:0]: Internal high-speed clock trimming
These bits provide an additional user-programmable trimming value that is added to the
HSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature
that influence the frequency of the internal HSI RC.
The default value is 16, which, when added to the HSICAL value, should trim the HSI to 8
MHz 1%. The trimming step (F
hsitrim
) is around 40 kHz between two consecutive HSICAL
steps.
Bit 2 Reserved, must be kept at reset value.
Bit 1 HSIRDY: Internal high-speed clock ready flag
Set by hardware to indicate that internal 8 MHz RC oscillator is stable. After the HSION bit is
cleared, HSIRDY goes low after 6 internal 8 MHz RC oscillator clock cycles.
0: Internal 8 MHz RC oscillator not ready
1: Internal 8 MHz RC oscillator ready
Bit 0 HSION: Internal high-speed clock enable
Set and cleared by software.
Set by hardware to force the internal 8 MHz RC oscillator ON when leaving Stop or Standby
mode or in case of failure of the external 3-25 MHz oscillator used directly or indirectly as
system clock. This bit can not be cleared if the internal 8 MHz RC is used directly or
indirectly as system clock or is selected to become the system clock.
0: Internal 8 MHz RC oscillator OFF
1: Internal 8 MHz RC oscillator ON
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
MCO[3:0]
Res.
OTGFS
PRE
PLLMUL[3:0]
PLL
XTPRE
PLL
SRC
rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADC PRE[1:0] PPRE2[2:0] PPRE1[2:0] HPRE[3:0] SWS[1:0] SW[1:0]
rw rw rw rw rw rw rw rw rw rw rw rw r r rw rw
Bits 31:27 Reserved, must be kept at reset value.

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Bits 26:24 MCO[3:0]: Microcontroller clock output
Set and cleared by software.
00xx: No clock
0100: System clock (SYSCLK) selected
0101: HSI clock selected
0110: HSE clock selected
0111: PLL clock divided by 2 selected
1000: PLL2 clock selected
1001: PLL3 clock divided by 2 selected
1010: XT1 external 3-25 MHz oscillator clock selected (for Ethernet)
1011: PLL3 clock selected (for Ethernet)
Note: This clock output may have some truncated cycles at startup or during MCO clock source
switching.
The selected clock to output onto the MCO pin must not exceed 50 MHz (the maximum I/O
speed).
Bit 22 OTGFSPRE: USB OTG FS prescaler
Set and cleared by software to generate the 48 MHz USB OTG FS clock. This bit must be valid
before enabling the OTG FS clock in the RCC_APB1ENR register. This bit can not be cleared if the
OTG FS clock is enabled.
0: PLL VCO (2 PLLCLK) clock is divided by 3 (PLL must be configured to output 72 MHz)
1: PLL VCO (2 PLLCLK) clock is divided by 2 (PLL must be configured to output 48 MHz)
Bits 21:18 PLLMUL[3:0]: PLL multiplication factor
These bits are written by software to define the PLL multiplication factor. They can be written only
when PLL is disabled.
000x: Reserved
0010: PLL input clock x 4
0011: PLL input clock x 5
0100: PLL input clock x 6
0101: PLL input clock x 7
0110: PLL input clock x 8
0111: PLL input clock x 9
10xx: Reserved
1100: Reserved
1101: PLL input clock x 6.5
111x: Reserved
Caution: The PLL output frequency must not exceed 72 MHz.
Bit 17 PLLXTPRE: LSB of division factor PREDIV1
Set and cleared by software to select the least significant bit of the PREDIV1 division factor. It is the
same bit as bit(0) in the RCC_CFGR2 register, so modifying bit(0) in the RCC_CFGR2 register
changes this bit accordingly.
If bits[3:1] in register RCC_CFGR2 are not set, this bit controls if PREDIV1 divides its input clock by
2 (PLLXTPRE=1) or not (PLLXTPRE=0).
This bit can be written only when PLL is disabled.
Bit 16 PLLSRC: PLL entry clock source
Set and cleared by software to select PLL clock source. This bit can be written only when PLL is
disabled.
0: HSI oscillator clock / 2 selected as PLL input clock
1: Clock from PREDIV1 selected as PLL input clock
Note: When changing the main PLLs entry clock source, the original clock source must be switched
off only after the selection of the new clock source.
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Bits 14:14 ADCPRE[1:0]: ADC prescaler
Set and cleared by software to select the frequency of the clock to the ADCs.
00: PCLK2 divided by 2
01: PCLK2 divided by 4
10: PCLK2 divided by 6
11: PCLK2 divided by 8
Bits 13:11 PPRE2[2:0]: APB high-speed prescaler (APB2)
Set and cleared by software to control the division factor of the APB High speed clock (PCLK2).
0xx: HCLK not divided
100: HCLK divided by 2
101: HCLK divided by 4
110: HCLK divided by 8
111: HCLK divided by 16
Bits 10:8 PPRE1[2:0]: APB Low-speed prescaler (APB1)
Set and cleared by software to control the division factor of the APB Low speed clock (PCLK1).
0xx: HCLK not divided
100: HCLK divided by 2
101: HCLK divided by 4
110: HCLK divided by 8
111: HCLK divided by 16
Caution: Software must configure these bits ensure that the frequency in this domain does not
exceed 36 MHz.
Bits 7:4 HPRE[3:0]: AHB prescaler
Set and cleared by software to control AHB clock division factor.
0xxx: SYSCLK not divided
1000: SYSCLK divided by 2
1001: SYSCLK divided by 4
1010: SYSCLK divided by 8
1011: SYSCLK divided by 16
1100: SYSCLK divided by 64
1101: SYSCLK divided by 128
1110: SYSCLK divided by 256
1111: SYSCLK divided by 512
Note: The prefetch buffer must be kept on when using a prescaler different from 1 on the AHB clock.
Refer to the section Reading the Flash memory on page 58 for more details.
Caution: The AHB clock frequency must be at least 25 MHz when the Ethernet is used.
Bits 3:2 SWS[1:0]: System clock switch status
Set and cleared by hardware to indicate which clock source is used as system clock.
00: HSI oscillator used as system clock
01: HSE oscillator used as system clock
10: PLL used as system clock
11: Not applicable

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8.3.3 Clock interrupt register (RCC_CIR)
Address offset: 0x08
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access


Bits 1:0 SW[1:0]: System clock Switch
Set and cleared by software to select SYSCLK source.
Set by hardware to force HSI selection when leaving Stop and Standby mode or in case of failure of
the HSE oscillator used directly or indirectly as system clock (if the Clock Security System is
enabled).
00: HSI selected as system clock
01: HSE selected as system clock
10: PLL selected as system clock
11: Not allowed
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
CSSC
PLL3
RDYC
PLL2
RDYC
PLL
RDYC
HSE
RDYC
HSI
RDYC
LSE
RDYC
LSI
RDYC
w w w w w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res.
PLL3
RDYIE
PLL2
RDYIE
PLL
RDYIE
HSE
RDYIE
HSI
RDYIE
LSE
RDYIE
LSI
RDYIE
CSSF
PLL3
RDYF
PLL2
RDYF
PLL
RDYF
HSE
RDYF
HSI
RDYF
LSE
RDYF
LSI
RDYF
rw rw rw rw rw rw rw r r r r r r r r
Bits 31:24 Reserved, must be kept at reset value.
Bit 23 CSSC: Clock security system interrupt clear
This bit is set by software to clear the CSSF flag.
0: No effect
1: Clear CSSF flag
Bit 22 PLL3RDYC: PLL3 Ready Interrupt Clear
This bit is set by software to clear the PLL3RDYF flag.
0: No effect
1: Clear PLL3RDYF flag
Bit 21 PLL2RDYC: PLL2 Ready Interrupt Clear
This bit is set by software to clear the PLL2RDYF flag.
0: No effect
1: Clear PLL2RDYF flag
Bit 20 PLLRDYC: PLL ready interrupt clear
This bit is set by software to clear the PLLRDYF flag.
0: No effect
1: Clear PLLRDYF flag
Bit 19 HSERDYC: HSE ready interrupt clear
This bit is set by software to clear the HSERDYF flag.
0: No effect
1: Clear HSERDYF flag
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Bit 18 HSIRDYC: HSI ready interrupt clear
This bit is set by software to clear the HSIRDYF flag.
0: No effect
1: Clear HSIRDYF flag
Bit 17 LSERDYC: LSE ready interrupt clear
This bit is set by software to clear the LSERDYF flag.
0: No effect
1: Clear LSERDYF flag
Bit 16 LSIRDYC: LSI ready interrupt clear
This bit is set by software to clear the LSIRDYF flag.
0: No effect
1: Clear LSIRDYF flag
Bit 15 Reserved, must be kept at reset value.
Bit 14 PLL3RDYIE: PLL3 Ready Interrupt Enable
Set and cleared by software to enable/disable interrupt caused by PLL3 lock.
0: PLL3 lock interrupt disabled
1: PLL3 lock interrupt enabled
Bit 13 PLL2RDYIE: PLL2 Ready Interrupt Enable
Set and cleared by software to enable/disable interrupt caused by PLL2 lock.
0: PLL2 lock interrupt disabled
1: PLL2 lock interrupt enabled
Bit 12 PLLRDYIE: PLL ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by PLL lock.
0: PLL lock interrupt disabled
1: PLL lock interrupt enabled
Bit 11 HSERDYIE: HSE ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by the external 3-25 MHz
oscillator stabilization.
0: HSE ready interrupt disabled
1: HSE ready interrupt enabled
Bit 10 HSIRDYIE: HSI ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by the internal 8 MHz RC
oscillator stabilization.
0: HSI ready interrupt disabled
1: HSI ready interrupt enabled
Bit 9 LSERDYIE: LSE ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by the external 32 kHz
oscillator stabilization.
0: LSE ready interrupt disabled
1: LSE ready interrupt enabled
Bit 8 LSIRDYIE: LSI ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by internal RC 40 kHz
oscillator stabilization.
0: LSI ready interrupt disabled
1: LSI ready interrupt enabled

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Bit 7 CSSF: Clock security system interrupt flag
Set by hardware when a failure is detected in the external 3-25 MHz oscillator. It is cleared
by software setting the CSSC bit.
0: No clock security interrupt caused by HSE clock failure
1: Clock security interrupt caused by HSE clock failure
Bit 6 PLL3RDYF: PLL3 Ready Interrupt flag
Set by hardware when the PLL3 locks and PLL3RDYIE is set. It is cleared by software
setting the PLL3RDYC bit.
0: No clock ready interrupt caused by PLL3 lock
1: Clock ready interrupt caused by PLL3 lock
Bit 5 PLL2RDYF: PLL2 Ready Interrupt flag
Set by hardware when the PLL2 locks and PLL2RDYDIE is set. It is cleared by software
setting the PLL2RDYC bit.
0: No clock ready interrupt caused by PLL2 lock
1: Clock ready interrupt caused by PLL2 lock
Bit 4 PLLRDYF: PLL ready interrupt flag
Set by hardware when the PLL locks and PLLRDYDIE is set. It is cleared by software setting
the PLLRDYC bit.
0: No clock ready interrupt caused by PLL lock
1: Clock ready interrupt caused by PLL lock
Bit3 HSERDYF: HSE ready interrupt flag
Set by hardware when External Low Speed clock becomes stable and HSERDYIE is set. It
is cleared by software setting the HSERDYC bit.
0: No clock ready interrupt caused by the external 3-25 MHz oscillator
1: Clock ready interrupt caused by the external 3-25 MHz oscillator
Bit 2 HSIRDYF: HSI ready interrupt flag
Set by hardware when the Internal High Speed clock becomes stable and HSIRDYIE is set.
It is cleared by software setting the HSIRDYC bit.
0: No clock ready interrupt caused by the internal 8 MHz RC oscillator
1: Clock ready interrupt caused by the internal 8 MHz RC oscillator
Bit 1 LSERDYF: LSE ready interrupt flag
Set by hardware when the External Low Speed clock becomes stable and LSERDYIE is set.
It is cleared by software setting the LSERDYC bit.
0: No clock ready interrupt caused by the external 32 kHz oscillator
1: Clock ready interrupt caused by the external 32 kHz oscillator
Bit 0 LSIRDYF: LSI ready interrupt flag
Set by hardware when Internal Low Speed clock becomes stable and LSIRDYIE is set. It is
cleared by software setting the LSIRDYC bit.
0: No clock ready interrupt caused by the internal RC 40 kHz oscillator
1: Clock ready interrupt caused by the internal RC 40 kHz oscillator
RM0008 Connectivity line devices: reset and clock control (RCC)
Doc ID 13902 Rev 13 137/1093

8.3.4 APB2 peripheral reset register (RCC_APB2RSTR)
Address offset: 0x0C
Reset value: 0x00000 0000
Access: no wait state, word, half-word and byte access


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res.
USART1
RST
Res.
SPI1
RST
TIM1
RST
ADC2
RST
ADC1
RST
Reserved
IOPE
RST
IOPD
RST
IOPC
RST
IOPB
RST
IOPA
RST
Res.
AFIO
RST
rw rw rw rw rw rw rw rw rw rw rw
Bits 31:15 Reserved, must be kept at reset value.
Bit 14 USART1RST: USART1 reset
Set and cleared by software.
0: No effect
1: Reset USART1
Bit 13 Reserved, must be kept at reset value.
Bit 12 SPI1RST: SPI 1 reset
Set and cleared by software.
0: No effect
1: Reset SPI 1
Bit 11 TIM1RST: TIM1 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM1 timer
Bit 10 ADC2RST: ADC 2 interface reset
Set and cleared by software.
0: No effect
1: Reset ADC 2 interface
Bit 9 ADC1RST: ADC 1 interface reset
Set and cleared by software.
0: No effect
1: Reset ADC 1 interface
Bits 8:7 Reserved, must be kept at reset value.
Bit 6 IOPERST: I/O port E reset
Set and cleared by software.
0: No effect
1: Reset I:O port E
Bit 5 IOPDRST: I/O port D reset
Set and cleared by software.
0: No effect
1: Reset I/O port D

Connectivity line devices: reset and clock control (RCC) RM0008
138/1093 Doc ID 13902 Rev 13
8.3.5 APB1 peripheral reset register (RCC_APB1RSTR)
Address offset: 0x10
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access


Bit 4 IOPCRST: IO port C reset
Set and cleared by software.
0: No effect
1: Reset I/O port C
Bit 3 IOPBRST: IO port B reset
Set and cleared by software.
0: No effect
1: Reset I/O port B
Bit 2 IOPARST: I/O port A reset
Set and cleared by software.
0: No effect
1: Reset I/O port A
Bit 1 Reserved, must be kept at reset value.
Bit 0 AFIORST: Alternate function I/O reset
Set and cleared by software.
0: No effect
1: Reset Alternate Function
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
DAC
RST
PWR
RST
BKP
RST
CAN2
RST
CAN1
RST
Reserved
I2C2
RST
I2C1
RST
UART
5
RST
UART
4
RST
USART
3
RST
USART
2
RST
Res.
rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI3
RST
SPI2
RST
Reserved
WWD
GRST
Reserved
TIM7
RST
TIM6
RST
TIM5
RST
TIM4
RST
TIM3
RST
TIM2
RST
rw rw rw rw rw rw rw rw rw
Bits 31:30 Reserved, must be kept at reset value.
Bit 29 DACRST: DAC interface reset
Set and cleared by software.
0: No effect
1: Reset DAC interface
Bit 28 PWRRST: Power interface reset
Set and cleared by software.
0: No effect
1: Reset power interface
RM0008 Connectivity line devices: reset and clock control (RCC)
Doc ID 13902 Rev 13 139/1093

Bit 27 BKPRST: Backup interface reset
Set and cleared by software.
0: No effect
1: Reset backup interface
Bit 26 CAN2RST: CAN2 reset
Set and cleared by software.
0: No effect
1: Reset CAN2
Bit 25 CAN1RST: CAN1 reset
Set and cleared by software.
0: No effect
1: Reset CAN1
Bits 24:23 Reserved, must be kept at reset value.
Bit 22 I2C2RST: I2C 2 reset
Set and cleared by software.
0: No effect
1: Reset I2C 2
Bit 21 I2C1RST: I2C1 reset
Set and cleared by software.
0: No effect
1: Reset I2C 1
Bit 20 UART5RST: USART 5 reset
Set and cleared by software.
0: No effect
1: Reset USART 5
Bit 19 UART4RST: USART 4 reset
Set and cleared by software.
0: No effect
1: Reset USART 4
Bit 18 USART3RST: USART 3 reset
Set and cleared by software.
0: No effect
1: Reset USART 3
Bit 17 USART2RST: USART 2 reset
Set and cleared by software.
0: No effect
1: Reset USART 2
Bits 16 Reserved, must be kept at reset value.
Bit 15 SPI3RST: SPI3 reset
Set and cleared by software.
0: No effect
1: Reset SPI 3
Bit 14 SPI2RST: SPI2 reset
Set and cleared by software.
0: No effect
1: Reset SPI2

Connectivity line devices: reset and clock control (RCC) RM0008
140/1093 Doc ID 13902 Rev 13
Bits 13:12 Reserved, must be kept at reset value.
Bit 11 WWDGRST: Window watchdog reset
Set and cleared by software.
0: No effect
1: Reset window watchdog
Bits 10:6 Reserved, must be kept at reset value.
Bit 5 TIM7RST: Timer 7 reset
Set and cleared by software.
0: No effect
1: Reset timer 7
Bit 4 TIM6RST: Timer 6 reset
Set and cleared by software.
0: No effect
1: Reset timer 6
Bit 3 TIM5RST: Timer 5 reset
Set and cleared by software.
0: No effect
1: Reset timer 5
Bit 2 TIM4RST: Timer 4 reset
Set and cleared by software.
0: No effect
1: Reset timer 4
Bit 1 TIM3RST: Timer 3 reset
Set and cleared by software.
0: No effect
1: Reset timer 3
Bit 0 TIM2RST: Timer 2 reset
Set and cleared by software.
0: No effect
1: Reset timer 2
RM0008 Connectivity line devices: reset and clock control (RCC)
Doc ID 13902 Rev 13 141/1093

8.3.6 AHB Peripheral Clock enable register (RCC_AHBENR)
Address offset: 0x14
Reset value: 0x0000 0014
Access: no wait state, word, half-word and byte access


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
ETH
MACR
XEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETHM
ACTX
EN
ETHM
ACEN
Res.
OTGF
SEN
Reserved
CRCEN
Res.
FLITFE
N
Res.
SRAM
EN
DMA2
EN
DMA1
EN
rw rw rw rw rw rw rw rw
Bits 31:17 Reserved, must be kept at reset value.
Bit 16 ETHMACRXEN: Ethernet MAC RX clock enable
Set and cleared by software.
0: Ethernet MAC RX clock disabled
1: Ethernet MAC RX clock enabled
Note: In the RMII mode, if this clock is enabled, the RMII clock of the MAC is also enabled.
Bit 15 ETHMACTXEN: Ethernet MAC TX clock enable
Set and cleared by software.
0: Ethernet MAC TX clock disabled
1: Ethernet MAC TX clock enabled
Note: In the RMII mode, if this clock is enabled, the RMII clock of the MAC is also enabled.
Bit 14 ETHMACEN: Ethernet MAC clock enable
Set and cleared by software. Selection of PHY interface (MII/RMII) must be done before
enabling the MAC clock.
0: Ethernet MAC clock disabled
1: Ethernet MAC clock enabled
Bit 13 Reserved, must be kept at reset value.
Bit 12 OTGFSEN: USB OTG FS clock enable
Set and cleared by software.
0: USB OTG FS clock disabled
1: USB OTG FS clock enabled
Bits 11:7 Reserved, must be kept at reset value.
Bit 6 CRCEN: CRC clock enable
Set and cleared by software.
0: CRC clock disabled
1: CRC clock enabled
Bit 5 Reserved, must be kept at reset value.

Connectivity line devices: reset and clock control (RCC) RM0008
142/1093 Doc ID 13902 Rev 13
8.3.7 APB2 peripheral clock enable register (RCC_APB2ENR)
Address: 0x18
Reset value: 0x0000 0000
Access: word, half-word and byte access
No wait states, except if the access occurs while an access to a peripheral in the APB2
domain is on going. In this case, wait states are inserted until the access to APB2 peripheral
is finished.


Bit 4 FLITFEN: FLITF clock enable
Set and cleared by software to disable/enable FLITF clock during sleep mode.
0: FLITF clock disabled during Sleep mode
1: FLITF clock enabled during Sleep mode
Bit 3 Reserved, must be kept at reset value.
Bit 2 SRAMEN: SRAM interface clock enable
Set and cleared by software to disable/enable SRAM interface clock during Sleep mode.
0: SRAM interface clock disabled during Sleep mode
1: SRAM interface clock enabled during Sleep mode
Bit 1 DMA2EN: DMA2 clock enable
Set and cleared by software.
0: DMA2 clock disabled
1: DMA2 clock enabled
Bit 0 DMA1EN: DMA1 clock enable
Set and cleared by software.
0: DMA1 clock disabled
1: DMA1 clock enabled
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res.
USAR
T1EN
Res.
SPI1
EN
TIM1
EN
ADC2
EN
ADC1
EN
Reserved
IOPE
EN
IOPD
EN
IOPC
EN
IOPB
EN
IOPA
EN
Res.
AFIO
EN
rw rw rw rw rw rw rw rw rw rw rw
Bits 31:15 Reserved, must be kept at reset value.
Bit 14 USART1EN: USART1 clock enable
Set and cleared by software.
0: USART1 clock disabled
1: USART1 clock enabled
Bit 13 Reserved, must be kept at reset value.
Bit 12 SPI1EN: SPI 1 clock enable
Set and cleared by software.
0: SPI 1 clock disabled
1: SPI 1 clock enabled
RM0008 Connectivity line devices: reset and clock control (RCC)
Doc ID 13902 Rev 13 143/1093

Bit 11 TIM1EN: TIM1 Timer clock enable
Set and cleared by software.
0: TIM1 timer clock disabled
1: TIM1 timer clock enabled
Bit 10 ADC2EN: ADC 2 interface clock enable
Set and cleared by software.
0: ADC 2 interface clock disabled
1: ADC 2 interface clock enabled
Bit 9 ADC1EN: ADC 1 interface clock enable
Set and cleared by software.
0: ADC 1 interface disabled
1: ADC 1 interface clock enabled
Bits 8:7 Reserved, must be kept at reset value.
Bit 6 IOPEEN: I/O port E clock enable
Set and cleared by software.
0: I/O port E clock disabled
1: I/O port E clock enabled
Bit 5 IOPDEN: I/O port D clock enable
Set and cleared by software.
0: I/O port D clock disabled
1: I/O port D clock enabled
Bit 4 IOPCEN: I/O port C clock enable
Set and cleared by software.
0: I/O port C clock disabled
1:I/O port C clock enabled
Bit 3 IOPBEN: I/O port B clock enable
Set and cleared by software.
0: I/O port B clock disabled
1:I/O port B clock enabled
Bit 2 IOPAEN: I/O port A clock enable
Set and cleared by software.
0: I/O port A clock disabled
1:I/O port A clock enabled
Bit 1 Reserved, must be kept at reset value.
Bit 0 AFIOEN: Alternate function I/O clock enable
Set and cleared by software.
0: Alternate Function I/O clock disabled
1:Alternate Function I/O clock enabled

Connectivity line devices: reset and clock control (RCC) RM0008
144/1093 Doc ID 13902 Rev 13
8.3.8 APB1 peripheral clock enable register (RCC_APB1ENR)
Address: 0x1C
Reset value: 0x0000 0000
Access: word, half-word and byte access
No wait state, except if the access occurs while an access to a peripheral on APB1 domain
is on going. In this case, wait states are inserted until this access to APB1 peripheral is
finished.


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
DAC
EN
PWR
EN
BKP
EN
CAN2
EN
CAN1
EN
Reserved
I2C2
EN
I2C1
EN
UART5E
N
UART4
EN
USART
3EN
USART
2EN
Res.
rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI3
EN
SPI2
EN
Reserved
WWD
GEN
Reserved
TIM7
EN
TIM6
EN
TIM5
EN
TIM4
EN
TIM3
EN
TIM2
EN
rw rw rw rw rw rw rw rw rw
Bits 31:30 Reserved, must be kept at reset value.
Bit 29 DACEN: DAC interface clock enable
Set and cleared by software.
0: DAC interface clock disabled
1: DAC interface clock enable
Bit 28 PWREN: Power interface clock enable
Set and cleared by software.
0: Power interface clock disabled
1: Power interface clock enable
Bit 27 BKPEN: Backup interface clock enable
Set and cleared by software.
0: Backup interface clock disabled
1: Backup interface clock enabled
Bit 26 CAN2EN: CAN2 clock enable
Set and cleared by software.
0: CAN2 clock disabled
1: CAN2 clock enabled
Bit 25 CAN1EN: CAN1 clock enable
Set and cleared by software.
0: CAN1 clock disabled
1: CAN1 clock enabled
Bits 24:23 Reserved, must be kept at reset value.
Bit 22 I2C2EN: I2C 2 clock enable
Set and cleared by software.
0: I2C 2 clock disabled
1: I2C 2 clock enabled
RM0008 Connectivity line devices: reset and clock control (RCC)
Doc ID 13902 Rev 13 145/1093

Bit 21 I2C1EN: I2C 1 clock enable
Set and cleared by software.
0: I2C 1 clock disabled
1: I2C 1 clock enabled
Bit 20 UART5EN: USART 5 clock enable
Set and cleared by software.
0: USART 5 clock disabled
1: USART 5 clock enabled
Bit 19 UART4EN: USART 4 clock enable
Set and cleared by software.
0: USART 4 clock disabled
1: USART 4 clock enabled
Bit 18 USART3EN: USART 3 clock enable
Set and cleared by software.
0: USART 3 clock disabled
1: USART 3 clock enabled
Bit 17 USART2EN: USART 2 clock enable
Set and cleared by software.
0: USART 2 clock disabled
1: USART 2 clock enabled
Bits 16 Reserved, must be kept at reset value.
Bit 15 SPI3EN: SPI 3 clock enable
Set and cleared by software.
0: SPI 3 clock disabled
1: SPI 3 clock enabled
Bit 14 SPI2EN: SPI 2 clock enable
Set and cleared by software.
0: SPI 2 clock disabled
1: SPI 2 clock enabled
Bits 13:12 Reserved, must be kept at reset value.
Bit 11 WWDGEN: Window watchdog clock enable
Set and cleared by software.
0: Window watchdog clock disabled
1: Window watchdog clock enabled
Bits 10:6 Reserved, must be kept at reset value.
Bit 5 TIM7EN: Timer 7 clock enable
Set and cleared by software.
0: Timer 7 clock disabled
1: Timer 7 clock enabled
Bit 4 TIM6EN: Timer 6 clock enable
Set and cleared by software.
0: Timer 6 clock disabled
1: Timer 6 clock enabled

Connectivity line devices: reset and clock control (RCC) RM0008
146/1093 Doc ID 13902 Rev 13
8.3.9 Backup domain control register (RCC_BDCR)
Address: 0x20
Reset value: 0x0000 0000, reset by Backup domain Reset.
Access: 0 wait state 3, word, half-word and byte access
Wait states are inserted in the case of successive accesses to this register.
Note: LSEON, LSEBYP, RTCSEL and RTCEN bits of the Backup domain control register
(RCC_BDCR) are in the Backup domain. As a result, after Reset, these bits are write-
protected and the DBP bit in the Power control register (PWR_CR) has to be set before
these can be modified. Refer to Section 6 on page 79 for further information. These bits are
only reset after a Backup domain Reset (see Section 8.1.3: Backup domain reset). Any
internal or external Reset will not have any effect on these bits.


Bit 3 TIM5EN: Timer 5 clock enable
Set and cleared by software.
0: Timer 5 clock disabled
1: Timer 5 clock enabled
Bit 2 TIM4EN: Timer 4 clock enable
Set and cleared by software.
0: Timer 4 clock disabled
1: Timer 4 clock enabled
Bit 1 TIM3EN: Timer 3 clock enable
Set and cleared by software.
0: Timer 3 clock disabled
1: Timer 3 clock enabled
Bit 0 TIM2EN: Timer 2 clock enable
Set and cleared by software.
0: Timer 2 clock disabled
1: Timer 2 clock enabled
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
BDRST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTC
EN
Reserved
RTCSEL[1:0]
Reserved
LSE
BYP
LSE
RDY
LSEON
rw rw rw rw r rw
Bits 31:17 Reserved, must be kept at reset value.
Bit 16 BDRST: Backup domain software reset
Set and cleared by software.
0: Reset not activated
1: Resets the entire Backup domain
RM0008 Connectivity line devices: reset and clock control (RCC)
Doc ID 13902 Rev 13 147/1093

Bit 15 RTCEN: RTC clock enable
Set and cleared by software.
0: RTC clock disabled
1: RTC clock enabled
Bits 14:10 Reserved, must be kept at reset value.
Bits 9:8 RTCSEL[1:0]: RTC clock source selection
Set by software to select the clock source for the RTC. Once the RTC clock source has been
selected, it cannot be changed anymore unless the Backup domain is reset. The BDRST bit
can be used to reset the RTCSEL[1:0] bits.
00: No clock
01: LSE oscillator clock used as RTC clock
10: LSI oscillator clock used as RTC clock
11: HSE oscillator clock divided by 128 used as RTC clock
Bits 7:3 Reserved, must be kept at reset value.
Bit 2 LSEBYP: External Low Speed oscillator bypass
Set and cleared by software to bypass oscillator in debug mode. This bit can be written only
when the external 32 kHz oscillator is disabled.
0: LSE oscillator not bypassed
1: LSE oscillator bypassed
Bit 1 LSERDY: External Low Speed oscillator ready
Set and cleared by hardware to indicate when the external 32 kHz oscillator is stable. After
the LSEON bit is cleared, LSERDY goes low after 6 external low speed oscillator clock
cycles
0: External 32 kHz oscillator not ready
1: External 32 kHz oscillator ready
Bit 0 LSEON: External Low Speed oscillator enable
Set and cleared by software.
0: External 32 kHz oscillator OFF
1: External 32 kHz oscillator ON

Connectivity line devices: reset and clock control (RCC) RM0008
148/1093 Doc ID 13902 Rev 13
8.3.10 Control/status register (RCC_CSR)
Address: 0x24
Reset value: 0x0C00 0000, reset by system Reset, except reset flags by power Reset only.
Access: 0 wait state 3, word, half-word and byte access
Wait states are inserted in the case of successive accesses to this register.


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPWR
RSTF
WWDG
RSTF
IWDG
RSTF
SFT
RSTF
POR
RSTF
PIN
RSTF
Res.
RMVF
Reserved
rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
LSI
RDY
LSION
r rw
Bit 31 LPWRRSTF: Low-power reset flag
Set by hardware when a Low-power management reset occurs. It is cleared by writing to the
RMVF bit.
0: No Low-power management reset occurred
1: Low-power management reset occurred
For further information on Low-power management reset, refer to Section : Low-power
management reset.
Bit 30 WWDGRSTF: Window watchdog reset flag
Set by hardware when a window watchdog reset occurs. It is cleared by writing to the RMVF
bit.
0: No window watchdog reset occurred
1: Window watchdog reset occurred
Bit 29 IWDGRSTF: Independent watchdog reset flag
Set by hardware when an independent watchdog reset from V
DD
domain occurs. It is cleared
by writing to the RMVF bit.
0: No watchdog reset occurred
1: Watchdog reset occurred
Bit 28 SFTRSTF: Software reset flag
Set by hardware when a software reset occurs. It is cleared by writing to the RMVF bit.
0: No software reset occurred
1: Software reset occurred
Bit 27 PORRSTF: POR/PDR reset flag
Set by hardware when a POR/PDR reset occurs. It is cleared by writing to the RMVF bit.
0: No POR/PDR reset occurred
1: POR/PDR reset occurred
Bit 26 PINRSTF: PIN reset flag
Set by hardware when a reset from the NRST pin occurs. It is cleared by writing to the
RMVF bit.
0: No reset from NRST pin occurred
1: Reset from NRST pin occurred
Bit 25 Reserved, must be kept at reset value.
RM0008 Connectivity line devices: reset and clock control (RCC)
Doc ID 13902 Rev 13 149/1093

8.3.11 AHB peripheral clock reset register (RCC_AHBRSTR)
Address offset: 0x28
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access


Bit 24 RMVF: Remove reset flag
Set by software to clear the reset flags.
0: No effect
1: Clear the reset flags
Bits 23:2 Reserved, must be kept at reset value.
Bit 1 LSIRDY: Internal low speed oscillator ready
Set and cleared by hardware to indicate when the internal RC 40 kHz oscillator is stable.
After the LSION bit is cleared, LSIRDY goes low after 3 internal 40 kHz RC oscillator clock
cycles.
0: Internal RC 40 kHz oscillator not ready
1: Internal RC 40 kHz oscillator ready
Bit 0 LSION: Internal low speed oscillator enable
Set and cleared by software.
0: Internal RC 40 kHz oscillator OFF
1: Internal RC 40 kHz oscillator ON
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res.
ETHMAC
RST
Res.
OTGFS
RST
Reserved
rw rw
Bits 31:15 Reserved, must be kept at reset value.
Bit 14 ETHMACRST Ethernet MAC reset
Set and cleared by software.
0: No effect
1: Reset ETHERNET MAC
Bit 13 Reserved, must be kept at reset value.
Bit 12 OTGFSRST USB OTG FS reset
Set and cleared by software.
0: No effect
1: Reset USB OTG FS
Bits 11:0 Reserved, must be kept at reset value.

Connectivity line devices: reset and clock control (RCC) RM0008
150/1093 Doc ID 13902 Rev 13
8.3.12 Clock configuration register2 (RCC_CFGR2)
Address offset: 0x2C
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access

7
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
I2S3S
RC
I2S2S
RC
PREDI
V1SRC
rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLL3MUL[3:0] PLL2MUL[3:0] PREDIV2[3:0] PREDIV1[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:19 Reserved, must be kept at reset value.
Bit 18 I2S3SRC: I2S3 clock source
Set and cleared by software to select I2S3 clock source. This bit must be valid before
enabling I2S3 clock.
0: System clock (SYSCLK) selected as I2S3 clock entry
1: PLL3 VCO clock selected as I2S3 clock entry
Bit 17 I2S2SRC: I2S2 clock source
Set and cleared by software to select I2S2 clock source. This bit must be valid before
enabling I2S2 clock.
0: System clock (SYSCLK) selected as I2S2 clock entry
1: PLL3 VCO clock selected as I2S2 clock entry
Bit 16 PREDIV1SRC: PREDIV1 entry clock source
Set and cleared by software to select PREDIV1 clock source. This bit can be written only
when PLL is disabled.
0: HSE oscillator clock selected as PREDIV1 clock entry
1: PLL2 selected as PREDIV1 clock entry
Bits 15:12 PLL3MUL[3:0]: PLL3 Multiplication Factor
Set and cleared by software to control PLL3 multiplication factor. These bits can be written
only when PLL3 is disabled.
00xx: Reserved
010x: Reserved
0110: PLL3 clock entry x 8
0111: PLL3 clock entry x 9
1000: PLL3 clock entry x 10
1001: PLL3 clock entry x 11
1010: PLL3 clock entry x 12
1011: PLL3 clock entry x 13
1100: PLL3 clock entry x 14
1101: Reserved
1110: PLL3 clock entry x 16
1111: PLL3 clock entry x 20
RM0008 Connectivity line devices: reset and clock control (RCC)
Doc ID 13902 Rev 13 151/1093

Bits 11:8 PLL2MUL[3:0]: PLL2 Multiplication Factor
Set and cleared by software to control PLL2 multiplication factor. These bits can be written
only when PLL2 is disabled.
00xx: Reserved
010x: Reserved
0110: PLL2 clock entry x 8
0111: PLL2 clock entry x 9
1000: PLL2 clock entry x 10
1001: PLL2 clock entry x 11
1010: PLL2 clock entry x 12
1011: PLL2 clock entry x 13
1100: PLL2 clock entry x 14
1101: Reserved
1110: PLL2 clock entry x 16
1111: PLL2 clock entry x 20
Bits 7:4 PREDIV2[3:0]: PREDIV2 division factor
Set and cleared by software to select PREDIV2 division factor. These bits can be written only
when both PLL2 and PLL3 are disabled.
0000: PREDIV2 input clock not divided
0001: PREDIV2 input clock divided by 2
0010: PREDIV2 input clock divided by 3
0011: PREDIV2 input clock divided by 4
0100: PREDIV2 input clock divided by 5
0101: PREDIV2 input clock divided by 6
0110: PREDIV2 input clock divided by 7
0111: PREDIV2 input clock divided by 8
1000: PREDIV2 input clock divided by 9
1001: PREDIV2 input clock divided by 10
1010: PREDIV2 input clock divided by 11
1011: PREDIV2 input clock divided by 12
1100: PREDIV2 input clock divided by 13
1101: PREDIV2 input clock divided by 14
1110: PREDIV2 input clock divided by 15
1111: PREDIV2 input clock divided by 16

Connectivity line devices: reset and clock control (RCC) RM0008
152/1093 Doc ID 13902 Rev 13
8.3.13 RCC register map
The following table gives the RCC register map and the reset values.

Bits 3:0 PREDIV1[3:0]: PREDIV1 division factor
Set and cleared by software to select PREDIV1 division factor. These bits can be written only
when PLL is disabled.
Note: Bit(0) is the same as bit(17) in the RCC_CFGR register, so modifying bit(17) in the
RCC_CFGR register changes Bit(0) accordingly.
0000: PREDIV1 input clock not divided
0001: PREDIV1 input clock divided by 2
0010: PREDIV1 input clock divided by 3
0011: PREDIV1 input clock divided by 4
0100: PREDIV1 input clock divided by 5
0101: PREDIV1 input clock divided by 6
0110: PREDIV1 input clock divided by 7
0111: PREDIV1 input clock divided by 8
1000: PREDIV1 input clock divided by 9
1001: PREDIV1 input clock divided by 10
1010: PREDIV1 input clock divided by 11
1011: PREDIV1 input clock divided by 12
1100: PREDIV1 input clock divided by 13
1101: PREDIV1 input clock divided by 14
1110: PREDIV1 input clock divided by 15
1111: PREDIV1 input clock divided by 16
Table 19. RCC register map and reset values
Offset Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9 8 7 6 5 4 3 2 1 0
0x000
RCC_CR Reser
ved
P
L
L
3

R
D
Y
P
L
L
3

O
N
P
L
L
2

R
D
Y
P
L
L
2

O
N
P
L
L

R
D
Y
P
L
L
O
N
Reserved
C
S
S
O
N
H
S
E
B
Y
P
H
S
E
R
D
Y
H
S
E
O
N
HSICAL[7:0] HSITRIM[4:0]
R
e
s
e
r
v
e
d
H
S
I
R
D
Y
H
S
I
O
N
Reset value 0 0 0 0 0 0 0 0 0 0 x x x x x x x x 1 0 0 0 0 1 1
0x004
RCC_CFGR
Reserved
MCO [3:0]
R
e
s
e
r
v
e
d
O
T
G
F
S
P
R
E
PLLMUL [3:0]
P
L
L
X
T
P
R
E
P
L
L
S
R
C
ADC
PRE
[1:0]
PPRE2
[2:0]
PPRE1
[2:0]
HPRE[3:0]
SWS
[1:0]
SW
[1:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x008
RCC_CIR
Reserved
C
S
S
C
P
L
L
3
R
D
Y
C
P
L
L
2
R
D
Y
C
P
L
L
R
D
Y
C
H
S
E
R
D
Y
C
H
S
I
R
D
Y
C
L
S
E
R
D
Y
C
L
S
I
R
D
Y
C
R
e
s
e
r
v
e
d
P
L
L
3
R
D
Y
I
E
P
L
L
2
R
D
Y
I
E
P
L
L
R
D
Y
I
E
H
S
E
R
D
Y
I
E
H
S
I
R
D
Y
I
E
L
S
E
R
D
Y
I
E
L
S
I
R
D
Y
I
E
C
S
S
F
P
L
L
3
R
D
Y
F
P
L
L
2
R
D
Y
F
P
L
L
R
D
Y
F
H
S
E
R
D
Y
F
H
S
I
R
D
Y
F
L
S
E
R
D
Y
F
L
S
I
R
D
Y
F
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x00C
RCC_APB2RSTR
Reserved
R
e
s
e
r
v
e
d
U
S
A
R
T
1
R
S
T
R
e
s
e
r
v
e
d
S
P
I
1
R
S
T
T
I
M
1
R
S
T
A
D
C
2
R
S
T
A
D
C
1
R
S
T
R
e
s
e
r
v
e
d
I
O
P
E
R
S
T
I
O
P
D
R
S
T
I
O
P
C
R
S
T
I
O
P
B
R
S
T
I
O
P
A
R
S
T
R
e
s
e
r
v
e
d
A
F
I
O
R
S
T
Reset value 0 0 0 0 0 0 0 0 0 0 0
0x010
RCC_APB1RSTR Reser
ved
D
A
C
R
S
T
P
W
R
R
S
T
B
K
P
R
S
T
C
A
N
2
R
S
T
C
A
N
1
R
S
T
R
e
s
e
r
v
e
d
I
2
C
2
R
S
T
I
2
C
1
R
S
T
U
A
R
T
5
R
S
T
U
A
R
T
4
R
S
T
U
S
A
R
T
3
R
S
T
U
S
A
R
T
2
R
S
T
R
e
s
e
r
v
e
d
S
P
I
3
R
S
T
S
P
I
2
R
S
T
R
e
s
e
r
v
e
d
W
W
D
G
R
S
T
Reserved
T
M
7
R
S
T
T
M
6
R
S
T
T
M
5
R
S
T
T
I
M
4
R
S
T
T
I
M
3
R
S
T
T
I
M
2
R
S
T
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RM0008 Connectivity line devices: reset and clock control (RCC)
Doc ID 13902 Rev 13 153/1093

Refer to Table 3 on page 50 for the register boundary addresses.
0x014
RCC_AHBENR
Reserved
E
T
H
M
A
C
R
X
E
N
E
T
H
M
A
C
T
X
E
N
E
T
H
M
A
C
E
N
R
e
s
e
r
v
e
d
O
T
G
F
S
E
N
Reserved
C
R
C
E
N
R
e
s
e
r
v
e
d
F
L
I
T
F
E
N
R
e
s
e
r
v
e
d
S
R
A
M
E
N
D
M
2
A
E
N
D
M
1
A
E
N
Reset value 0 0 0 0 0 1 1 0 0
0x018 RCC_APB2ENR
Reserved
R
e
s
e
r
v
e
d
U
S
A
R
T
1
E
N
R
e
s
e
r
v
e
d
S
P
I
1
E
N
T
I
M
1
E
N
A
D
C
2
E
N
A
D
C
1
E
N
R
e
s
e
r
v
e
d
I
O
P
E
E
N
I
O
P
D
E
N
I
O
P
C
E
N
I
O
P
B
E
N
I
O
P
A
E
N
R
e
s
e
r
v
e
d
A
F
I
O
E
N
Reset value 0 0 0 0 0 0 0 0 0 0 0
0x01C
RCC_APB1ENR Reser
ved
D
A
C
E
N
P
W
R
E
N
B
K
P
E
N
C
A
N
2
E
N
C
A
N
1
E
N
R
e
s
e
r
v
e
d
I
2
C
2
E
N
I
2
C
1
E
N
U
A
R
T
5
E
N
U
A
R
T
4
E
N
U
S
A
R
T
3
E
N
U
S
A
R
T
2
E
N
R
e
s
e
r
v
e
d
S
P
I
3
E
N
S
P
I
2
E
N
R
e
s
e
r
v
e
d
W
W
D
G
E
N
Reserved
T
I
M
7
E
N
T
I
M
6
E
N
T
I
M
5
E
N
T
I
M
4
E
N
T
I
M
3
E
N
T
I
M
2
E
N
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x020
RCC_BDCR
Reserved
B
D
R
S
T
R
T
C
E
N
Reserved
RTC
SEL
[1:0]
Reserved
L
S
E
B
Y
P
L
S
E
R
D
Y
L
S
E
O
N
Reset value 0 0 0 0 0 0 0
0x024
RCC_CSR
L
P
W
R
S
T
F
W
W
D
G
R
S
T
F
I
W
D
G
R
S
T
F
S
F
T
R
S
T
F
P
O
R
R
S
T
F
P
I
N
R
S
T
F
R
e
s
e
r
v
e
d
R
M
V
F
Reserved
L
S
I
R
D
Y
L
S
I
O
N
Reset value 0 0 0 0 1 1 0 0 0
0x028
RCC_AHBSTR
Reserved
E
T
H
M
A
C
R
S
T
R
e
s
e
r
v
e
d
O
T
G
F
S
R
S
T
Reserved
Reset value 0 0
0x02C
RCC_CFGR2
Reserved
I
2
S
3
S
R
C
I
2
S
2
S
R
C
P
R
E
D
I
V
1
S
R
C
PLL3MUL
[3:0]
PLL2MUL
[3:0]
PREDIV2[3:0] PREDIV1[3:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 19. RCC register map and reset values (continued)
Offset Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9 8 7 6 5 4 3 2 1 0

General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008
154/1093 Doc ID 13902 Rev 13
9 General-purpose and alternate-function I/Os (GPIOs
and AFIOs)
Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx
microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx
microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
High-density devices are STM32F101xx and STM32F103xx microcontrollers where the
Flash memory density ranges between 256 and 512 Kbytes.
XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the
Flash memory density ranges between 768 Kbytes and 1 Mbyte.
Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
This section applies to the whole STM32F10xxx family, unless otherwise specified.
9.1 GPIO functional description
Each of the general-purpose I/O ports has two 32-bit configuration registers (GPIOx_CRL,
GPIOx_CRH), two 32-bit data registers (GPIOx_IDR, GPIOx_ODR), a 32-bit set/reset
register (GPIOx_BSRR), a 16-bit reset register (GPIOx_BRR) and a 32-bit locking register
(GPIOx_LCKR).
Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each
port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software
in several modes:
Input floating
Input pull-up
Input-pull-down
Analog
Output open-drain
Output push-pull
Alternate function push-pull
Alternate function open-drain
Each I/O port bit is freely programmable, however the I/O port registers have to be accessed
as 32-bit words (half-word or byte accesses are not allowed). The purpose of the
GPIOx_BSRR and GPIOx_BRR registers is to allow atomic read/modify accesses to any of
the GPIO registers. This way, there is no risk that an IRQ occurs between the read and the
modify access.
Figure 13 shows the basic structure of an I/O Port bit.
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs)
Doc ID 13902 Rev 13 155/1093

Figure 13. Basic structure of a standard I/O port bit
Figure 14. Basic structure of a five-volt tolerant I/O port bit
1. V
DD_FT
is a potential specific to five-volt tolerant I/Os and different from V
DD
.
Alternate Function Output
Alternate Function Input
Push-pull,
open-drain or
disabled
I
n
p
u
t

d
a
t
a

r
e
g
i
s
t
e
r
O
u
t
p
u
t

d
a
t
a

r
e
g
i
s
t
e
r
Read/write
From on-chip
peripheral
To on-chip
peripheral
Output
control
Analog Input
on/off
on/off
I/O pin
V
DD
V
DD
V
SS
V
SS
TTL Schmitt
trigger
V
SS
V
DD
Protection
diode
Protection
diode
on/off
Input driver
Output driver
P-MOS
N-MOS
Read
B
i
t

s
e
t
/
r
e
s
e
t

r
e
g
i
s
t
e
r
s
Write
ai14781
Alternate Function Output
Alternate Function Input
Push-pull,
open-drain or
disabled
I
n
p
u
t

d
a
t
a

r
e
g
i
s
t
e
r
O
u
t
p
u
t

d
a
t
a

r
e
g
i
s
t
e
r
Read/write
From on-chip
peripheral
To on-chip
peripheral
Output
control
Analog Input
on/off
on/off
I/O pin
V
DD
V
DD
V
SS
V
SS
TTL Schmitt
trigger
V
SS
V
DD_FT
(1)
Protection
diode
on/off
Input driver
Output driver
P-MOS
N-MOS
Read
B
i
t

s
e
t
/
r
e
s
e
t

r
e
g
i
s
t
e
r
s
Write
ai14782

General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008
156/1093 Doc ID 13902 Rev 13


9.1.1 General-purpose I/O (GPIO)
During and just after reset, the alternate functions are not active and the I/O ports are
configured in Input Floating mode (CNFx[1:0]=01b, MODEx[1:0]=00b).
The JTAG pins are in input PU/PD after reset:
PA15: JTDI in PU
PA14: JTCK in PD
PA13: JTMS in PU
PB4: NJTRST in PU
When configured as output, the value written to the Output Data register (GPIOx_ODR) is
output on the I/O pin. It is possible to use the output driver in Push-Pull mode or Open-Drain
mode (only the N-MOS is activated when outputting 0).
The Input Data register (GPIOx_IDR) captures the data present on the I/O pin at every
APB2 clock cycle.
All GPIO pins have an internal weak pull-up and weak pull-down which can be activated or
not when configured as input.
9.1.2 Atomic bit set or reset
There is no need for the software to disable interrupts when programming the GPIOx_ODR
at bit level: it is possible to modify only one or several bits in a single atomic APB2 write
access. This is achieved by programming to 1 the Bit Set/Reset Register (GPIOx_BSRR,
Table 20. Port bit configuration table
Configuration mode CNF1 CNF0 MODE1 MODE0
PxODR
register
General purpose
output
Push-pull
0
0
01
10
11
see Table 21
0 or 1
Open-drain 1 0 or 1
Alternate Function
output
Push-pull
1
0 dont care
Open-drain 1 dont care
Input
Analog
0
0
00
dont care
Input floating 1 dont care
Input pull-down
1 0
0
Input pull-up 1
Table 21. Output MODE bits
MODE[1:0] Meaning
00 Reserved
01 Max. output speed 10 MHz
10 Max. output speed 2 MHz
11 Max. output speed 50 MHz
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs)
Doc ID 13902 Rev 13 157/1093

or for reset only GPIOx_BRR) to select the bits you want to modify. The unselected bits will
not be modified.
9.1.3 External interrupt/wakeup lines
All ports have external interrupt capability. To use external interrupt lines, the port must be
configured in input mode. For more information on external interrupts, refer to:
Section 10.2: External interrupt/event controller (EXTI) on page 198 and
Section 10.2.3: Wakeup event management on page 199
9.1.4 Alternate functions (AF)
It is necessary to program the Port Bit Configuration Register before using a default
alternate function.
For alternate function inputs, the port must be configured in Input mode (floating, pull-
up or pull-down) and the input pin must be driven externally.
Note: It is also possible to emulate the AFI input pin by software by programming the GPIO
controller. In this case, the port should be configured in Alternate Function Output mode.
And obviously, the corresponding port should not be driven externally as it will be driven by
the software using the GPIO controller.
For alternate function outputs, the port must be configured in Alternate Function Output
mode (Push-Pull or Open-Drain).
For bidirectional Alternate Functions, the port bit must be configured in Alternate
Function Output mode (Push-Pull or Open-Drain). In this case the input driver is
configured in input floating mode
If you configure a port bit as Alternate Function Output, this disconnects the output register
and connects the pin to the output signal of an on-chip peripheral.
If software configures a GPIO pin as Alternate Function Output, but peripheral is not
activated, its output is not specified.
9.1.5 Software remapping of I/O alternate functions
To optimize the number of peripheral I/O functions for different device packages, it is
possible to remap some alternate functions to some other pins. This is achieved by
software, by programming the corresponding registers (refer to AFIO registers on page 177.
In that case, the alternate functions are no longer mapped to their original assignations.
9.1.6 GPIO locking mechanism
The locking mechanism allows the IO configuration to be frozen. When the LOCK sequence
has been applied on a port bit, it is no longer possible to modify the value of the port bit until
the next reset.

General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008
158/1093 Doc ID 13902 Rev 13
9.1.7 Input configuration
When the I/O Port is programmed as Input:
The Output Buffer is disabled
The Schmitt Trigger Input is activated
The weak pull-up and pull-down resistors are activated or not depending on input
configuration (pull-up, pull-down or floating):
The data present on the I/O pin is sampled into the Input Data Register every APB2
clock cycle
A read access to the Input Data Register obtains the I/O State.
The Figure 15 on page 158 shows the Input Configuration of the I/O Port bit.
Figure 15. Input floating/pull up/pull down configurations
1. V
DD_FT
is a potential specific to five-volt tolerant I/Os and different from V
DD
.
9.1.8 Output configuration
When the I/O Port is programmed as Output:
The Output Buffer is enabled:
Open Drain Mode: A 0 in the Output register activates the N-MOS while a 1 in
the Output register leaves the port in Hi-Z. (the P-MOS is never activated)
Push-Pull Mode: A 0 in the Output register activates the N-MOS while a 1 in the
Output register activates the P-MOS.
The Schmitt Trigger Input is activated.
The weak pull-up and pull-down resistors are disabled.
The data present on the I/O pin is sampled into the Input Data Register every APB2
clock cycle
A read access to the Input Data Register gets the I/O state in open drain mode
A read access to the Output Data register gets the last written value in Push-Pull mode
I/O pin
TTL Schmitt
trigger
V
SS
V
DD
or V
DD_FT
(1)
protection
diode
protection
diode
on
input driver
output driver
I
n
p
u
t

d
a
t
a

r
e
g
i
s
t
e
r
O
u
t
p
u
t

d
a
t
a

r
e
g
i
s
t
e
r
Read/write
Read
B
i
t

s
e
t
/
r
e
s
e
t

r
e
g
i
s
t
e
r
s
Write
on/off
on/off
V
DD
V
SS
ai14783
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs)
Doc ID 13902 Rev 13 159/1093

The Figure 16 on page 159 shows the Output configuration of the I/O Port bit.
Figure 16. Output configuration
1. V
DD_FT
is a potential specific to five-volt tolerant I/Os and different from V
DD
.
9.1.9 Alternate function configuration
When the I/O Port is programmed as Alternate Function:
The Output Buffer is turned on in Open Drain or Push-Pull configuration
The Output Buffer is driven by the signal coming from the peripheral (alternate function
out)
The Schmitt Trigger Input is activated
The weak pull-up and pull-down resistors are disabled.
The data present on the I/O pin is sampled into the Input Data Register every APB2
clock cycle
A read access to the Input Data Register gets the I/O state in open drain mode
A read access to the Output Data register gets the last written value in Push-Pull mode
The Figure 17 on page 160 shows the Alternate Function Configuration of the I/O Port bit.
Also, refer to Section 9.4: AFIO registers on page 177 for further information.
A set of Alternate Function I/O registers allow you to remap some alternate functions to
different pins. Refer to
Push-pull or
Open-drain
Output
control
I/O pin
V
DD
V
SS
TTL Schmitt
trigger
V
SS
V
DD
or V
DD_FT
(1)
Protection
diode
Protection
diode
on
Input driver
Output driver
P-MOS
N-MOS
I
n
p
u
t

d
a
t
a

r
e
g
i
s
t
e
r
O
u
t
p
u
t

d
a
t
a

r
e
g
i
s
t
e
r
Read/write
Read
B
i
t

s
e
t
/
r
e
s
e
t

r
e
g
i
s
t
e
r
s
Write
ai14784

General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008
160/1093 Doc ID 13902 Rev 13
Figure 17. Alternate function configuration
1. V
DD_FT
is a potential specific to five-volt tolerant I/Os and different from V
DD
.
9.1.10 Analog configuration
When the I/O Port is programmed as Analog configuration:
The Output Buffer is disabled.
The Schmitt Trigger Input is de-activated providing zero consumption for every analog
value of the I/O pin. The output of the Schmitt Trigger is forced to a constant value (0).
The weak pull-up and pull-down resistors are disabled.
Read access to the Input Data Register gets the value 0.
The Figure 18 on page 161 shows the high impedance-analog configuration of the I/O Port
bit.
Alternate Function Output
Alternate Function Input
push-pull or
open-drain
From on-chip
peripheral
To on-chip
peripheral
Output
control
I/O pin
V
DD
V
SS
TTL Schmitt
trigger
VSS
V
DD
or V
DD_FT
(1)
Protection
diode
Protection
diode
on
Input driver
Output driver
P-MOS
N-MOS
I
n
p
u
t

d
a
t
a

r
e
g
i
s
t
e
r
O
u
t
p
u
t

d
a
t
a

r
e
g
i
s
t
e
r
Read/write
Read
B
i
t

s
e
t
/
r
e
s
e
t

r
e
g
i
s
t
e
r
s
Write
ai14785
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs)
Doc ID 13902 Rev 13 161/1093

Figure 18. High impedance-analog configuration
9.1.11 GPIO configurations for device peripherals
Table 22 to Table 33 give the GPIO configurations of the device peripherals.



From on-chip
peripheral
To on-chip
peripheral
Analog Input
I/O pin
TTL Schmitt
trigger
V
SS
V
DD
or V
DD_FT
(1)
Protection
diode
Protection
diode
off
Input driver
0
I
n
p
u
t

d
a
t
a

r
e
g
i
s
t
e
r
O
u
t
p
u
t

d
a
t
a

r
e
g
i
s
t
e
r
Read/write
Read
B
i
t

s
e
t
/
r
e
s
e
t

r
e
g
i
s
t
e
r
s
Write
ai14786
Table 22. Advanced timers TIM1/TIM8
TIM1/8 pinout Configuration GPIO configuration
TIM1/8_CHx
Input capture channel x Input floating
Output compare channel x Alternate function push-pull
TIM1/8_CHxN Complementary output channel x Alternate function push-pull
TIM1/8_BKIN Break input Input floating
TIM1/8_ETR External trigger timer input Input floating
Table 23. General-purpose timers TIM2/3/4/5
TIM2/3/4/5 pinout Configuration GPIO configuration
TIM2/3/4/5_CHx
Input capture channel x Input floating
Output compare channel x Alternate function push-pull
TIM2/3/4/5_ETR External trigger timer input Input floating
Table 24. USARTs
USART pinout Configuration GPIO configuration
USARTx_TX
Full duplex Alternate function push-pull
Half duplex synchronous mode Alternate function push-pull

General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008
162/1093 Doc ID 13902 Rev 13


USARTx_RX
Full duplex Input floating / Input pull-up
Half duplex synchronous mode Not used. Can be used as a general IO
USARTx_CK Synchronous mode Alternate function push-pull
USARTx_RTS Hardware flow control Alternate function push-pull
USARTx_CTS Hardware flow control Input floating/ Input pull-up
Table 25. SPI
SPI pinout Configuration GPIO configuration
SPIx_SCK
Master Alternate function push-pull
Slave Input floating
SPIx_MOSI
Full duplex / master Alternate function push-pull
Full duplex / slave Input floating / Input pull-up
Simplex bidirectional data wire / master Alternate function push-pull
Simplex bidirectional data wire/ slave Not used. Can be used as a GPIO
SPIx_MISO
Full duplex / master Input floating / Input pull-up
Full duplex / slave (point to point) Alternate function push-pull
Full duplex / slave (multi-slave) Alternate function open drain
Simplex bidirectional data wire / master Not used. Can be used as a GPIO
Simplex bidirectional data wire/ slave
(point to point)
Alternate function push-pull
Simplex bidirectional data wire/ slave
(multi-slave)
Alternate function open drain
SPIx_NSS
Hardware master /slave Input floating/ Input pull-up / Input pull-down
Hardware master/ NSS output enabled Alternate function push-pull
Software Not used. Can be used as a GPIO
Table 26. I2S
I2S pinout Configuration GPIO configuration
I2Sx_ WS
Master Alternate function push-pull
Slave Input floating
I2Sx_CK
Master Alternate function push-pull
Slave Input floating
I2Sx_SD
Transmitter Alternate function push-pull
Receiver Input floating/ Input pull-up/ Input pull-down
Table 24. USARTs (continued)
USART pinout Configuration GPIO configuration
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs)
Doc ID 13902 Rev 13 163/1093





I2Sx_MCK
Master Alternate function push-pull
Slave Not used. Can be used as a GPIO
Table 27. I2C
I2C pinout Configuration GPIO configuration
I2Cx_SCL I2C clock Alternate function open drain
I2Cx_SDA I2C Data I/O Alternate function open drain
Table 28. BxCAN
BxCAN pinout GPIO configuration
CAN_TX (Transmit data line) Alternate function push-pull
CAN_RX (Receive data line) Input floating / Input pull-up
Table 29. USB
(1)
1. This table applies to low-, medium-, high and XL-density devices only.
USB pinout GPIO configuration
USB_DM / USB_DP
As soon as the USB is enabled, these pins are connected to the USB
internal transceiver automatically.
Table 30. OTG_FS pin configuration
(1)
OTG_FS pinout Configuration GPIO configuration
OTG_FS_SOF
Host AF push-pull, if used
Device AF push-pull, if used
OTG AF push-pull, if used
OTG_FS_VBUS
(2)
Host Input floating
Device Input floating
OTG Input floating
OTG_FS_ID
Host
No need if the Force host mode is selected by software
(FHMOD set in the OTG_FS_GUSBCFG register)
Device
No need if the Force device mode is selected by software
(FDMOD set in the OTG_FS_GUSBCFG register)
OTG Input pull-up
OTG_FS_DM
Host Controlled automatically by the USB power-down
Device Controlled automatically by the USB power-down
OTG Controlled automatically by the USB power-down
Table 26. I2S
I2S pinout Configuration GPIO configuration

General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008
164/1093 Doc ID 13902 Rev 13

The GPIO configuration of the ADC inputs should be analog.


OTG_FS_DP
Host Controlled automatically by the USB power-down
Device Controlled automatically by the USB power-down
OTG Controlled automatically by the USB power-down
1. This table applies to connectivity line devices only.
2. For the OTG_FS_VBUS pin (PA9) to be used by another shared peripheral or as a general-purpose IO,
the PHY Power-down mode has to be active (clear bit 16 in the OTG_FS_GCCFG register).
Table 31. SDIO
SDIO pinout GPIO configuration
SDIO_CK Alternate function push-pull
SDIO_CMD Alternate function push-pull
SDIO[D7:D0] Alternate function push-pull
Figure 19. ADC / DAC
ADC/DAC pin GPIO configuration
ADC/DAC Analog
Table 32. FSMC
FSMC pinout GPIO configuration
FSMC_A[25:0]
FSMC_D[15:0]
Alternate function push-pull
FSMC_CK Alternate function push-pull
FSMC_NOE
FSMC_NWE
Alternate function push-pull
FSMC_NE[4:1]
FSMC_NCE[3:2]
FSMC_NCE4_1
FSMC_NCE4_2
Alternate function push-pull
FSMC_NWAIT
FSMC_CD
Input floating/ Input pull-up
FSMC_NIOS16,
FSMC_INTR
FSMC_INT[3:2]
Input floating
FSMC_NL
FSMC_NBL[1:0]
Alternate function push-pull
FSMC_NIORD, FSMC_NIOWR
FSMC_NREG
Alternate function push-pull
Table 30. OTG_FS pin configuration
(1)
OTG_FS pinout Configuration GPIO configuration
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs)
Doc ID 13902 Rev 13 165/1093


Table 33. Other IOs
Pins Alternate function GPIO configuration
TAMPER-RTC pin
RTC output
Forced by hardware when configuring the
BKP_CR and BKP_RTCCR registers
Tamper event input
MCO Clock output Alternate function push-pull
EXTI input lines External input interrupts Input floating / input pull-up / input pull-down

General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008
166/1093 Doc ID 13902 Rev 13
9.2 GPIO registers
Refer to Section 2.1 on page 46 for a list of abbreviations used in register descriptions.
The peripheral registers have to be accessed by words (32-bit).
9.2.1 Port configuration register low (GPIOx_CRL) (x=A..G)
Address offset: 0x00
Reset value: 0x4444 4444


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNF7[1:0] MODE7[1:0] CNF6[1:0] MODE6[1:0] CNF5[1:0] MODE5[1:0] CNF4[1:0] MODE4[1:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNF3[1:0] MODE3[1:0] CNF2[1:0] MODE2[1:0] CNF1[1:0] MODE1[1:0] CNF0[1:0] MODE0[1:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:30, 27:26,
23:22, 19:18, 15:14,
11:10, 7:6, 3:2
CNFy[1:0]: Port x configuration bits (y= 0 .. 7)
These bits are written by software to configure the corresponding I/O port.
Refer to Table 20: Port bit configuration table on page 156.
In input mode (MODE[1:0]=00):
00: Analog mode
01: Floating input (reset state)
10: Input with pull-up / pull-down
11: Reserved
In output mode (MODE[1:0] > 00):
00: General purpose output push-pull
01: General purpose output Open-drain
10: Alternate function output Push-pull
11: Alternate function output Open-drain
Bits 29:28, 25:24,
21:20, 17:16, 13:12,
9:8, 5:4, 1:0
MODEy[1:0]: Port x mode bits (y= 0 .. 7)
These bits are written by software to configure the corresponding I/O port.
Refer to Table 20: Port bit configuration table on page 156.
00: Input mode (reset state)
01: Output mode, max speed 10 MHz.
10: Output mode, max speed 2 MHz.
11: Output mode, max speed 50 MHz.
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs)
Doc ID 13902 Rev 13 167/1093

9.2.2 Port configuration register high (GPIOx_CRH) (x=A..G)
Address offset: 0x04
Reset value: 0x4444 4444


9.2.3 Port input data register (GPIOx_IDR) (x=A..G)
Address offset: 0x08h
Reset value: 0x0000 XXXX


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNF15[1:0] MODE15[1:0] CNF14[1:0] MODE14[1:0] CNF13[1:0] MODE13[1:0] CNF12[1:0] MODE12[1:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNF11[1:0] MODE11[1:0] CNF10[1:0] MODE10[1:0] CNF9[1:0] MODE9[1:0] CNF8[1:0] MODE8[1:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:30, 27:26,
23:22, 19:18, 15:14,
11:10, 7:6, 3:2
CNFy[1:0]: Port x configuration bits (y= 8 .. 15)
These bits are written by software to configure the corresponding I/O port.
Refer to Table 20: Port bit configuration table on page 156.
In input mode (MODE[1:0]=00):
00: Analog mode
01: Floating input (reset state)
10: Input with pull-up / pull-down
11: Reserved
In output mode (MODE[1:0] > 00):
00: General purpose output push-pull
01: General purpose output Open-drain
10: Alternate function output Push-pull
11: Alternate function output Open-drain
Bits 29:28, 25:24,
21:20, 17:16, 13:12,
9:8, 5:4, 1:0
MODEy[1:0]: Port x mode bits (y= 8 .. 15)
These bits are written by software to configure the corresponding I/O port.
Refer to Table 20: Port bit configuration table on page 156.
00: Input mode (reset state)
01: Output mode, max speed 10 MHz.
10: Output mode, max speed 2 MHz.
11: Output mode, max speed 50 MHz.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15 IDR14 IDR13 IDR12 IDR11 IDR10 IDR9 IDR8 IDR7 IDR6 IDR5 IDR4 IDR3 IDR2 IDR1 IDR0
r r r r r r r r r r r r r r r r
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 IDRy[15:0]: Port input data (y= 0 .. 15)
These bits are read only and can be accessed in Word mode only. They contain the input
value of the corresponding I/O port.

General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008
168/1093 Doc ID 13902 Rev 13
9.2.4 Port output data register (GPIOx_ODR) (x=A..G)
Address offset: 0x0C
Reset value: 0x0000 0000


9.2.5 Port bit set/reset register (GPIOx_BSRR) (x=A..G)
Address offset: 0x10
Reset value: 0x0000 0000


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15 ODR14 ODR13 ODR12 ODR11 ODR10 ODR9 ODR8 ODR7 ODR6 ODR5 ODR4 ODR3 ODR2 ODR1 ODR0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 ODRy[15:0]: Port output data (y= 0 .. 15)
These bits can be read and written by software and can be accessed in Word mode only.
Note: For atomic bit set/reset, the ODR bits can be individually set and cleared by writing to
the GPIOx_BSRR register (x = A .. G).
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15 BR14 BR13 BR12 BR11 BR10 BR9 BR8 BR7 BR6 BR5 BR4 BR3 BR2 BR1 BR0
w w w w w w w w w w w w w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15 BS14 BS13 BS12 BS11 BS10 BS9 BS8 BS7 BS6 BS5 BS4 BS3 BS2 BS1 BS0
w w w w w w w w w w w w w w w w
Bits 31:16 BRy: Port x Reset bit y (y= 0 .. 15)
These bits are write-only and can be accessed in Word mode only.
0: No action on the corresponding ODRx bit
1: Reset the corresponding ODRx bit
Note: If both BSx and BRx are set, BSx has priority.
Bits 15:0 BSy: Port x Set bit y (y= 0 .. 15)
These bits are write-only and can be accessed in Word mode only.
0: No action on the corresponding ODRx bit
1: Set the corresponding ODRx bit
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs)
Doc ID 13902 Rev 13 169/1093

9.2.6 Port bit reset register (GPIOx_BRR) (x=A..G)
Address offset: 0x14
Reset value: 0x0000 0000


9.2.7 Port configuration lock register (GPIOx_LCKR) (x=A..G)
This register is used to lock the configuration of the port bits when a correct write sequence
is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the
GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the
LOCK sequence has been applied on a port bit it is no longer possible to modify the value of
the port bit until the next reset.
Each lock bit freezes the corresponding 4 bits of the control register (CRL, CRH).
Address offset: 0x18
Reset value: 0x0000 0000


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR15 BR14 BR13 BR12 BR11 BR10 BR9 BR8 BR7 BR6 BR5 BR4 BR3 BR2 BR1 BR0
w w w w w w w w w w w w w w w w
Bits 31:16 Reserved
Bits 15:0 BRy: Port x Reset bit y (y= 0 .. 15)
These bits are write-only and can be accessed in Word mode only.
0: No action on the corresponding ODRx bit
1: Reset the corresponding ODRx bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15 LCK14 LCK13 LCK12 LCK11 LCK10 LCK9 LCK8 LCK7 LCK6 LCK5 LCK4 LCK3 LCK2 LCK1 LCK0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:17 Reserved

General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008
170/1093 Doc ID 13902 Rev 13
9.3 Alternate function I/O and debug configuration (AFIO)
To optimize the number of peripherals available for the 64-pin or the 100-pin or the 144-pin
package, it is possible to remap some alternate functions to some other pins. This is
achieved by software, by programming the AF remap and debug I/O configuration register
(AFIO_MAPR) on page 179. In this case, the alternate functions are no longer mapped to
their original assignations.
9.3.1 Using OSC32_IN/OSC32_OUT pins as GPIO ports PC14/PC15
The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general-purpose I/O
PC14 and PC15, respectively, when the LSE oscillator is off. The LSE has priority over the
GP IOs function.
Note: 1 The PC14/PC15 GPIO functionality is lost when the 1.8 V domain is powered off (by
entering standby mode) or when the backup domain is supplied by V
BAT
(V
DD
no more
supplied). In this case the IOs are set in analog mode.
2 Refer to the note on IO usage restrictions in Section 5.1.2 on page 67.
9.3.2 Using OSC_IN/OSC_OUT pins as GPIO ports PD0/PD1
The HSE oscillator pins OSC_IN/OSC_OUT can be used as general-purpose I/O PD0/PD1
by programming the PD01_REMAP bit in the AF remap and debug I/O configuration register
(AFIO_MAPR).
This remap is available only on 36-, 48- and 64-pin packages (PD0 and PD1 are available
on 100-pin and 144-pin packages, no need for remapping).
Note: The external interrupt/event function is not remapped. PD0 and PD1 cannot be used for
external interrupt/event generation on 36-, 48- and 64-pin packages.
Bit 16 LCKK[16]: Lock key
This bit can be read anytime. It can only be modified using the Lock Key Writing Sequence.
0: Port configuration lock key not active
1: Port configuration lock key active. GPIOx_LCKR register is locked until an MCU reset
occurs.
LOCK key writing sequence:
Write 1
Write 0
Write 1
Read 0
Read 1 (this read is optional but confirms that the lock is active)
Note: During the LOCK Key Writing sequence, the value of LCK[15:0] must not change.
Any error in the lock sequence will abort the lock.
Bits 15:0 LCKy: Port x Lock bit y (y= 0 .. 15)
These bits are read write but can only be written when the LCKK bit is 0.
0: Port configuration not locked
1: Port configuration locked.
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs)
Doc ID 13902 Rev 13 171/1093

9.3.3 CAN1 alternate function remapping
The CAN signals can be mapped on Port A, Port B or Port D as shown in Table 34. For port
D, remapping is not possible in devices delivered in 36-, 48- and 64-pin packages.

9.3.4 CAN2 alternate function remapping
CAN2 is available in connectivity line devices. The external signal can be remapped as
shown in Chapter Table 35.

9.3.5 JTAG/SWD alternate function remapping
The debug interface signals are mapped on the GPIO ports as shown in Table 36.

Table 34. CAN1 alternate function remapping
Alternate function
(1)
1. CAN1_RX and CAN1_TX in connectivity line devices; CAN_RX and CAN_TX in other devices with a single
CAN interface.
CAN_REMAP[1:0] =
00
CAN_REMAP[1:0] =
10
(2)
2. Remap not available on 36-pin package
CAN_REMAP[1:0] =
11
(3)
3. This remapping is available only on 100-pin and 144-pin packages, when PD0 and PD1 are not remapped
on OSC-IN and OSC-OUT.
CAN1_RX or CAN_RX PA11 PB8 PD0
CAN1_TX or CAN_RX PA12 PB9 PD1
Table 35. CAN2 alternate function remapping
Alternate function CAN2_REMAP = 0 CAN2_REMAP = 1
CAN2_RX PB12 PB5
CAN2_TX PB13 PB6
Table 36. Debug interface signals
Alternate function GPIO port
JTMS / SWDIO PA13
JTCK / SWCLK PA14
JTDI PA15
JTDO / TRACESWO PB3
NJTRST PB4
TRACECK PE2
TRACED0 PE3
TRACED1 PE4
TRACED2 PE5
TRACED3 PE6

General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008
172/1093 Doc ID 13902 Rev 13
To optimize the number of free GPIOs during debugging, this mapping can be configured in
different ways by programming the SWJ_CFG[1:0] bits in the AF remap and debug I/O
configuration register (AFIO_MAPR). Refer to Table 37

9.3.6 ADC alternate function remapping
Refer to AF remap and debug I/O configuration register (AFIO_MAPR).



Table 37. Debug port mapping
SWJ _CFG
[2:0]
Available debug ports
SWJ I/O pin assigned
PA13 /
JTMS/
SWDIO
PA14 /
JTCK/S
WCLK
PA15 /
JTDI
PB3 / JTDO/
TRACE
SWO
PB4/
NJTRST
000
Full SWJ (JTAG-DP + SW-DP)
(Reset state)
X X X X X
001
Full SWJ (JTAG-DP + SW-DP)
but without NJTRST
X X X x free
010
JTAG-DP Disabled and
SW-DP Enabled
X X free free
(1)
1. Released only if not using asynchronous trace.
free
100
JTAG-DP Disabled and
SW-DP Disabled
free free free free free
Other Forbidden
Table 38. ADC1 external trigger injected conversion alternate function remapping
(1)
1. Remap available only for high-density and XL-density devices.
Alternate function ADC1_ETRGINJ_REMAP = 0 ADC1_ETRGINJ_REMAP = 1
ADC1 external trigger injected
conversion
ADC1 external trigger injected
conversion is connected to
EXTI15
ADC1 external trigger injected
conversion is connected to
TIM8_CH4
Table 39. ADC1 external trigger regular conversion alternate function remapping
(1)
1. Remap available only for high-density and XL-density devices.
Alternate function ADC1_ETRGREG_REMAP = 0 ADC1_ETRGREG_REMAP = 1
ADC1 external trigger regular
conversion
ADC1 external trigger regular
conversion is connected to
EXTI11
ADC1 external trigger regular
conversion is connected to
TIM8_TRGO
Table 40. ADC2 external trigger injected conversion alternate function remapping
(1)
1. Remap available only for high-density and XL-density devices.
Alternate function ADC2_ETRGINJ_REMAP = 0 ADC2_ETRGINJ_REMAP = 1
ADC2 external trigger injected
conversion
ADC2 external trigger injected
conversion is connected to
EXTI 15
ADC2 external trigger injected
conversion is connected to
TIM8_CH4
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs)
Doc ID 13902 Rev 13 173/1093


9.3.7 Timer alternate function remapping
Timer 4 channels 1 to 4 can be remapped from Port B to Port D. Other timer remapping
possibilities are listed in Table 44 to Table 46. Refer to AF remap and debug I/O
configuration register (AFIO_MAPR).



Table 41. ADC2 external trigger regular conversion alternate function remapping
(1)
1. Remap available only for high-density and XL-density devices.
Alternate function ADC2_ETRGREG_REG = 0 ADC2_ETRGREG_REG = 1
ADC2 external trigger regular
conversion
ADC2 external trigger regular
conversion is connected to
EXTI11
ADC2 external trigger regular
conversion is connected to
TIM8_TRGO
Table 42. TIM5 alternate function remapping
(1)
1. Remap available only for high-density, XL-density and connectivity line devices.
Alternate function TIM5CH4_IREMAP = 0 TIM5CH4_IREMAP = 1
TIM5_CH4
TIM5 Channel4 is
connected to PA3
LSI internal clock is connected to TIM5_CH4
input for calibration purpose.
Table 43. TIM4 alternate function remapping
Alternate function TIM4_REMAP = 0 TIM4_REMAP = 1
(1)
1. Remap available only for 100-pin and for 144-pin package.
TIM4_CH1 PB6 PD12
TIM4_CH2 PB7 PD13
TIM4_CH3 PB8 PD14
TIM4_CH4 PB9 PD15
Table 44. TIM3 alternate function remapping
Alternate function
TIM3_REMAP[1:0] =
00 (no remap)
TIM3_REMAP[1:0] =
10 (partial remap)
TIM3_REMAP[1:0] =
11 (full remap)
(1)
1. Remap available only for 64-pin, 100-pin and 144-pin packages.
TIM3_CH1 PA6 PB4 PC6
TIM3_CH2 PA7 PB5 PC7
TIM3_CH3 PB0 PC8
TIM3_CH4 PB1 PC9

General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008
174/1093 Doc ID 13902 Rev 13




Table 45. TIM2 alternate function remapping
Alternate function
TIM2_REMAP[1:
0] = 00 (no
remap)
TIM2_REMAP[1:
0] = 01 (partial
remap)
TIM2_REMAP[1:
0] = 10 (partial
remap)
(1)
1. Remap not available on 36-pin package.
TIM2_REMAP[1:
0] = 11 (full
remap)
(1)
TIM2_CH1_ETR
(2)
2. TIM_CH1 and TIM_ETR share the same pin but cannot be used at the same time (which is why we have
this notation: TIM2_CH1_ETR).
PA0 PA15 PA0 PA15
TIM2_CH2 PA1 PB3 PA1 PB3
TIM2_CH3 PA2 PB10
TIM2_CH4 PA3 PB11
Table 46. TIM1 alternate function remapping
Alternate functions
mapping
TIM1_REMAP[1:0] =
00 (no remap)
TIM1_REMAP[1:0] =
01 (partial remap)
TIM1_REMAP[1:0] =
11 (full remap)
(1)
1. Remap available only for 100-pin and 144-pin packages.
TIM1_ETR PA12 PE7
TIM1_CH1 PA8 PE9
TIM1_CH2 PA9 PE11
TIM1_CH3 PA10 PE13
TIM1_CH4 PA11 PE14
TIM1_BKIN PB12
(2)
2. Remap not available on 36-pin package.
PA6 PE15
TIM1_CH1N PB13 PA7 PE8
TIM1_CH2N PB14
(2)
PB0 PE10
TIM1_CH3N PB15
(2)
PB1 PE12
Table 47. TIM9 remapping
(1)
1. Refer to the AF remap and debug I/O configuration register Section 9.4.7: AF remap and debug I/O
configuration register2 (AFIO_MAPR2).
Alternate function TIM9_REMAP = 0 TIM9_REMAP = 1
TIM9_CH1 PA2 PE5
TIM9_CH2 PA3 PE6
Table 48. TIM10 remapping
(1)
1. Refer to the AF remap and debug I/O configuration register Section 9.4.7: AF remap and debug I/O
configuration register2 (AFIO_MAPR2).
Alternate function TIM10_REMAP = 0 TIM10_REMAP = 1
TIM10_CH1 PB8 PF6
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs)
Doc ID 13902 Rev 13 175/1093




9.3.8 USART alternate function remapping
Refer to AF remap and debug I/O configuration register (AFIO_MAPR).


Table 49. TIM11 remapping
(1)
1. Refer to the AF remap and debug I/O configuration register Section 9.4.7: AF remap and debug I/O
configuration register2 (AFIO_MAPR2).
Alternate function TIM11_REMAP = 0 TIM11_REMAP = 1
TIM11_CH1 PB9 PF7
Table 50. TIM13 remapping
(1)
1. Refer to the AF remap and debug I/O configuration registerSection 9.4.7: AF remap and debug I/O
configuration register2 (AFIO_MAPR2).
Alternate function TIM13_REMAP = 0 TIM13_REMAP = 1
TIM13_CH1 PA6 PF8
Table 51. TIM14 remapping
(1)
1. Refer to the AF remap and debug I/O configuration register Section 9.4.7: AF remap and debug I/O
configuration register2 (AFIO_MAPR2).
Alternate function TIM14_REMAP = 0 TIM14_REMAP = 1
TIM14_CH1 PA7 PF9
Table 52. USART3 remapping
Alternate function
USART3_REMAP[1:0]
= 00 (no remap)
USART3_REMAP[1:0] =
01 (partial remap)
(1)
1. Remap available only for 64-pin, 100-pin and 144-pin packages
USART3_REMAP[1:0]
= 11 (full remap)
(2)
2. Remap available only for 100-pin and 144-pin packages.
USART3_TX PB10 PC10 PD8
USART3_RX PB11 PC11 PD9
USART3_CK PB12 PC12 PD10
USART3_CTS PB13 PD11
USART3_RTS PB14 PD12
Table 53. USART2 remapping
Alternate functions USART2_REMAP = 0 USART2_REMAP = 1
(1)
1. Remap available only for 100-pin and 144-pin packages.
USART2_CTS PA0 PD3
USART2_RTS PA1 PD4
USART2_TX PA2 PD5
USART2_RX PA3 PD6
USART2_CK PA4 PD7

General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008
176/1093 Doc ID 13902 Rev 13

9.3.9 I2C1 alternate function remapping
Refer to AF remap and debug I/O configuration register (AFIO_MAPR)

9.3.10 SPI1 alternate function remapping
Refer to AF remap and debug I/O configuration register (AFIO_MAPR)

9.3.11 SPI3/I2S3 alternate function remapping
Refer to AF remap and debug I/O configuration register (AFIO_MAPR). This remap is
available only in connectivity line devices.

9.3.12 Ethernet alternate function remapping
Refer to AF remap and debug I/O configuration register (AFIO_MAPR). Ethernet is available
only in connectivity line devices.
Table 54. USART1 remapping
Alternate function USART1_REMAP = 0 USART1_REMAP = 1
USART1_TX PA9 PB6
USART1_RX PA10 PB7
Table 55. I2C1 remapping
Alternate function I2C1_REMAP = 0 I2C1_REMAP = 1
(1)
1. Remap not available on 36-pin package.
I2C1_SCL PB6 PB8
I2C1_SDA PB7 PB9
Table 56. SPI1 remapping
Alternate function SPI1_REMAP = 0 SPI1_REMAP = 1
SPI1_NSS PA4 PA15
SPI1_SCK PA5 PB3
SPI1_MISO PA6 PB4
SPI1_MOSI PA7 PB5
Table 57. SPI3/I2S3 remapping
Alternate function SPI3_REMAP = 0 SPI3_REMAP = 1
SPI3_NSS / I2S3_WS PA15 PA4
SPI3_SCK / I2S3_CK PB3 PC10
SPI3_MISO PB4 PC11
SPI3_MOSI / I2S3_SD PB5 PC12
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs)
Doc ID 13902 Rev 13 177/1093


9.4 AFIO registers
Refer to Section 2.1 on page 46for a list of abbreviations used in register descriptions.
Note: To read/write the AFIO_EVCR, AFIO_MAPR and AFIO_EXTICRX registers, the AFIO clock
should first be enabled. Refer to Section 7.3.7: APB2 peripheral clock enable register
(RCC_APB2ENR).
The peripheral registers have to be accessed by words (32-bit).
Table 58. ETH remapping
Alternate function ETH_REMAP = 0 ETH_REMAP = 1
RX_DV-CRS_DV PA7 PD8
RXD0 PC4 PD9
RXD1 PC5 PD10
RXD2 PB0 PD11
RXD3 PB1 PD12

General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008
178/1093 Doc ID 13902 Rev 13
9.4.1 Event control register (AFIO_EVCR)
Address offset: 0x00
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
EVOE PORT[2:0] PIN[3:0]
rw rw rw rw rw rw rw rw
Bits 31:8 Reserved
Bit 7 EVOE: Event output enable
Set and cleared by software. When set the EVENTOUT Cortex output is connected to the
I/O selected by the PORT[2:0] and PIN[3:0] bits.
Bits 6:4 PORT[2:0]: Port selection
Set and cleared by software. Select the port used to output the Cortex EVENTOUT signal.
Note: The EVENTOUT signal output capability is not extended to ports PF and PG.
000: PA selected
001: PB selected
010: PC selected
011: PD selected
100: PE selected
Bits 3:0 PIN[3:0]: Pin selection (x = A .. E)
Set and cleared by software. Select the pin used to output the Cortex EVENTOUT signal.
0000: Px0 selected
0001: Px1 selected
0010: Px2 selected
0011: Px3 selected
...
1111: Px15 selected
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs)
Doc ID 13902 Rev 13 179/1093

9.4.2 AF remap and debug I/O configuration register (AFIO_MAPR)
Address offset: 0x04
Reset value: 0x0000 0000
Memory map and bit definitions for low-, medium- high- and XL-density
devices:


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
SWJ_
CFG[2:0]
Reserved
ADC2_
ETRGR
EG_RE
MAP
ADC2_ET
RGINJ_R
EMAP
ADC1_ET
RGREG_
REMAP
ADC1_
ETRGIN
J_REM
AP
TIM5CH
4_IREM
AP
w w w rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD01_
REMAP
CAN_REMAP
[1:0]
TIM4_
REMAP
TIM3_REMAP
[1:0]
TIM2_REMAP
[1:0]
TIM1_REMAP
[1:0]
USART3_
REMAP[1:0]
USART2_
REMAP
USART1_
REMAP
I2C1_
REMAP
SPI1_
REMAP
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:27 Reserved
Bits 26:24 SWJ_CFG[2:0]: Serial wire JTAG configuration
These bits are write-only (when read, the value is undefined). They are used to configure the
SWJ and trace alternate function I/Os. The SWJ (Serial Wire JTAG) supports JTAG or SWD
access to the Cortex debug port. The default state after reset is SWJ ON without trace. This
allows JTAG or SW mode to be enabled by sending a specific sequence on the JTMS /
JTCK pin.
000: Full SWJ (JTAG-DP + SW-DP): Reset State
001: Full SWJ (JTAG-DP + SW-DP) but without NJTRST
010: JTAG-DP Disabled and SW-DP Enabled
100: JTAG-DP Disabled and SW-DP Disabled
Other combinations: no effect
Bits 23:21 Reserved.
Bits 20 ADC2_ETRGREG_REMAP: ADC 2 external trigger regular conversion remapping
Set and cleared by software. This bit controls the trigger input connected to ADC2 external
trigger regular conversion. When this bit is reset, the ADC2 external trigger regular
conversion is connected to EXTI11. When this bit is set, the ADC2 external event regular
conversion is connected to TIM8_TRGO.
Bits 19 ADC2_ETRGINJ_REMAP: ADC 2 external trigger injected conversion remapping
Set and cleared by software. This bit controls the trigger input connected to ADC2 external
trigger injected conversion. When this bit is reset, the ADC2 external trigger injected
conversion is connected to EXTI15. When this bit is set, the ADC2 external event injected
conversion is connected to TIM8_Channel4.
Bits 18 ADC1_ETRGREG_REMAP: ADC 1 external trigger regular conversion remapping
Set and cleared by software. This bit controls the trigger input connected to ADC1
External trigger regular conversion. When reset the ADC1 External trigger regular
conversion is connected to EXTI11. When set the ADC1 External Event regular conversion
is connected to TIM8 TRGO.

General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008
180/1093 Doc ID 13902 Rev 13
Bits 17 ADC1_ETRGINJ_REMAP: ADC 1 External trigger injected conversion remapping
Set and cleared by software. This bit controls the trigger input connected to ADC1
External trigger injected conversion. When reset the ADC1 External trigger injected
conversion is connected to EXTI15. When set the ADC1 External Event injected conversion
is connected to TIM8 Channel4.
Bits 16 TIM5CH4_IREMAP: TIM5 channel4 internal remap
Set and cleared by software. This bit controls the TIM5_CH4 internal mapping. When reset
the timer TIM5_CH4 is connected to PA3. When set the LSI internal clock is connected to
TIM5_CH4 input for calibration purpose.
Note: This bit is available only in high density value line devices.
Bit 15 PD01_REMAP: Port D0/Port D1 mapping on OSC_IN/OSC_OUT
This bit is set and cleared by software. It controls the mapping of PD0 and PD1 GPIO
functionality. When the HSE oscillator is not used (application running on internal 8 MHz RC)
PD0 and PD1 can be mapped on OSC_IN and OSC_OUT. This is available only on 36-, 48-
and 64-pin packages (PD0 and PD1 are available on 100-pin and 144-pin packages, no
need for remapping).
0: No remapping of PD0 and PD1
1: PD0 remapped on OSC_IN, PD1 remapped on OSC_OUT,
Bits 14:13 CAN_REMAP[1:0]: CAN alternate function remapping
These bits are set and cleared by software. They control the mapping of alternate functions
CAN_RX and CAN_TX in devices with a single CAN interface.
00: CAN_RX mapped to PA11, CAN_TX mapped to PA12
01: Not used
10: CAN_RX mapped to PB8, CAN_TX mapped to PB9 (not available on 36-pin package)
11: CAN_RX mapped to PD0, CAN_TX mapped to PD1
Bit 12 TIM4_REMAP: TIM4 remapping
This bit is set and cleared by software. It controls the mapping of TIM4 channels 1 to 4 onto
the GPIO ports.
0: No remap (TIM4_CH1/PB6, TIM4_CH2/PB7, TIM4_CH3/PB8, TIM4_CH4/PB9)
1: Full remap (TIM4_CH1/PD12, TIM4_CH2/PD13, TIM4_CH3/PD14, TIM4_CH4/PD15)
Note: TIM4_ETR on PE0 is not re-mapped.
Bits 11:10 TIM3_REMAP[1:0]: TIM3 remapping
These bits are set and cleared by software. They control the mapping of TIM3 channels 1 to
4 on the GPIO ports.
00: No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1)
01: Not used
10: Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1)
11: Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9)
Note: TIM3_ETR on PE0 is not re-mapped.
Bits 9:8 TIM2_REMAP[1:0]: TIM2 remapping
These bits are set and cleared by software. They control the mapping of TIM2 channels 1 to
4 and external trigger (ETR) on the GPIO ports.
00: No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3)
01: Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3)
10: Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11)
11: Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11)
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs)
Doc ID 13902 Rev 13 181/1093

Bits 7:6 TIM1_REMAP[1:0]: TIM1 remapping
These bits are set and cleared by software. They control the mapping of TIM1 channels 1 to
4, 1N to 3N, external trigger (ETR) and Break input (BKIN) on the GPIO ports.
00: No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12,
CH1N/PB13, CH2N/PB14, CH3N/PB15)
01: Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6,
CH1N/PA7, CH2N/PB0, CH3N/PB1)
10: not used
11: Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15,
CH1N/PE8, CH2N/PE10, CH3N/PE12)
Bits 5:4 USART3_REMAP[1:0]: USART3 remapping
These bits are set and cleared by software. They control the mapping of USART3 CTS,
RTS,CK,TX and RX alternate functions on the GPIO ports.
00: No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14)
01: Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14)
10: not used
11: Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12)
Bit 3 USART2_REMAP: USART2 remapping
This bit is set and cleared by software. It controls the mapping of USART2 CTS, RTS,CK,TX
and RX alternate functions on the GPIO ports.
0: No remap (CTS/PA0, RTS/PA1, TX/PA2, RX/PA3, CK/PA4)
1: Remap (CTS/PD3, RTS/PD4, TX/PD5, RX/PD6, CK/PD7)
Bit 2 USART1_REMAP: USART1 remapping
This bit is set and cleared by software. It controls the mapping of USART1 TX and RX
alternate functions on the GPIO ports.
0: No remap (TX/PA9, RX/PA10)
1: Remap (TX/PB6, RX/PB7)
Bit 1 I2C1_REMAP: I2C1 remapping
This bit is set and cleared by software. It controls the mapping of I2C1 SCL and SDA
alternate functions on the GPIO ports.
0: No remap (SCL/PB6, SDA/PB7)
1: Remap (SCL/PB8, SDA/PB9)
Bit 0 SPI1_REMAP: SPI1 remapping
This bit is set and cleared by software. It controls the mapping of SPI1 NSS, SCK, MISO,
MOSI alternate functions on the GPIO ports.
0: No remap (NSS/PA4, SCK/PA5, MISO/PA6, MOSI/PA7)
1: Remap (NSS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5)

General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008
182/1093 Doc ID 13902 Rev 13
Memory map and bit definitions for connectivity line devices:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res.
PTP_P
PS_RE
MAP
TIM2ITR
1_
IREMAP
SPI3_
REMAP
Res.
SWJ_
CFG[2:0]
MII_RMI
I_SEL
CAN2_
REMAP
ETH_R
EMAP
Reserved
TIM5CH
4_IREM
AP
rw rw rw w w w rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD01_
REMAP
CAN1_REMAP
[1:0]
TIM4_
REMAP
TIM3_REMAP
[1:0]
TIM2_REMAP
[1:0]
TIM1_REMAP
[1:0]
USART3_
REMAP[1:0]
USART2_
REMAP
USART1_
REMAP
I2C1_
REMAP
SPI1_
REMAP
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bit 31 Reserved, must be kept at reset value.
Bit 30 PTP_PPS_REMAP: Ethernet PTP PPS remapping
This bit is set and cleared by software. It enables the Ethernet MAC PPS_PTS to be output
on the PB5 pin.
0: PTP_PPS not output on PB5 pin.
1: PTP_PPS is output on PB5 pin.
Note: This bit is available only in connectivity line devices and is reserved otherwise.
Bit 29 TIM2ITR1_IREMAP: TIM2 internal trigger 1 remapping
This bit is set and cleared by software. It controls the TIM2_ITR1 internal mapping.
0: Connect TIM2_ITR1 internally to the Ethernet PTP output for calibration purposes.
1: Connect USB OTG SOF (Start of Frame) output to TIM2_ITR1 for calibration purposes.
Note: This bit is available only in connectivity line devices and is reserved otherwise.
Bit 28 SPI3_REMAP: SPI3/I2S3 remapping
This bit is set and cleared by software. It controls the mapping of SPI3_NSS/I2S3_WS,
SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD alternate functions on the GPIO
ports.
0: No remap (SPI_NSS-I2S3_WS/PA15, SPI3_SCK-I2S3_CK/PB3, SPI3_MISO/PB4,
SPI3_MOSI-I2S3_SD/PB5)
1: Remap (SPI3_NSS-I2S3_WS/PA4, SPI3_SCK-I2S3_CK/PC10, SPI3_MISO/PC11,
SPI3_MOSI-I2S3_SD/PC12)
Note: This bit is available only in connectivity line devices and is reserved otherwise.
Bit 27 Reserved
Bits 26:24 SWJ_CFG[2:0]: Serial wire JTAG configuration
These bits are write-only (when read, the value is undefined). They are used to configure the
SWJ and trace alternate function I/Os. The SWJ (Serial Wire JTAG) supports JTAG or SWD
access to the Cortex debug port. The default state after reset is SWJ ON without trace. This
allows JTAG or SW mode to be enabled by sending a specific sequence on the JTMS /
JTCK pin.
000: Full SWJ (JTAG-DP + SW-DP): Reset State
001: Full SWJ (JTAG-DP + SW-DP) but without NJTRST
010: JTAG-DP Disabled and SW-DP Enabled
100: JTAG-DP Disabled and SW-DP Disabled
Other combinations: no effect
Bit 23 MII_RMII_SEL: MII or RMII selection
This bit is set and cleared by software. It configures the Ethernet MAC internally for use with
an external MII or RMII PHY.
0: Configure Ethernet MAC for connection with an MII PHY
1: Configure Ethernet MAC for connection with an RMII PHY
Note: This bit is available only in connectivity line devices and is reserved otherwise.
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs)
Doc ID 13902 Rev 13 183/1093

Bit 22 CAN2_REMAP: CAN2 I/O remapping
This bit is set and cleared by software. It controls the CAN2_TX and CAN2_RX pins.
0: No remap (CAN2_RX/PB12, CAN2_TX/PB13)
1: Remap (CAN2_RX/PB5, CAN2_TX/PB6)
Note: This bit is available only in connectivity line devices and is reserved otherwise.
Bit 21 ETH_REMAP: Ethernet MAC I/O remapping
This bit is set and cleared by software. It controls the Ethernet MAC connections with the
PHY.
0: No remap (RX_DV-CRS_DV/PA7, RXD0/PC4, RXD1/PC5, RXD2/PB0, RXD3/PB1)
1: Remap (RX_DV-CRS_DV/PD8, RXD0/PD9, RXD1/PD10, RXD2/PD11, RXD3/PD12)
Note: This bit is available only in connectivity line devices and is reserved otherwise.
Bits 20:17 Reserved
Bits 16 TIM5CH4_IREMAP: TIM5 channel4 internal remap
Set and cleared by software. This bit controls the TIM5_CH4 internal mapping. When reset
the timer TIM5_CH4 is connected to PA3. When set the LSI internal clock is connected to
TIM5_CH4 input for calibration purpose.
Bit 15 PD01_REMAP: Port D0/Port D1 mapping on OSC_IN/OSC_OUT
This bit is set and cleared by software. It controls the mapping of PD0 and PD1 GPIO
functionality. When the HSE oscillator is not used (application running on internal 8 MHz RC)
PD0 and PD1 can be mapped on OSC_IN and OSC_OUT. This is available only on 36-, 48-
and 64-pin packages (PD0 and PD1 are available on 100-pin and 144-pin packages, no
need for remapping).
0: No remapping of PD0 and PD1
1: PD0 remapped on OSC_IN, PD1 remapped on OSC_OUT,
Bits 14:13 CAN1_REMAP[1:0]: CAN1 alternate function remapping
These bits are set and cleared by software. They control the mapping of alternate functions
CAN1_RX and CAN1_TX.
00: CAN1_RX mapped to PA11, CAN1_TX mapped to PA12
01: Not used
10: CAN1_RX mapped to PB8, CAN1_TX mapped to PB9 (not available on 36-pin package)
11: CAN1_RX mapped to PD0, CAN1_TX mapped to PD1
Bit 12 TIM4_REMAP: TIM4 remapping
This bit is set and cleared by software. It controls the mapping of TIM4 channels 1 to 4 onto
the GPIO ports.
0: No remap (TIM4_CH1/PB6, TIM4_CH2/PB7, TIM4_CH3/PB8, TIM4_CH4/PB9)
1: Full remap (TIM4_CH1/PD12, TIM4_CH2/PD13, TIM4_CH3/PD14, TIM4_CH4/PD15)
Note: TIM4_ETR on PE0 is not re-mapped.
Bits 11:10 TIM3_REMAP[1:0]: TIM3 remapping
These bits are set and cleared by software. They control the mapping of TIM3 channels 1 to
4 on the GPIO ports.
00: No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1)
01: Not used
10: Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1)
11: Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9)
Note: TIM3_ETR on PE0 is not re-mapped.

General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008
184/1093 Doc ID 13902 Rev 13
Bits 9:8 TIM2_REMAP[1:0]: TIM2 remapping
These bits are set and cleared by software. They control the mapping of TIM2 channels 1 to
4 and external trigger (ETR) on the GPIO ports.
00: No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3)
01: Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3)
10: Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11)
11: Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11)
Bits 7:6 TIM1_REMAP[1:0]: TIM1 remapping
These bits are set and cleared by software. They control the mapping of TIM1 channels 1 to
4, 1N to 3N, external trigger (ETR) and Break input (BKIN) on the GPIO ports.
00: No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12,
CH1N/PB13, CH2N/PB14, CH3N/PB15)
01: Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6,
CH1N/PA7, CH2N/PB0, CH3N/PB1)
10: not used
11: Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15,
CH1N/PE8, CH2N/PE10, CH3N/PE12)
Bits 5:4 USART3_REMAP[1:0]: USART3 remapping
These bits are set and cleared by software. They control the mapping of USART3 CTS,
RTS,CK,TX and RX alternate functions on the GPIO ports.
00: No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14)
01: Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14)
10: not used
11: Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12)
Bit 3 USART2_REMAP: USART2 remapping
This bit is set and cleared by software. It controls the mapping of USART2 CTS, RTS,CK,TX
and RX alternate functions on the GPIO ports.
0: No remap (CTS/PA0, RTS/PA1, TX/PA2, RX/PA3, CK/PA4)
1: Remap (CTS/PD3, RTS/PD4, TX/PD5, RX/PD6, CK/PD7)
Bit 2 USART1_REMAP: USART1 remapping
This bit is set and cleared by software. It controls the mapping of USART1 TX and RX
alternate functions on the GPIO ports.
0: No remap (TX/PA9, RX/PA10)
1: Remap (TX/PB6, RX/PB7)
Bit 1 I2C1_REMAP: I2C1 remapping
This bit is set and cleared by software. It controls the mapping of I2C1 SCL and SDA
alternate functions on the GPIO ports.
0: No remap (SCL/PB6, SDA/PB7)
1: Remap (SCL/PB8, SDA/PB9)
Bit 0 SPI1_REMAP: SPI1 remapping
This bit is set and cleared by software. It controls the mapping of SPI1 NSS, SCK, MISO,
MOSI alternate functions on the GPIO ports.
0: No remap (NSS/PA4, SCK/PA5, MISO/PA6, MOSI/PA7)
1: Remap (NSS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5)
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs)
Doc ID 13902 Rev 13 185/1093

9.4.3 External interrupt configuration register 1 (AFIO_EXTICR1)
Address offset: 0x08
Reset value: 0x0000

9.4.4 External interrupt configuration register 2 (AFIO_EXTICR2)
Address offset: 0x0C
Reset value: 0x0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI3[3:0] EXTI2[3:0] EXTI1[3:0] EXTI0[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:16 Reserved
Bits 15:0 EXTIx[3:0]: EXTI x configuration (x= 0 to 3)
These bits are written by software to select the source input for EXTIx external interrupt.
Refer to Section 10.2.5: External interrupt/event line mapping on page 200
0000: PA[x] pin
0001: PB[x] pin
0010: PC[x] pin
0011: PD[x] pin
0100: PE[x] pin
0101: PF[x] pin
0110: PG[x] pin
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI7[3:0] EXTI6[3:0] EXTI5[3:0] EXTI4[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:16 Reserved
Bits 15:0 EXTIx[3:0]: EXTI x configuration (x= 4 to 7)
These bits are written by software to select the source input for EXTIx external interrupt.
0000: PA[x] pin
0001: PB[x] pin
0010: PC[x] pin
0011: PD[x] pin
0100: PE[x] pin
0101: PF[x] pin
0110: PG[x] pin

General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008
186/1093 Doc ID 13902 Rev 13
9.4.5 External interrupt configuration register 3 (AFIO_EXTICR3)
Address offset: 0x10
Reset value: 0x0000

9.4.6 External interrupt configuration register 4 (AFIO_EXTICR4)
Address offset: 0x14
Reset value: 0x0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI11[3:0] EXTI10[3:0] EXTI9[3:0] EXTI8[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:16 Reserved
Bits 15:0 EXTIx[3:0]: EXTI x configuration (x= 8 to 11)
These bits are written by software to select the source input for EXTIx external interrupt.
0000: PA[x] pin
0001: PB[x] pin
0010: PC[x] pin
0011: PD[x] pin
0100: PE[x] pin
0101: PF[x] pin
0110: PG[x] pin
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI15[3:0] EXTI14[3:0] EXTI13[3:0] EXTI12[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:16 Reserved
Bits 15:0 EXTIx[3:0]: EXTI x configuration (x= 12 to 15)
These bits are written by software to select the source input for EXTIx external interrupt.
0000: PA[x] pin
0001: PB[x] pin
0010: PC[x] pin
0011: PD[x] pin
0100: PE[x] pin
0101: PF[x] pin
0110: PG[x] pin
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs)
Doc ID 13902 Rev 13 187/1093

9.4.7 AF remap and debug I/O configuration register2 (AFIO_MAPR2)
Address offset: 0x1C
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
FSMC_
NADV
TIM14_
REMAP
TIM13_
REMAP
TIM11_
REMAP
TIM10_
REMAP
TIM9_R
EMAP
Reserved
rw rw rw rw rw rw
Bits 31:11 Reserved.
Bit 10 FSMC_NADV: NADV connect/disconnect
This bit is set and cleared by software. It controls the use of the optional FSMC_NADV
signal.
0: The NADV signal is connected to the output (default)
1: The NADV signal is not connected. The I/O pin can be used by another peripheral.
Bit 9 TIM14_REMAP: TIM14 remapping
This bit is set and cleared by software. It controls the mapping of the TIM14_CH1 alternate
function onto the GPIO ports.
0: No remap (PA7)
1: Remap (PF9)
Bit 8 TIM13_REMAP: TIM13 remapping
This bit is set and cleared by software. It controls the mapping of the TIM13_CH1 alternate
function onto the GPIO ports.
0: No remap (PA6)
1: Remap (PF8)
Bit 7 TIM11_REMAP: TIM11 remapping
This bit is set and cleared by software. It controls the mapping of the TIM11_CH1 alternate
function onto the GPIO ports.
0: No remap (PB9)
1: Remap (PF7)
Bit 6 TIM10_REMAP: TIM10 remapping
This bit is set and cleared by software. It controls the mapping of the TIM10_CH1 alternate
function onto the GPIO ports.
0: No remap (PB8)
1: Remap (PF6)
Bit 5 TIM9_REMAP: TIM9 remapping
This bit is set and cleared by software. It controls the mapping of the TIM9_CH1 and
TIM9_CH2 alternate functions onto the GPIO ports.
0: No remap (TIM9_CH1 on PA2 and TIM9_CH2 on PA3)
1: Remap (TIM9_CH1 on PE5 and TIM9_CH2 on PE6)
Bits 4:0 Reserved.

General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008
188/1093 Doc ID 13902 Rev 13
9.5 GPIO and AFIO register maps
Refer to Table 3 on page 50 for the register boundary addresses. The following tables give
the GPIO and AFIO register map and the reset values.


Table 59. GPIO register map and reset values
Offset Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9 8 7 6 5 4 3 2 1 0
0x00
GPIOx_CRL
CNF7
[1:0]
MODE7
[1:0]
CNF6
[1:0]
MODE6
[1:0]
CNF5
[1:0]
MODE5
[1:0]
CNF4
[1:0]
MODE4
[1:0]
CNF3
[1:0]
MODE3
[1:0]
CNF2
[1:0]
MODE2
[1:0]
CNF1
[1:0]
MODE1
[1:0]
CNF0
[1:0]
MODE0
[1:0]
Reset value 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0
0x04
GPIOx_CRH
CNF
15
[1:0]
MODE1
5
[1:0]
CNF
14
[1:0]
MODE1
4
[1:0]
CNF
13
[1:0]
MODE1
3
[1:0]
CNF
12
[1:0]
MODE1
2
[1:0]
CNF
11
[1:0]
MODE1
1
[1:0]
CNF
10
[1:0]
MODE1
0
[1:0]
CNF
9
[1:0]
MODE9
[1:0]
CNF
8
[1:0]
MODE8
[1:0]
Reset value 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0
0x08
GPIOx_IDR
Reserved
IDR[15:0]l
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x0C
GPIOx_ODR
Reserved
ODR[15:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x10
GPIOx_BSRR BR[15:0] BSR[15:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x14
GPIOx_BRR
Reserved
BR[15:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x18
GPIOx_LCKR
Reserved
L
C
K
K
LCK[15:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 60. AFIO register map and reset values
Offset Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9 8 7 6 5 4 3 2 1 0
0x00
AFIO_EVCR
Reserved
E
V
O
E
PORT[2:0] PIN[3:0]
Reset value 0 0 0 0 0 0 0
0x04
AFIO_MAPR
low-, medium-,
high- and XL-
density devices
Reserved
S
W
J
_
C
F
G
[
2
]
S
W
J
_
C
F
G
[
1
]
S
W
J
_
C
F
G
[
0
]
Reserved
A
D
C
2
_
E
T
R
G
R
E
G
_
R
E
M
A
P
A
D
C
2
_
E
T
R
G
I
N
J
_
R
E
M
A
P
A
D
C
1
_
E
T
R
G
R
E
G
_
R
E
M
A
P
A
D
C
1
_
E
T
R
G
I
N
J
_
R
E
M
A
P
T
I
M
5
C
H
4
_
I
R
E
M
A
P
P
D
0
1
_
R
E
M
A
P
C
A
N
1
_
R
E
M
A
P
[
1
]
C
A
N
1
_
R
E
M
A
P
[
0
]
T
I
M
4
_
R
E
M
P
A
P
T
I
M
3
_
R
E
M
P
A
P
[
1
]
T
I
M
3
_
R
E
M
P
A
P
[
0
]
T
I
M
2
_
R
E
M
P
A
P
[
1
]
T
I
M
2
_
R
E
M
P
A
P
[
0
]
T
I
M
1
_
R
E
M
P
A
P
[
1
]
T
I
M
1
_
R
E
M
P
A
P
[
0
]
U
S
A
R
T
3
_
R
E
M
A
P
[
1
]
U
S
A
R
T
3
_
R
E
M
A
P
[
0
]
U
S
A
R
T
2
_
R
E
M
A
P
U
S
A
R
T
1
_
R
E
M
A
P
I
2
C
1
_
R
E
M
A
P
S
P
I
1
_
R
E
M
A
P
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x04
AFIO_MAPR
connectivity line
devices
R
e
s
e
r
v
e
d
P
T
P
_
P
P
S
_
R
E
M
A
P
T
I
M
2
I
T
R
1
_
I
R
E
M
A
P
S
P
I
3
_
R
E
M
A
P
R
e
s
e
r
v
e
d
S
W
J
_
C
F
G
[
2
]
S
W
J
_
C
F
G
[
1
]
S
W
J
_
C
F
G
[
0
]
M
I
I
_
R
M
I
I
_
S
E
L
C
A
N
2
_
R
E
M
A
P
E
T
H
_
R
E
M
A
P
R
e
s
e
r
v
e
d
T
I
M
5
C
H
4
_
I
R
E
M
A
P
P
D
0
1
_
R
E
M
A
P
C
A
N
1
_
R
E
M
A
P
[
1
]
C
A
N
1
_
R
E
M
A
P
[
0
]
T
I
M
4
_
R
E
M
P
A
P
T
I
M
3
_
R
E
M
P
A
P
[
1
]
T
I
M
3
_
R
E
M
P
A
P
[
0
]
T
I
M
2
_
R
E
M
P
A
P
[
1
]
T
I
M
2
_
R
E
M
P
A
P
[
0
]
T
I
M
1
_
R
E
M
P
A
P
[
1
]
T
I
M
1
_
R
E
M
P
A
P
[
0
]
U
S
A
R
T
3
_
R
E
M
A
P
[
1
]
U
S
A
R
T
3
_
R
E
M
A
P
[
0
]
U
S
A
R
T
2
_
R
E
M
A
P
U
S
A
R
T
1
_
R
E
M
A
P
I
2
C
1
_
R
E
M
A
P
S
P
I
1
_
R
E
M
A
P
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x08
AFIO_EXTICR1
Reserved
EXTI3[3:0] EXTI2[3:0] EXTI1[3:0] EXTI0[3:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x0C
AFIO_EXTICR2
Reserved
EXTI7[3:0] EXTI6[3:0] EXTI5[3:0] EXTI4[3:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs)
Doc ID 13902 Rev 13 189/1093

Refer to Table 3 on page 50 for the register boundary addresses.
0x10
AFIO_EXTICR3
Reserved
EXTI11[3:0] EXTI10[3:0] EXTI9[3:0] EXTI8[3:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x14
AFIO_EXTICR4
Reserved
EXTI15[3:0] EXTI14[3:0] EXTI13[3:0] EXTI12[3:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x1C
AFIO_MAPR2
Reserved
F
S
M
C
_
N
A
D
V
T
I
M
1
4
_
R
E
M
A
P
T
I
M
1
3
_
R
E
M
A
P
T
I
M
1
1
_
R
E
M
A
P
T
I
M
1
0
_
R
E
M
A
P
T
I
M
9
_
R
E
M
A
P
Reserved
Reset value 0 0 0 0 0 0
Table 60. AFIO register map and reset values (continued)
Offset Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9 8 7 6 5 4 3 2 1 0

Interrupts and events RM0008
190/1093 Doc ID 13902 Rev 13
10 Interrupts and events
Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx
microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx
microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
High-density devices are STM32F101xx and STM32F103xx microcontrollers where the
Flash memory density ranges between 256 and 512 Kbytes.
XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the
Flash memory density ranges between 768 Kbytes and 1 Mbyte.
Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
This Section applies to the whole STM32F10xxx family, unless otherwise specified.
10.1 Nested vectored interrupt controller (NVIC)
Features
68 (not including the sixteen Cortex-M3 interrupt lines)
16 programmable priority levels (4 bits of interrupt priority are used)
Low-latency exception and interrupt handling
Power management control
Implementation of System Control Registers
The NVIC and the processor core interface are closely coupled, which enables low latency
interrupt processing and efficient processing of late arriving interrupts.
All interrupts including the core exceptions are managed by the NVIC. For more information
on exceptions and NVIC programming, refer to STM32F10xxx Cortex-M3 programming
manual (see Related documents on page 1).
10.1.1 SysTick calibration value register
The SysTick calibration value is set to 9000, which gives a reference time base of 1 ms with
the SysTick clock set to 9 MHz (max HCLK/8).
10.1.2 Interrupt and exception vectors
Table 61 and Table 63 are the vector tables for connectivity line and other STM32F10xxx
devices, respectively.

Table 61. Vector table for connectivity line devices
P
o
s
i
t
i
o
n
P
r
i
o
r
i
t
y
Type of
priority
Acronym Description Address
- - - Reserved 0x0000_0000
-3 fixed Reset Reset 0x0000_0004
RM0008 Interrupts and events
Doc ID 13902 Rev 13 191/1093

-2 fixed NMI
Non maskable interrupt. The RCC
Clock Security System (CSS) is
linked to the NMI vector.
0x0000_0008
-1 fixed HardFault All class of fault 0x0000_000C
0 settable MemManage Memory management 0x0000_0010
1 settable BusFault Pre-fetch fault, memory access fault 0x0000_0014
2 settable UsageFault Undefined instruction or illegal state 0x0000_0018
- - - Reserved
0x0000_001C -
0x0000_002B
3 settable SVCall
System service call via SWI
instruction
0x0000_002C
4 settable Debug Monitor Debug Monitor 0x0000_0030
- - - Reserved 0x0000_0034
5 settable PendSV Pendable request for system service 0x0000_0038
6 settable SysTick System tick timer 0x0000_003C
0 7 settable WWDG Window Watchdog interrupt 0x0000_0040
1 8 settable PVD
PVD through EXTI Line detection
interrupt
0x0000_0044
2 9 settable TAMPER Tamper interrupt 0x0000_0048
3 10 settable RTC RTC global interrupt 0x0000_004C
4 11 settable FLASH Flash global interrupt 0x0000_0050
5 12 settable RCC RCC global interrupt 0x0000_0054
6 13 settable EXTI0 EXTI Line0 interrupt 0x0000_0058
7 14 settable EXTI1 EXTI Line1 interrupt 0x0000_005C
8 15 settable EXTI2 EXTI Line2 interrupt 0x0000_0060
9 16 settable EXTI3 EXTI Line3 interrupt 0x0000_0064
10 17 settable EXTI4 EXTI Line4 interrupt 0x0000_0068
11 18 settable DMA1_Channel1 DMA1 Channel1 global interrupt 0x0000_006C
12 19 settable DMA1_Channel2 DMA1 Channel2 global interrupt 0x0000_0070
13 20 settable DMA1_Channel3 DMA1 Channel3 global interrupt 0x0000_0074
14 21 settable DMA1_Channel4 DMA1 Channel4 global interrupt 0x0000_0078
15 22 settable DMA1_Channel5 DMA1 Channel5 global interrupt 0x0000_007C
16 23 settable DMA1_Channel6 DMA1 Channel6 global interrupt 0x0000_0080
17 24 settable DMA1_Channel7 DMA1 Channel7 global interrupt 0x0000_0084
18 25 settable ADC1_2 ADC1 and ADC2 global interrupt 0x0000_0088
Table 61. Vector table for connectivity line devices (continued)
P
o
s
i
t
i
o
n
P
r
i
o
r
i
t
y
Type of
priority
Acronym Description Address

Interrupts and events RM0008
192/1093 Doc ID 13902 Rev 13
19 26 settable CAN1_TX CAN1 TX interrupts 0x0000_008C
20 27 settable CAN1_RX0 CAN1 RX0 interrupts 0x0000_0090
21 28 settable CAN1_RX1 CAN1 RX1 interrupt 0x0000_0094
22 29 settable CAN1_SCE CAN1 SCE interrupt 0x0000_0098
23 30 settable EXTI9_5 EXTI Line[9:5] interrupts 0x0000_009C
24 31 settable TIM1_BRK TIM1 Break interrupt 0x0000_00A0
25 32 settable TIM1_UP TIM1 Update interrupt 0x0000_00A4
26 33 settable TIM1_TRG_COM
TIM1 Trigger and Commutation
interrupts
0x0000_00A8
27 34 settable TIM1_CC TIM1 Capture Compare interrupt 0x0000_00AC
28 35 settable TIM2 TIM2 global interrupt 0x0000_00B0
29 36 settable TIM3 TIM3 global interrupt 0x0000_00B4
30 37 settable TIM4 TIM4 global interrupt 0x0000_00B8
31 38 settable I2C1_EV I
2
C1 event interrupt 0x0000_00BC
32 39 settable I2C1_ER I
2
C1 error interrupt 0x0000_00C0
33 40 settable I2C2_EV I
2
C2 event interrupt 0x0000_00C4
34 41 settable I2C2_ER I
2
C2 error interrupt 0x0000_00C8
35 42 settable SPI1 SPI1 global interrupt 0x0000_00CC
36 43 settable SPI2 SPI2 global interrupt 0x0000_00D0
37 44 settable USART1 USART1 global interrupt 0x0000_00D4
38 45 settable USART2 USART2 global interrupt 0x0000_00D8
39 46 settable USART3 USART3 global interrupt 0x0000_00DC
40 47 settable EXTI15_10 EXTI Line[15:10] interrupts 0x0000_00E0
41 48 settable RTCAlarm
RTC alarm through EXTI line
interrupt
0x0000_00E4
42 49 settable OTG_FS_WKUP
USB On-The-Go FS Wakeup
through EXTI line interrupt
0x0000_00E8
- - - - Reserved
0x0000_00EC -
0x0000_0104
50 57 settable TIM5 TIM5 global interrupt 0x0000_0108
51 58 settable SPI3 SPI3 global interrupt 0x0000_010C
52 59 settable UART4 UART4 global interrupt 0x0000_0110
53 60 settable UART5 UART5 global interrupt 0x0000_0114
54 61 settable TIM6 TIM6 global interrupt 0x0000_0118
55 62 settable TIM7 TIM7 global interrupt 0x0000_011C
Table 61. Vector table for connectivity line devices (continued)
P
o
s
i
t
i
o
n
P
r
i
o
r
i
t
y
Type of
priority
Acronym Description Address
RM0008 Interrupts and events
Doc ID 13902 Rev 13 193/1093


56 63 settable DMA2_Channel1 DMA2 Channel1 global interrupt 0x0000_0120
57 64 settable DMA2_Channel2 DMA2 Channel2 global interrupt 0x0000_0124
58 65 settable DMA2_Channel3 DMA2 Channel3 global interrupt 0x0000_0128
59 66 settable DMA2_Channel4 DMA2 Channel4 global interrupt 0x0000_012C
60 67 settable DMA2_Channel5 DMA2 Channel5 global interrupt 0x0000_0130
61 68 settable ETH Ethernet global interrupt 0x0000_0134
62 69 settable ETH_WKUP
Ethernet Wakeup through EXTI line
interrupt
0x0000_0138
63 70 settable CAN2_TX CAN2 TX interrupts 0x0000_013C
64 71 settable CAN2_RX0 CAN2 RX0 interrupts 0x0000_0140
65 72 settable CAN2_RX1 CAN2 RX1 interrupt 0x0000_0144
66 73 settable CAN2_SCE CAN2 SCE interrupt 0x0000_0148
67 74 settable OTG_FS USB On The Go FS global interrupt 0x0000_014C
Table 62. Vector table for XL-density devices
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Type of
priority
Acronym Description Address
- - - Reserved 0x0000_0000
-3 fixed Reset Reset 0x0000_0004
-2 fixed NMI
Nonmaskable interrupt. The RCC
Clock Security System (CSS) is
linked to the NMI vector.
0x0000_0008
-1 fixed HardFault All class of fault 0x0000_000C
0 settable MemManage Memory management 0x0000_0010
1 settable BusFault Prefetch fault, memory access fault 0x0000_0014
2 settable UsageFault Undefined instruction or illegal state 0x0000_0018
- - - Reserved
0x0000_001C -
0x0000_002B
3 settable SVCall
System service call via SWI
instruction
0x0000_002C
4 settable Debug Monitor Debug monitor 0x0000_0030
- - - Reserved 0x0000_0034
5 settable PendSV Pendable request for system service 0x0000_0038
6 settable SysTick Systick timer 0x0000_003C
0 7 settable WWDG Window watchdog interrupt 0x0000_0040
Table 61. Vector table for connectivity line devices (continued)
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194/1093 Doc ID 13902 Rev 13
1 8 settable PVD
PVD through EXTI Line detection
interrupt
0x0000_0044
2 9 settable TAMPER Tamper interrupt 0x0000_0048
3 10 settable RTC RTC global interrupt 0x0000_004C
4 11 settable FLASH Flash global interrupt 0x0000_0050
5 12 settable RCC RCC global interrupt 0x0000_0054
6 13 settable EXTI0 EXTI Line0 interrupt 0x0000_0058
7 14 settable EXTI1 EXTI Line1 interrupt 0x0000_005C
8 15 settable EXTI2 EXTI Line2 interrupt 0x0000_0060
9 16 settable EXTI3 EXTI Line3 interrupt 0x0000_0064
10 17 settable EXTI4 EXTI Line4 interrupt 0x0000_0068
11 18 settable DMA1_Channel1 DMA1 Channel1 global interrupt 0x0000_006C
12 19 settable DMA1_Channel2 DMA1 Channel2 global interrupt 0x0000_0070
13 20 settable DMA1_Channel3 DMA1 Channel3 global interrupt 0x0000_0074
14 21 settable DMA1_Channel4 DMA1 Channel4 global interrupt 0x0000_0078
15 22 settable DMA1_Channel5 DMA1 Channel5 global interrupt 0x0000_007C
16 23 settable DMA1_Channel6 DMA1 Channel6 global interrupt 0x0000_0080
17 24 settable DMA1_Channel7 DMA1 Channel7 global interrupt 0x0000_0084
18 25 settable ADC1_2 ADC1 and ADC2 global interrupt 0x0000_0088
19 26 settable USB_HP_CAN_TX
USB high priority or CAN TX
interrupts
0x0000_008C
20 27 settable USB_LP_CAN_RX0
USB low priority or CAN RX0
interrupts
0x0000_0090
21 28 settable CAN_RX1 CAN RX1 interrupt 0x0000_0094
22 29 settable CAN_SCE CAN SCE interrupt 0x0000_0098
23 30 settable EXTI9_5 EXTI Line[9:5] interrupts 0x0000_009C
24 31 settable TIM1_BRK_TIM9
TIM1 Break interrupt and TIM9
global interrupt
0x0000_00A0
25 32 settable TIM1_UP_TIM10
TIM1 Update interrupt and TIM10
global interrupt
0x0000_00A4
26 33 settable TIM1_TRG_COM_TIM11
TIM1 Trigger and Commutation
interrupts and TIM11 global interrupt
0x0000_00A8
27 34 settable TIM1_CC TIM1 Capture Compare interrupt 0x0000_00AC
28 35 settable TIM2 TIM2 global interrupt 0x0000_00B0
29 36 settable TIM3 TIM3 global interrupt 0x0000_00B4
30 37 settable TIM4 TIM4 global interrupt 0x0000_00B8
Table 62. Vector table for XL-density devices (continued)
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Acronym Description Address
RM0008 Interrupts and events
Doc ID 13902 Rev 13 195/1093

31 38 settable I2C1_EV I2C1 event interrupt 0x0000_00BC
32 39 settable I2C1_ER I2C1 error interrupt 0x0000_00C0
33 40 settable I2C2_EV I2C2 event interrupt 0x0000_00C4
34 41 settable I2C2_ER I2C2 error interrupt 0x0000_00C8
35 42 settable SPI1 SPI1 global interrupt 0x0000_00CC
36 43 settable SPI2 SPI2 global interrupt 0x0000_00D0
37 44 settable USART1 USART1 global interrupt 0x0000_00D4
38 45 settable USART2 USART2 global interrupt 0x0000_00D8
39 46 settable USART3 USART3 global interrupt 0x0000_00DC
40 47 settable EXTI15_10 EXTI Line[15:10] interrupts 0x0000_00E0
41 48 settable RTCAlarm
RTC alarm through EXTI line
interrupt
0x0000_00E4
42 49 settable USBWakeUp
USB wakeup from suspend through
EXTI line interrupt
0x0000_00E8
43 50 settable TIM8_BRK_TIM12
TIM8 Break interrupt and TIM12
global interrupt
0x0000_00EC
44 51 settable TIM8_UP_TIM13
TIM8 Update interrupt and TIM13
global interrupt
0x0000_00F0
45 52 settable TIM8_TRG_COM_TIM14
TIM8 Trigger and Commutation
interrupts and TIM14 global interrupt
0x0000_00F4
46 53 settable TIM8_CC TIM8 Capture Compare interrupt 0x0000_00F8
47 54 settable ADC3 ADC3 global interrupt 0x0000_00FC
48 55 settable FSMC FSMC global interrupt 0x0000_0100
49 56 settable SDIO SDIO global interrupt 0x0000_0104
50 57 settable TIM5 TIM5 global interrupt 0x0000_0108
51 58 settable SPI3 SPI3 global interrupt 0x0000_010C
52 59 settable UART4 UART4 global interrupt 0x0000_0110
53 60 settable UART5 UART5 global interrupt 0x0000_0114
54 61 settable TIM6 TIM6 global interrupt 0x0000_0118
55 62 settable TIM7 TIM7 global interrupt 0x0000_011C
56 63 settable DMA2_Channel1 DMA2 Channel1 global interrupt 0x0000_0120
57 64 settable DMA2_Channel2 DMA2 Channel2 global interrupt 0x0000_0124
58 65 settable DMA2_Channel3 DMA2 Channel3 global interrupt 0x0000_0128
59 66 settable DMA2_Channel4_5
DMA2 Channel4 and DMA2
Channel5 global interrupts
0x0000_012C
Table 62. Vector table for XL-density devices (continued)
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Acronym Description Address

Interrupts and events RM0008
196/1093 Doc ID 13902 Rev 13

Table 63. Vector table for other STM32F10xxx devices
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Type of
priority
Acronym Description Address
- - - Reserved 0x0000_0000
-3 fixed Reset Reset 0x0000_0004
-2 fixed NMI
Non maskable interrupt. The RCC
Clock Security System (CSS) is
linked to the NMI vector.
0x0000_0008
-1 fixed HardFault All class of fault 0x0000_000C
0 settable MemManage Memory management 0x0000_0010
1 settable BusFault Prefetch fault, memory access fault 0x0000_0014
2 settable UsageFault Undefined instruction or illegal state 0x0000_0018
- - - Reserved
0x0000_001C -
0x0000_002B
3 settable SVCall
System service call via SWI
instruction
0x0000_002C
4 settable Debug Monitor Debug Monitor 0x0000_0030
- - - Reserved 0x0000_0034
5 settable PendSV Pendable request for system service 0x0000_0038
6 settable SysTick System tick timer 0x0000_003C
0 7 settable WWDG Window watchdog interrupt 0x0000_0040
1 8 settable PVD
PVD through EXTI Line detection
interrupt
0x0000_0044
2 9 settable TAMPER Tamper interrupt 0x0000_0048
3 10 settable RTC RTC global interrupt 0x0000_004C
4 11 settable FLASH Flash global interrupt 0x0000_0050
5 12 settable RCC RCC global interrupt 0x0000_0054
6 13 settable EXTI0 EXTI Line0 interrupt 0x0000_0058
7 14 settable EXTI1 EXTI Line1 interrupt 0x0000_005C
8 15 settable EXTI2 EXTI Line2 interrupt 0x0000_0060
9 16 settable EXTI3 EXTI Line3 interrupt 0x0000_0064
10 17 settable EXTI4 EXTI Line4 interrupt 0x0000_0068
11 18 settable DMA1_Channel1 DMA1 Channel1 global interrupt 0x0000_006C
12 19 settable DMA1_Channel2 DMA1 Channel2 global interrupt 0x0000_0070
13 20 settable DMA1_Channel3 DMA1 Channel3 global interrupt 0x0000_0074
14 21 settable DMA1_Channel4 DMA1 Channel4 global interrupt 0x0000_0078
15 22 settable DMA1_Channel5 DMA1 Channel5 global interrupt 0x0000_007C
16 23 settable DMA1_Channel6 DMA1 Channel6 global interrupt 0x0000_0080
RM0008 Interrupts and events
Doc ID 13902 Rev 13 197/1093

17 24 settable DMA1_Channel7 DMA1 Channel7 global interrupt 0x0000_0084
18 25 settable ADC1_2 ADC1 and ADC2 global interrupt 0x0000_0088
19 26 settable
USB_HP_CAN_
TX
USB High Priority or CAN TX
interrupts
0x0000_008C
20 27 settable
USB_LP_CAN_
RX0
USB Low Priority or CAN RX0
interrupts
0x0000_0090
21 28 settable CAN_RX1 CAN RX1 interrupt 0x0000_0094
22 29 settable CAN_SCE CAN SCE interrupt 0x0000_0098
23 30 settable EXTI9_5 EXTI Line[9:5] interrupts 0x0000_009C
24 31 settable TIM1_BRK TIM1 Break interrupt 0x0000_00A0
25 32 settable TIM1_UP TIM1 Update interrupt 0x0000_00A4
26 33 settable TIM1_TRG_COM
TIM1 Trigger and Commutation
interrupts
0x0000_00A8
27 34 settable TIM1_CC TIM1 Capture Compare interrupt 0x0000_00AC
28 35 settable TIM2 TIM2 global interrupt 0x0000_00B0
29 36 settable TIM3 TIM3 global interrupt 0x0000_00B4
30 37 settable TIM4 TIM4 global interrupt 0x0000_00B8
31 38 settable I2C1_EV I
2
C1 event interrupt 0x0000_00BC
32 39 settable I2C1_ER I
2
C1 error interrupt 0x0000_00C0
33 40 settable I2C2_EV I
2
C2 event interrupt 0x0000_00C4
34 41 settable I2C2_ER I
2
C2 error interrupt 0x0000_00C8
35 42 settable SPI1 SPI1 global interrupt 0x0000_00CC
36 43 settable SPI2 SPI2 global interrupt 0x0000_00D0
37 44 settable USART1 USART1 global interrupt 0x0000_00D4
38 45 settable USART2 USART2 global interrupt 0x0000_00D8
39 46 settable USART3 USART3 global interrupt 0x0000_00DC
40 47 settable EXTI15_10 EXTI Line[15:10] interrupts 0x0000_00E0
41 48 settable RTCAlarm
RTC alarm through EXTI line
interrupt
0x0000_00E4
42 49 settable USBWakeup
USB wakeup from suspend through
EXTI line interrupt
0x0000_00E8
43 50 settable TIM8_BRK TIM8 Break interrupt 0x0000_00EC
44 51 settable TIM8_UP TIM8 Update interrupt 0x0000_00F0
45 52 settable TIM8_TRG_COM
TIM8 Trigger and Commutation
interrupts
0x0000_00F4
46 53 settable TIM8_CC TIM8 Capture Compare interrupt 0x0000_00F8
Table 63. Vector table for other STM32F10xxx devices (continued)
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Interrupts and events RM0008
198/1093 Doc ID 13902 Rev 13
10.2 External interrupt/event controller (EXTI)
The external interrupt/event controller consists of up to 20 edge detectors in connectivity line
devices, or 19 edge detectors in other devices for generating event/interrupt requests. Each
input line can be independently configured to select the type (pulse or pending) and the
corresponding trigger event (rising or falling or both). Each line can also masked
independently. A pending register maintains the status line of the interrupt requests
10.2.1 Main features
The EXTI controller main features are the following:
Independent trigger and mask on each interrupt/event line
Dedicated status bit for each interrupt line
Generation of up to 20 software event/interrupt requests
Detection of external signal with pulse width lower than APB2 clock period. Refer to the
electrical characteristics section of the datasheet for details on this parameter.
10.2.2 Block diagram
The block diagram is shown in Figure 20.
47 54 settable ADC3 ADC3 global interrupt 0x0000_00FC
48 55 settable FSMC FSMC global interrupt 0x0000_0100
49 56 settable SDIO SDIO global interrupt 0x0000_0104
50 57 settable TIM5 TIM5 global interrupt 0x0000_0108
51 58 settable SPI3 SPI3 global interrupt 0x0000_010C
52 59 settable UART4 UART4 global interrupt 0x0000_0110
53 60 settable UART5 UART5 global interrupt 0x0000_0114
54 61 settable TIM6 TIM6 global interrupt 0x0000_0118
55 62 settable TIM7 TIM7 global interrupt 0x0000_011C
56 63 settable DMA2_Channel1 DMA2 Channel1 global interrupt 0x0000_0120
57 64 settable DMA2_Channel2 DMA2 Channel2 global interrupt 0x0000_0124
58 65 settable DMA2_Channel3 DMA2 Channel3 global interrupt 0x0000_0128
59 66 settable DMA2_Channel4_5
DMA2 Channel4 and DMA2
Channel5 global interrupts
0x0000_012C
Table 63. Vector table for other STM32F10xxx devices (continued)
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Acronym Description Address
RM0008 Interrupts and events
Doc ID 13902 Rev 13 199/1093

Figure 20. External interrupt/event controller block diagram
10.2.3 Wakeup event management
The STM32F10xxx is able to handle external or internal events in order to wake up the core
(WFE). The wakeup event can be generated either by:
enabling an interrupt in the peripheral control register but not in the NVIC, and enabling
the SEVONPEND bit in the Cortex-M3 System Control register. When the MCU
resumes from WFE, the peripheral interrupt pending bit and the peripheral NVIC IRQ
channel pending bit (in the NVIC interrupt clear pending register) have to be cleared.
or configuring an external or internal EXTI line in event mode. When the CPU resumes
from WFE, it is not necessary to clear the peripheral interrupt pending bit or the NVIC
IRQ channel pending bit as the pending bit corresponding to the event line is not set.
In connectivity line devices, Ethernet wakeup events also have the WFE wakeup capability.
To use an external line as a wakeup event, refer to Section 10.2.4: Functional description.
10.2.4 Functional description
To generate the interrupt, the interrupt line should be configured and enabled. This is done
by programming the two trigger registers with the desired edge detection and by enabling
the interrupt request by writing a 1 to the corresponding bit in the interrupt mask register.
When the selected edge occurs on the external interrupt line, an interrupt request is
generated. The pending bit corresponding to the interrupt line is also set. This request is
reset by writing a 1 in the pending register.
To generate the event, the event line should be configured and enabled. This is done by
programming the two trigger registers with the desired edge detection and by enabling the
trigger
selection
Peripheral interface
mask
register
Edge detect
AMBA APB bus
PCLK2
19
19 19 19 19
circuit
Pending
register
interrupt
request
.
19
19
To NVIC Interrupt
Software
Controller
trigger
selection
Rising Falling
19
Event
mask
Pulse
generator
19
19
19 19
Input
Line
Interrupt
register register
register
19
19
event
register
ai15801

Interrupts and events RM0008
200/1093 Doc ID 13902 Rev 13
event request by writing a 1 to the corresponding bit in the event mask register. When the
selected edge occurs on the event line, an event pulse is generated. The pending bit
corresponding to the event line is not set
An interrupt/event request can also be generated by software by writing a 1 in the software
interrupt/event register.
Hardware interrupt selection
To configure the 20 lines as interrupt sources, use the following procedure:
Configure the mask bits of the 20 Interrupt lines (EXTI_IMR)
Configure the Trigger Selection bits of the Interrupt lines (EXTI_RTSR and
EXTI_FTSR)
Configure the enable and mask bits that control the NVIC IRQ channel mapped to the
External Interrupt Controller (EXTI) so that an interrupt coming from one of the 20 lines
can be correctly acknowledged.
Hardware event selection
To configure the 20 lines as event sources, use the following procedure:
Configure the mask bits of the 20 Event lines (EXTI_EMR)
Configure the Trigger Selection bits of the Event lines (EXTI_RTSR and EXTI_FTSR)
Software interrupt/event selection
The 20 lines can be configured as software interrupt/event lines. The following is the
procedure to generate a software interrupt.
Configure the mask bits of the 20 Interrupt/Event lines (EXTI_IMR, EXTI_EMR)
Set the required bit of the software interrupt register (EXTI_SWIER)
10.2.5 External interrupt/event line mapping
The 112 GPIOs are connected to the 16 external interrupt/event lines in the following
manner:
RM0008 Interrupts and events
Doc ID 13902 Rev 13 201/1093

Figure 21. External interrupt/event GPIO mapping
1. To configure the AFIO_EXTICRx for the mapping of external interrupt/event lines onto GPIOs, the AFIO
clock should first be enabled. Refer to Section 7.3.7: APB2 peripheral clock enable register
(RCC_APB2ENR) for low-, medium-, high- and XL-density devices and, to Section 8.3.7: APB2 peripheral
clock enable register (RCC_APB2ENR) for connectivity line devices.
The four other EXTI lines are connected as follows:
EXTI line 16 is connected to the PVD output
EXTI line 17 is connected to the RTC Alarm event
EXTI line 18 is connected to the USB Wakeup event
EXTI line 19 is connected to the Ethernet Wakeup event (available only in connectivity
line devices)
EXTI0
PA0
PB0
PC0
PD0
PE0
EXTI0[3:0] bits in AFIO_EXTICR1 register
PF0
PG0
EXTI1
PA1
PB1
PC1
PD1
PE1
EXTI1[3:0] bits in AFIO_EXTICR1 register
PF1
PG1
EXTI15
PA15
PB15
PC15
PD15
PE15
EXTI15[3:0] bits in AFIO_EXTICR4 register
PF15
PG15

Interrupts and events RM0008
202/1093 Doc ID 13902 Rev 13
10.3 EXTI registers
Refer to Section 2.1 on page 46 for a list of abbreviations used in register descriptions.
The peripheral registers have to be accessed by words (32-bit).
10.3.1 Interrupt mask register (EXTI_IMR)
Address offset: 0x00
Reset value: 0x0000 0000


10.3.2 Event mask register (EXTI_EMR)
Address offset: 0x04
Reset value: 0x0000 0000


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
MR19 MR18 MR17 MR16
rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MR15 MR14 MR13 MR12 MR11 MR10 MR9 MR8 MR7 MR6 MR5 MR4 MR3 MR2 MR1 MR0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:20 Reserved, must be kept at reset value (0).
Bits 19:0 MRx: Interrupt Mask on line x
0: Interrupt request from Line x is masked
1: Interrupt request from Line x is not masked
Note: Bit 19 is used in connectivity line devices only and is reserved otherwise.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
MR19 MR18 MR17 MR16
rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MR15 MR14 MR13 MR12 MR11 MR10 MR9 MR8 MR7 MR6 MR5 MR4 MR3 MR2 MR1 MR0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:20 Reserved, must be kept at reset value (0).
Bits 19:0 MRx: Event mask on line x
0: Event request from Line x is masked
1: Event request from Line x is not masked
Note: Bit 19 is used in connectivity line devices only and is reserved otherwise.
RM0008 Interrupts and events
Doc ID 13902 Rev 13 203/1093

10.3.3 Rising trigger selection register (EXTI_RTSR)
Address offset: 0x08
Reset value: 0x0000 0000


Note: The external wakeup lines are edge triggered, no glitches must be generated on these lines.
If a rising edge on external interrupt line occurs during writing of EXTI_RTSR register, the
pending bit will not be set.
Rising and Falling edge triggers can be set for the same interrupt line. In this configuration,
both generate a trigger condition.
10.3.4 Falling trigger selection register (EXTI_FTSR)
Address offset: 0x0C
Reset value: 0x0000 0000


Note: The external wakeup lines are edge triggered, no glitches must be generated on these lines.
If a falling edge on external interrupt line occurs during writing of EXTI_FTSR register, the
pending bit will not be set.
Rising and Falling edge triggers can be set for the same interrupt line. In this configuration,
both generate a trigger condition.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
TR19 TR18 TR17 TR16
rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TR15 TR14 TR13 TR12 TR11 TR10 TR9 TR8 TR7 TR6 TR5 TR4 TR3 TR2 TR1 TR0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:20 Reserved, must be kept at reset value (0).
Bits 19:0 TRx: Rising trigger event configuration bit of line x
0: Rising trigger disabled (for Event and Interrupt) for input line
1: Rising trigger enabled (for Event and Interrupt) for input line.
Note: Bit 19 is used in connectivity line devices only and is reserved otherwise.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
TR19 TR18 TR17 TR16
rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TR15 TR14 TR13 TR12 TR11 TR10 TR9 TR8 TR7 TR6 TR5 TR4 TR3 TR2 TR1 TR0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:20 Reserved, must be kept at reset value (0).
Bits 19:0 TRx: Falling trigger event configuration bit of line x
0: Falling trigger disabled (for Event and Interrupt) for input line
1: Falling trigger enabled (for Event and Interrupt) for input line.
Note: Bit 19 used in connectivity line devices and is reserved otherwise.

Interrupts and events RM0008
204/1093 Doc ID 13902 Rev 13
10.3.5 Software interrupt event register (EXTI_SWIER)
Address offset: 0x10
Reset value: 0x0000 0000


10.3.6 Pending register (EXTI_PR)
Address offset: 0x14
Reset value: undefined


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
SWIER
19
SWIER
18
SWIER
17
SWIER
16
rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWIER
15
SWIER
14
SWIER
13
SWIER
12
SWIER
11
SWIER
10
SWIER
9
SWIER
8
SWIER
7
SWIER
6
SWIER
5
SWIER
4
SWIER
3
SWIER
2
SWIER
1
SWIER
0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:20 Reserved, must be kept at reset value (0).
Bits 19:0 SWIERx: Software interrupt on line x
Writing a 1 to this bit when it is at 0 sets the corresponding pending bit in EXTI_PR. If the
interrupt is enabled on this line on the EXTI_IMR and EXTI_EMR, an interrupt request is
generated.
This bit is cleared by clearing the corresponding bit of EXTI_PR (by writing a 1 into the bit).
Note: Bit 19 used in connectivity line devices and is reserved otherwise.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
PR19 PR18 PR17 PR16
rc_w1 rc_w1 rc_w1 rc_w1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PR15 PR14 PR13 PR12 PR11 PR10 PR9 PR8 PR7 PR6 PR5 PR4 PR3 PR2 PR1 PR0
rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1
Bits 31:20 Reserved, must be kept at reset value (0).
Bits 19:0 PRx: Pending bit
0: No trigger request occurred
1: selected trigger request occurred
This bit is set when the selected edge event arrives on the external interrupt line. This bit is
cleared by writing a 1 into the bit or by changing the sensitivity of the edge detector.
Note: Bit 19 is used in connectivity line devices only and is reserved otherwise.
RM0008 Interrupts and events
Doc ID 13902 Rev 13 205/1093

10.3.7 EXTI register map
The following table gives the EXTI register map and the reset values. Bits 19 in all registers,
are used in connectivity line devices and is reserved otherwise.

Refer to Table 3 on page 50 for the register boundary addresses.
Table 64. External interrupt/event controller register map and reset values
Offset Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9 8 7 6 5 4 3 2 1 0
0x00
EXTI_IMR
Reserved
MR[19:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x04
EXTI_EMR
Reserved
MR[19:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x08
EXTI_RTSR
Reserved
TR[19:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x0C
EXTI_FTSR
Reserved
TR[19:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x10
EXTI_SWIER
Reserved
SWIER[19:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x14
EXTI_PR
Reserved
PR[19:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Analog-to-digital converter (ADC) RM0008
206/1093 Doc ID 13902 Rev 13
11 Analog-to-digital converter (ADC)
Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx
microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx
microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
High-density devices are STM32F101xx and STM32F103xx microcontrollers where the
Flash memory density ranges between 256 and 512 Kbytes.
XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the
Flash memory density ranges between 768 Kbytes and 1 Mbyte.
Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
This Section applies to the whole STM32F10xxx family, unless otherwise specified.
11.1 ADC introduction
The 12-bit ADC is a successive approximation analog-to-digital converter. It has up to 18
multiplexed channels allowing it measure signals from 16 external and two internal sources.
A/D conversion of the various channels can be performed in single, continuous, scan or
discontinuous mode. The result of the ADC is stored in a left-aligned or right-aligned 16-bit
data register.
The analog watchdog feature allows the application to detect if the input voltage goes
outside the user-defined high or low thresholds.
The ADC input clock is generated from the PCLK2 clock divided by a prescaler and it must
not exceed 14 MHz, refer to Figure 8: Clock tree for low-, medium-, high- and XL-density
devices, and to Figure 11: Clock tree for connectivity line devices.
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11.2 ADC main features
12-bit resolution
Interrupt generation at End of Conversion, End of Injected conversion and Analog
watchdog event
Single and continuous conversion modes
Scan mode for automatic conversion of channel 0 to channel n
Self-calibration
Data alignment with in-built data coherency
Channel by channel programmable sampling time
External trigger option for both regular and injected conversion
Discontinuous mode
Dual mode (on devices with 2 ADCs or more)
ADC conversion time:
STM32F103xx performance line devices: 1 s at 56 MHz (1.17 s at 72 MHz)
STM32F101xx access line devices: 1 s at 28 MHz (1.55 s at 36 MHz)
STM32F102xx USB access line devices: 1.2 s at 48 MHz
STM32F105xx and STM32F107xx devices: 1 s at 56 MHz (1.17 s at 72 MHz)
ADC supply requirement: 2.4 V to 3.6 V
ADC input range: V
REF-
V
IN
V
REF+
DMA request generation during regular channel conversion
The block diagram of the ADC is shown in Figure 22.
Note: V
REF-
,if available (depending on package), must be tied to V
SSA
.
11.3 ADC functional description
Figure 22 shows a single ADC block diagramand Table 65 gives the ADC pin description.
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208/1093 Doc ID 13902 Rev 13
Figure 22. Single ADC block diagram
1. ADC3 has regular and injected conversion triggers different from those of ADC1 and ADC2.
2. TIM8_CH4 and TIM8_TRGO with their corresponding remap bits exist only in High-density and XL-density
products.
ADCx_IN0
ADCx_IN1
Analog to digital
converter
ADCx_IN15
Analog
MUX
ADCCLK
ADC Interrupt to NVIC
GPIO
Ports
Analog watchdog
A
d
d
r
e
s
s
/
d
a
t
a

b
u
s
Low Threshold (12 bits)
Compare Result
High Threshold (12 bits)
Flags enable bits
EOC
AWD
Analog watchdog event
V
DDA
V
SSA
V
REF+
V
REF-
Interrupt
TIM1_CH2
TIM1_CH3
TIM2_CH2
TIM3_CH4
From ADC prescaler
(16 bits)
End of conversion
channels
Injected
channels
End of injected conversion
JEOC
EOCIE
AWDIE
JEOCIE
up to 4
up to 16
Regular data register
(4 x 16 bits)
Injected data registers
Regular
Start trigger
(regular group)
EXTSEL[2:0] bits
EXTRI G
TIM1_CH1
TIM4_TRGO
EXTI_15
TIM1_CH4
TIM2_TRGO
TIM2_CH1
TIM3_TRGO
Start trigger
(injected group)
JEXTSEL[2:0] bits
TIM1_TRGO
TIM4_CH4
JEXTRIG
bit
bit
DMA request
Temp. sensor
V
REFINT
TIM2_CH3
TIM1_CH3
TIM8_CH1
TIM8_CH4
TIM3_CH1
TIM5_TRGO
TIM1_CH4
TIM4_CH3
TIM8_CH2
TIM8_TRGO
JEXTSEL[2:0] bits
TIM1_TRGO
TIM5_CH1
Triggers for ADC3
(1)
Start trigger
(injected group)
JEXTRIG
bit
Start trigger
(regular group)
EXTRIG
bit
EXTSEL[2:0] bits
TIM5_CH4
TIM5_CH3
EXTI_11
TIM8_TRGO
(2)
ADCx_ETRGREG_REMAP bit
TIM8_CH4
(2)
ADCx-ETRGINJ_REMAP bit
ai14802d
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Table 65. ADC pins
Name Signal type Remarks
V
REF+
Input, analog reference
positive
The higher/positive reference voltage for the ADC,
2.4 V V
REF+
V
DDA
V
DDA
(1)
1. V
DDA
and V
SSA
have to be connected to V
DD
and V
SS
, respectively.
Input, analog supply
Analog power supply equal to V
DD
and
2.4 V V
DDA
3.6 V
V
REF-
Input, analog reference
negative
The lower/negative reference voltage for the ADC,
V
REF-
=

V
SSA
V
SSA
(1)
Input, analog supply
ground
Ground for analog power supply equal to V
SS
ADCx_IN[15:0] Analog signals Up to 21 analog channels
(2)
2. For full details about the ADC I/O pins, please refer to the Pinouts and pin descriptions section of the
corresponding device datasheet.
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11.3.1 ADC on-off control
The ADC can be powered-on by setting the ADON bit in the ADC_CR2 register. When the
ADON bit is set for the first time, it wakes up the ADC from Power Down mode.
Conversion starts when ADON bit is set for a second time by software after ADC power-up
time (t
STAB
).
You can stop conversion and put the ADC in power down mode by resetting the ADON bit. In
this mode the ADC consumes almost no power (only a few A).
11.3.2 ADC clock
The ADCCLK clock provided by the Clock Controller is synchronous with the PCLK2 (APB2
clock). The RCC controller has a dedicated programmable prescaler for the ADC clock (refer
to Low-, medium-, high- and XL-density reset and clock control (RCC) on page 87for more
details.
11.3.3 Channel selection
There are 16 multiplexed channels. It is possible to organize the conversions in two groups:
regular and injected. A group consists of a sequence of conversions which can be done on
any channel and in any order. For instance, it is possible to do the conversion in the
following order: Ch3, Ch8, Ch2, Ch2, Ch0, Ch2, Ch2, Ch15.
The regular group is composed of up to 16 conversions. The regular channels and
their order in the conversion sequence must be selected in the ADC_SQRx registers.
The total number of conversions in the regular group must be written in the L[3:0] bits in
the ADC_SQR1 register.
The injected group is composed of up to 4 conversions. The injected channels and
their order in the conversion sequence must be selected in the ADC_JSQR register.
The total number of conversions in the injected group must be written in the L[1:0] bits
in the ADC_JSQR register.
If the ADC_SQRx or ADC_JSQR registers are modified during a conversion, the current
conversion is reset and a new start pulse is sent to the ADC to convert the new chosen
group.
Temperature sensor/V
REFINT
internal channels
The Temperature sensor is connected to channel ADCx_IN16 and the internal reference
voltage V
REFINT
is connected to ADCx_IN17. These two internal channels can be selected
and converted as injected or regular channels.
Note: The sensor and V
REFINT
are only available on the master ADC1 peripheral.
11.3.4 Single conversion mode
In Single conversion mode the ADC does one conversion. This mode is started either by
setting the ADON bit in the ADC_CR2 register (for a regular channel only) or by external
trigger (for a regular or injected channel), while the CONT bit is 0.
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Once the conversion of the selected channel is complete:
If a regular channel was converted:
The converted data is stored in the 16-bit ADC_DR register
The EOC (End Of Conversion) flag is set
and an interrupt is generated if the EOCIE is set.
If an injected channel was converted:
The converted data is stored in the 16-bit ADC_DRJ1 register
The JEOC (End Of Conversion Injected) flag is set
and an interrupt is generated if the JEOCIE bit is set.
The ADC is then stopped.
11.3.5 Continuous conversion mode
In continuous conversion mode ADC starts another conversion as soon as it finishes one.
This mode is started either by external trigger or by setting the ADON bit in the ADC_CR2
register, while the CONT bit is 1.
After each conversion:
If a regular channel was converted:
The converted data is stored in the 16-bit ADC_DR register
The EOC (End Of Conversion) flag is set
An interrupt is generated if the EOCIE is set.
If an injected channel was converted:
The converted data is stored in the 16-bit ADC_DRJ1 register
The JEOC (End Of Conversion Injected) flag is set
An interrupt is generated if the JEOCIE bit is set.
11.3.6 Timing diagram
As shown in Figure 23, the ADC needs a stabilization time of t
STAB
before it starts
converting accurately. After the start of ADC conversion and after 14 clock cycles, the EOC
flag is set and the 16-bit ADC Data register contains the result of the conversion.
Figure 23. Timing diagram
ADC_CLK
EOC
Next ADC Conversion ADC Conversion
Conversion Time
t
STAB
ADC
Software resets EOC bit
SET ADON
ADC power on
(total conv time)
Start 1st conversion Start next conversion
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11.3.7 Analog watchdog
The AWD analog watchdog status bit is set if the analog voltage converted by the ADC is
below a low threshold or above a high threshold. These thresholds are programmed in the
12 least significant bits of the ADC_HTR and ADC_LTR 16-bit registers. An interrupt can be
enabled by using the AWDIE bit in the ADC_CR1 register.
The threshold value is independent of the alignment selected by the ALIGN bit in the
ADC_CR2 register. The comparison is done before the alignment (see Section 11.5).
The analog watchdog can be enabled on one or more channels by configuring the
ADC_CR1 register as shown in Table 66.
Figure 24. Analog watchdog guarded area

11.3.8 Scan mode
This mode is used to scan a group of analog channels.
Scan mode can be selected by setting the SCAN bit in the ADC_CR1 register. Once this bit
is set, ADC scans all the channels selected in the ADC_SQRx registers (for regular
channels) or in the ADC_JSQR (for injected channels). A single conversion is performed for
each channel of the group. After each end of conversion the next channel of the group is
converted automatically. If the CONT bit is set, conversion does not stop at the last selected
group channel but continues again from the first selected group channel.
If the DMA bit is set, the direct memory access controller is used to transfer the converted
data of regular group channels to SRAM after each EOC.
The injected channel converted data is always stored in the ADC_JDRx registers.
Table 66. Analog watchdog channel selection
Channels to be guarded by analog
watchdog
ADC_CR1 register control bits (x = dont care)
AWDSGL bit AWDEN bit JAWDEN bit
None x 0 0
All injected channels 0 0 1
All regular channels 0 1 0
All regular and injected channels 0 1 1
Single
(1)
injected channel
1. Selected by AWDCH[4:0] bits
1 0 1
Single
(1)
regular channel 1 1 0
Single
(1)
regular or injected channel 1 1 1
Analog voltage
High threshold
Low threshold
Guarded area
HTR
LTR
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11.3.9 Injected channel management
Triggered injection
To use triggered injection, the JAUTO bit must be cleared and SCAN bit must be set in the
ADC_CR1 register.
1. Start conversion of a group of regular channels either by external trigger or by setting
the ADON bit in the ADC_CR2 register.
2. If an external injected trigger occurs during the regular group channel conversion, the
current conversion is reset and the injected channel sequence is converted in Scan
once mode.
3. Then, the regular group channel conversion is resumed from the last interrupted
regular conversion. If a regular event occurs during an injected conversion, it doesnt
interrupt it but the regular sequence is executed at the end of the injected sequence.
Figure 25 shows the timing diagram.
Note: When using triggered injection, one must ensure that the interval between trigger events is
longer than the injection sequence. For instance, if the sequence length is 28 ADC clock
cycles (that is two conversions with a 1.5 clock-period sampling time), the minimum interval
between triggers must be 29 ADC clock cycles.
Auto-injection
If the JAUTO bit is set, then the injected group channels are automatically converted after
the regular group channels. This can be used to convert a sequence of up to 20 conversions
programmed in the ADC_SQRx and ADC_JSQR registers.
In this mode, external trigger on injected channels must be disabled.
If the CONT bit is also set in addition to the JAUTO bit, regular channels followed by injected
channels are continuously converted.
For ADC clock prescalers ranging from 4 to 8, a delay of 1 ADC clock period is automatically
inserted when switching from regular to injected sequence (respectively injected to regular).
When the ADC clock prescaler is set to 2, the delay is 2 ADC clock periods.
Note: It is not possible to use both auto-injected and discontinuous modes simultaneously.
Figure 25. Injected conversion latency
1. The maximum latency value can be found in the electrical characteristics of the STM32F101xx and
STM32F103xx datasheets.
ADC clock
Inj. event
Reset ADC
SOC
max latency
(1)
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11.3.10 Discontinuous mode
Regular group
This mode is enabled by setting the DISCEN bit in the ADC_CR1 register. It can be used to
convert a short sequence of n conversions (n <=8) which is a part of the sequence of
conversions selected in the ADC_SQRx registers. The value of n is specified by writing to
the DISCNUM[2:0] bits in the ADC_CR1 register.
When an external trigger occurs, it starts the next n conversions selected in the ADC_SQRx
registers until all the conversions in the sequence are done. The total sequence length is
defined by the L[3:0] bits in the ADC_SQR1 register.
Example:
n = 3, channels to be converted = 0, 1, 2, 3, 6, 7, 9, 10
1st trigger: sequence converted 0, 1, 2
2nd trigger: sequence converted 3, 6, 7
3rd trigger: sequence converted 9, 10 and an EOC event generated
4th trigger: sequence converted 0, 1, 2
Note: When a regular group is converted in discontinuous mode, no rollover will occur. When all
sub groups are converted, the next trigger starts conversion of the first sub-group.
In the example above, the 4th trigger reconverts the 1st sub-group channels 0, 1 and 2.
Injected group
This mode is enabled by setting the JDISCEN bit in the ADC_CR1 register. It can be used to
convert the sequence selected in the ADC_JSQR register, channel by channel, after an
external trigger event.
When an external trigger occurs, it starts the next channel conversions selected in the
ADC_JSQR registers until all the conversions in the sequence are done. The total sequence
length is defined by the JL[1:0] bits in the ADC_JSQR register.
Example:
n = 1, channels to be converted = 1, 2, 3
1st trigger: channel 1 converted
2nd trigger: channel 2 converted
3rd trigger: channel 3 converted and EOC and JEOC events generated
4th trigger: channel 1
Note: 1 When all injected channels are converted, the next trigger starts the conversion of the first
injected channel. In the example above, the 4th trigger reconverts the 1st injected channel
1.
2 It is not possible to use both auto-injected and discontinuous modes simultaneously.
3 The user must avoid setting discontinuous mode for both regular and injected groups
together. Discontinuous mode must be enabled only for one group conversion.
11.4 Calibration
The ADC has an built-in self calibration mode. Calibration significantly reduces accuracy
errors due to internal capacitor bank variations. During calibration, an error-correction code
(digital word) is calculated for each capacitor, and during all subsequent conversions, the
error contribution of each capacitor is removed using this code.
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Calibration is started by setting the CAL bit in the ADC_CR2 register. Once calibration is
over, the CAL bit is reset by hardware and normal conversion can be performed. It is
recommended to calibrate the ADC once at power-on. The calibration codes are stored in
the ADC_DR as soon as the calibration phase ends.
Note: 1 It is recommended to perform a calibration after each power-up.
2 Before starting a calibration the ADC must have been in power-off state (ADON bit = 0) for
at least two ADC clock cycles.
Figure 26. Calibration timing diagram
11.5 Data alignment
ALIGN bit in the ADC_CR2 register selects the alignment of data stored after conversion.
Data can be left or right aligned as shown in Figure 27. and Figure 28.
The injected group channels converted data value is decreased by the user-defined offset
written in the ADC_JOFRx registers so the result can be a negative value. The SEXT bit is
the extended sign value.
For regular group channels no offset is subtracted so only twelve bits are significant.
Figure 27. Right alignment of data
Figure 28. Left alignment of data
CLK
t
CAL
Calibration ongoing
CAL
ADC
Conversion
Normal ADC Conversion
Calibration Reset by Hardware
D7 D8 D9 D6 D5 D4 D3 D2 D1 D0 D10 D11 SEXT SEXT SEXT SEXT
D7 D8 D9 D6 D5 D4 D3 D2 D1 D0 D10 D11
Injected group
Regular group
0 0 0 0
SEXT D0 D1 D11 D10 D9 D8 D7 D6 D5 D2 D3 D4 0 0 0
D0 D1 D11 D10 D9 D8 D7 D6 D5 D2 D3 D4 0 0 0 0
Injected group
Regular group
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11.6 Channel-by-channel programmable sample time
ADC samples the input voltage for a number of ADC_CLK cycles which can be modified us-
ing the SMP[2:0] bits in the ADC_SMPR1 and ADC_SMPR2 registers. Each channel can be
sampled with a different sample time.
The total conversion time is calculated as follows:
Tconv = Sampling time + 12.5 cycles
Example:
With an ADCCLK = 14 MHz and a sampling time of 1.5 cycles:
Tconv = 1.5 + 12.5 = 14 cycles = 1 s
11.7 Conversion on external trigger
Conversion can be triggered by an external event (e.g. timer capture, EXTI line). If the EXT-
TRIG control bit is set then external events are able to trigger a conversion. The EXT-
SEL[2:0] and JEXTSEL[2:0] control bits allow the application to select decide which out of 8
possible events can trigger conversion for the regular and injected groups.
Note: When an external trigger is selected for ADC regular or injected conversion, only the rising
edge of the signal can start the conversion.

Table 67. External trigger for regular channels for ADC1 and ADC2
Source Type EXTSEL[2:0]
TIM1_CC1 event
Internal signal from on-chip
timers
000
TIM1_CC2 event 001
TIM1_CC3 event 010
TIM2_CC2 event 011
TIM3_TRGO event 100
TIM4_CC4 event 101
EXTI line 11/TIM8_TRGO
event
(1)(2)
1. The TIM8_TRGO event exists only in high-density and XL-density devices.
2. The selection of the external trigger EXTI line11 or TIM8_TRGO event for regular channels is done through
configuration bits ADC1_ETRGREG_REMAP and ADC2_ETRGREG_REMAP for ADC1 and ADC2,
respectively.
External pin/Internal signal from
on-chip timers
110
SWSTART Software control bit 111
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Table 68. External trigger for injected channels for ADC1 and ADC2
Source Connection type JEXTSEL[2:0]
TIM1_TRGO event
Internal signal from on-chip
timers
000
TIM1_CC4 event 001
TIM2_TRGO event 010
TIM2_CC1 event 011
TIM3_CC4 event 100
TIM4_TRGO event 101
EXTI line 15/TIM8_CC4
event
(1)(2)
1. The TIM8_CC4 event exists only in high-density and XL-density devices.
2. The selection of the external trigger EXTI line15 or TIM8_CC4 event for injected channels is done through
configuration bits ADC1_ETRGINJ_REMAP and ADC2_ETRGINJ_REMAP for ADC1 and ADC2,
respectively.
External pin/Internal signal from
on-chip timers
110
JSWSTART Software control bit 111
Table 69. External trigger for regular channels for ADC3
Source Connection type EXTSEL[2:0]
TIM3_CC1 event
Internal signal from on-chip
timers
000
TIM2_CC3 event 001
TIM1_CC3 event 010
TIM8_CC1 event 011
TIM8_TRGO event 100
TIM5_CC1 event 101
TIM5_CC3 event 110
SWSTART Software control bit 111
Table 70. External trigger for injected channels for ADC3
Source Connection type JEXTSEL[2:0]
TIM1_TRGO event
Internal signal from on-chip
timers
000
TIM1_CC4 event 001
TIM4_CC3 event 010
TIM8_CC2 event 011
TIM8_CC4 event 100
TIM5_TRGO event 101
TIM5_CC4 event 110
JSWSTART Software control bit 111
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The software source trigger events can be generated by setting a bit in a register
(SWSTART and JSWSTART in ADC_CR2).
A regular group conversion can be interrupted by an injected trigger.
11.8 DMA request
Since converted regular channels value are stored in a unique data register, it is necessary
to use DMA for conversion of more than one regular channel. This avoids the loss of data
already stored in the ADC_DR register.
Only the end of conversion of a regular channel generates a DMA request, which allows the
transfer of its converted data from the ADC_DR register to the destination location selected
by the user.
Note: Only ADC1 and ADC3 have this DMA capability. ADC2-converted data can be transferred in
dual ADC mode using DMA thanks to master ADC1.
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11.9 Dual ADC mode
In devices with two ADCs or more, dual ADC mode can be used (see Figure 29).
In dual ADC mode the start of conversion is triggered alternately or simultaneously by the
ADC1 master to the ADC2 slave, depending on the mode selected by the DUALMOD[2:0]
bits in the ADC1_CR1 register.
Note: In dual mode, when configuring conversion to be triggered by an external event, the user
must set the trigger for the master only and set a software trigger for the slave to prevent
spurious triggers to start unwanted slave conversion. However, external triggers must be
enabled on both master and slave ADCs.
The following six possible modes are implemented:
Injected simultaneous mode
Regular simultaneous mode
Fast interleaved mode
Slow interleaved mode
Alternate trigger mode
Independent mode
It is also possible to use the previous modes combined in the following ways:
Injected simultaneous mode + Regular simultaneous mode
Regular simultaneous mode + Alternate trigger mode
Injected simultaneous mode + Interleaved mode
Note: In dual ADC mode, to read the slave converted data on the master data register, the DMA
bit must be enabled even if it is not used to transfer converted regular channel data.
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Figure 29. Dual ADC block diagram
(1)
1. External triggers are present on ADC2 but are not shown for the purposes of this diagram.
2. In some dual ADC modes, the ADC1 data register (ADC1_DR) contains both ADC1 and ADC2 regular converted data over
the entire 32 bits.
ADCx_IN0
ADCx_IN1
ADCx_IN15
GPIO
Ports
A
d
d
r
e
s
s
/
d
a
t
a

b
u
s
EXTI_11
EXTI_15
Injected data registers
(4 x 16 bits)
Regular
channels
Injected
channels
ADC2 (Slave)
(12 bits)
Injected data registers
(4 x 16 bits)
Regular
channels
injected
channels
ADC1 (Master)
Dual mode
internal triggers
Start trigger mux
(regular group)
(injected group)
Start trigger mux
control
Temp. sensor
V
REFINT
Regular data register
(16 bits)
Regular data register
(16 bits)
(2)
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11.9.1 Injected simultaneous mode
This mode converts an injected channel group. The source of external trigger comes from
the injected group mux of ADC1 (selected by the JEXTSEL[2:0] bits in the ADC1_CR2
register). A simultaneous trigger is provided to ADC2.
Note: Do not convert the same channel on the two ADCs (no overlapping sampling times for the
two ADCs when converting the same channel).
At the end of conversion event on ADC1 or ADC2:
The converted data is stored in the ADC_JDRx registers of each ADC interface.
An JEOC interrupt is generated (if enabled on one of the two ADC interfaces) when the
ADC1/ADC2 injected channels are all converted.
Note: In simultaneous mode, one must convert sequences with the same length or ensure that the
interval between triggers is longer than the longest of the 2 sequences. Otherwise, the ADC
with the shortest sequence may restart while the ADC with the longest sequence is
completing the previous conversions.
Figure 30. Injected simultaneous mode on 4 channels
11.9.2 Regular simultaneous mode
This mode is performed on a regular channel group. The source of the external trigger
comes from the regular group mux of ADC1 (selected by the EXTSEL[2:0] bits in the
ADC1_CR2 register). A simultaneous trigger is provided to the ADC2.
Note: Do not convert the same channel on the two ADCs (no overlapping sampling times for the
two ADCs when converting the same channel).
At the end of conversion event on ADC1 or ADC2:
A 32-bit DMA transfer request is generated (if DMA bit is set) which transfers to SRAM
the ADC1_DR 32-bit register containing the ADC2 converted data in the upper
halfword and the ADC1 converted data in the lower halfword.
An EOC interrupt is generated (if enabled on one of the two ADC interfaces) when
ADC1/ADC2 regular channels are all converted.
Note: In regular simultaneous mode, one must convert sequences with the same length or ensure
that the interval between triggers is longer than the longest of the 2 sequences. Otherwise,
the ADC with the shortest sequence may restart while the ADC with the longest sequence is
completing the previous conversions.
CH0 CH1 CH2 CH3
CH3 CH2 CH1 CH0
ADC2
ADC1
Trigger End of injected conversion on ADC1 and ADC2
Conversion
Sampling
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Figure 31. Regular simultaneous mode on 16 channels
11.9.3 Fast interleaved mode
This mode can be started only on a regular channel group (usually one channel). The
source of external trigger comes from the regular channel mux of ADC1. After an external
trigger occurs:
ADC2 starts immediately and
ADC1 starts after a delay of 7 ADC clock cycles.
If CONT bit is set on both ADC1 and ADC2 the selected regular channels of both ADCs are
continuously converted.
After an EOC interrupt is generated by ADC1 (if enabled through the EOCIE bit) a 32-bit
DMA transfer request is generated (if the DMA bit is set) which transfers to SRAM the
ADC1_DR 32-bit register containing the ADC2 converted data in the upper halfword and the
ADC1 converted data in the lower halfword.
Note: The maximum sampling time allowed is <7 ADCCLK cycles to avoid the overlap between
ADC1 and ADC2 sampling phases in the event that they convert the same channel.
Figure 32. Fast interleaved mode on 1 channel in continuous conversion mode
11.9.4 Slow interleaved mode
This mode can be started only on a regular channel group (only one channel). The source of
external trigger comes from regular channel mux of ADC1. After external trigger occurs:
ADC2 starts immediately and
ADC1 starts after a delay of 14 ADC clock cycles.
ADC2 starts after a second delay of 14 ADC cycles, and so on.
Note: The maximum sampling time allowed is <14 ADCCLK cycles to avoid an overlap with the
next conversion.
CH0 CH1 CH2 CH3
CH15 CH14 CH13 CH12
ADC1
ADC2
Trigger End of conversion on ADC1 and ADC2
Conversion
Sampling
CH15
CH0
...
...
CH0
CH0
ADC2
ADC1
Trigger
End of conversion on ADC1
Conversion
Sampling
CH0
CH0
...
...
7 ADCCLK
cycles
End of conversion on ADC2
RM0008 Analog-to-digital converter (ADC)
Doc ID 13902 Rev 13 223/1093
After an EOC interrupt is generated by ADC1 (if enabled through the EOCIE bit) a 32-bit
DMA transfer request is generated (if the DMA bit is set) which transfers to SRAM the
ADC1_DR 32-bit register containing the ADC2 converted data in the upper halfword and the
ADC1 converted data in the lower halfword.
A new ADC2 start is automatically generated after 28 ADC clock cycles
CONT bit can not be set in the mode since it continuously converts the selected regular
channel.
Note: The application must ensure that no external trigger for injected channel occurs when
interleaved mode is enabled.
Figure 33. Slow interleaved mode on 1 channel
11.9.5 Alternate trigger mode
This mode can be started only on an injected channel group. The source of external trigger
comes from the injected group mux of ADC1.
When the 1st trigger occurs, all injected group channels in ADC1 are converted.
When the 2nd trigger arrives, all injected group channels in ADC2 are converted
and so on.
A JEOC interrupt, if enabled, is generated after all injected group channels of ADC1 are
converted.
A JEOC interrupt, if enabled, is generated after all injected group channels of ADC2 are
converted.
If another external trigger occurs after all injected group channels have been converted then
the alternate trigger process restarts by converting ADC1 injected group channels.
Figure 34. Alternate trigger: injected channel group of each ADC
CH0
ADC2
ADC1
Trigger
End of conversion on ADC1
Conversion
Sampling
14 ADCCLK
cycles
28 ADCCLK
cycles
CH0
CH0
CH0
End of conversion on ADC2
ADC1
ADC2
1st trigger
Conversion
Sampling
2nd trigger
3rd trigger
4th trigger
(n)th trigger
(n+1)th trigger
EOC, JEOC
on ADC1
EOC, JEOC
on ADC1
. . .
EOC, JEOC
on ADC2
EOC, JEOC
on ADC2
Analog-to-digital converter (ADC) RM0008
224/1093 Doc ID 13902 Rev 13
If the injected discontinuous mode is enabled for both ADC1 and ADC2:
When the 1st trigger occurs, the first injected channel in ADC1 is converted.
When the 2nd trigger arrives, the first injected channel in ADC2 are converted
and so on....
A JEOC interrupt, if enabled, is generated after all injected group channels of ADC1 are
converted.
A JEOC interrupt, if enabled, is generated after all injected group channels of ADC2 are
converted.
If another external trigger occurs after all injected group channels have been converted then
the alternate trigger process restarts.
Figure 35. Alternate trigger: 4 injected channels (each ADC) in discontinuous model
11.9.6 Independent mode
In this mode the dual ADC synchronization is bypassed and each ADC interfaces works
independently.
11.9.7 Combined regular/injected simultaneous mode
It is possible to interrupt simultaneous conversion of a regular group to start simultaneous
conversion of an injected group.
Note: In combined regular/injected simultaneous mode, one must convert sequences with the
same length or ensure that the interval between triggers is longer than the longest of the 2
sequences. Otherwise, the ADC with the shortest sequence may restart while the ADC with
the longest sequence is completing the previous conversions.
11.9.8 Combined regular simultaneous + alternate trigger mode
It is possible to interrupt regular group simultaneous conversion to start alternate trigger
conversion of an injected group. Figure 36 shows the behavior of an alternate trigger
interrupting a regular simultaneous conversion.
The injected alternate conversion is immediately started after the injected event arrives. If
regular conversion is already running, in order to ensure synchronization after the injected
conversion, the regular conversion of both (master/slave) ADCs is stopped and resumed
synchronously at the end of the injected conversion.
Note: In combined regular simultaneous + alternate trigger mode, one must convert sequences
with the same length or ensure that the interval between triggers is longer than the longest
of the 2 sequences. Otherwise, the ADC with the shortest sequence may restart while the
ADC with the longest sequence is completing the previous conversions.
ADC1
ADC2
1st trigger
Conversion
Sampling
2nd trigger
3rd trigger
4th trigger
5th trigger
6th trigger
7th trigger
8th trigger
JEOC on ADC2
JEOC on ADC1
RM0008 Analog-to-digital converter (ADC)
Doc ID 13902 Rev 13 225/1093
Figure 36. Alternate + Regular simultaneous
If a trigger occurs during an injected conversion that has interrupted a regular conversion, it
will be ignored. Figure 37 shows the behavior in this case (2nd trig is ignored).
Figure 37. Case of trigger occurring during injected conversion
11.9.9 Combined injected simultaneous + interleaved
It is possible to interrupt an interleaved conversion with an injected event. In this case the
interleaved conversion is interrupted and the injected conversion starts, at the end of the
injected sequence the interleaved conversion is resumed. Figure 38 shows the behavior
using an example.
Note: When the ADC clock prescaler is set to 4, the interleaved mode does not recover with
evenly spaced sampling periods: the sampling interval is 8 ADC clock periods followed by 6
ADC clock periods, instead of 7 clock periods followed by 7 clock periods.
Figure 38. Interleaved single channel with injected sequence CH11, CH12
ADC1 reg CH0 CH1 CH2
CH0
CH2 CH3
CH0
ADC1 inj
ADC2 reg
ADC2 inj
1st trig
2nd trig
synchro not lost
CH3 CH5 CH6 CH6 CH7
CH3 CH4
CH7 CH8
ADC1 reg CH0 CH1 CH2
CH0
CH2 CH3
CH0
ADC1 inj
ADC2 reg
ADC2 inj
1st trig
4th trig
CH3 CH5 CH6 CH6 CH7
CH3 CH4
CH7 CH8
2nd trig
3rd trig
CH0
CH0
ADC2
ADC1
Trigger
Conversion
Sampling
CH0 CH0
CH0 CH0 CH0
CH11 CH12
CH12 CH11
CH0 CH0
CH0 CH0
Analog-to-digital converter (ADC) RM0008
226/1093 Doc ID 13902 Rev 13
11.10 Temperature sensor
The temperature sensor can be used to measure the ambient temperature (T
A
) of the
device.
The temperature sensor is internally connected to the ADCx_IN16 input channel which is
used to convert the sensor output voltage into a digital value. The recommended sampling
time for the temperature sensor is 17.1 s.
The block diagram of the temperature sensor is shown in Figure 39.
When not in use, this sensor can be put in power down mode.
Note: The TSVREFE bit must be set to enable both internal channels: ADCx_IN16 (temperature
sensor) and ADCx_IN17 (V
REFINT
) conversion.
The temperature sensor output voltage changes linearly with temperature. The offset of this
line varies from chip to chip due to process variation (up to 45 C from one chip to another).
The internal temperature sensor is more suited to applications that detect temperature
variations instead of absolute temperatures. If accurate temperature readings are needed,
an external temperature sensor part should be used.
Figure 39. Temperature sensor and V
REFINT
channel block diagram
SENSOR
TEMPERATURE
V
SENSE
TSVREFE control bit
ADC1
A
d
d
r
e
s
s
/
d
a
t
a

b
u
s
converted data
V
REFINT
ADCx_IN16
ADCx_IN17
POWER
BLOCK
INTERNAL
RM0008 Analog-to-digital converter (ADC)
Doc ID 13902 Rev 13 227/1093
Reading the temperature
To use the sensor:
1. Select the ADCx_IN16 input channel.
2. Select a sample time of 17.1 s
3. Set the TSVREFE bit in the ADC control register 2 (ADC_CR2) to wake up the
temperature sensor from power down mode.
4. Start the ADC conversion by setting the ADON bit (or by external trigger).
5. Read the resulting V
SENSE
data in the ADC data register
6. Obtain the temperature using the following formula:
Temperature (in C) = {(V
25
- V
SENSE
) / Avg_Slope} + 25.
Where,
V
25
= V
SENSE
value for 25 C and
Avg_Slope = Average Slope for curve between Temperature vs. V
SENSE
(given in
mV/ C or V/ C).
Refer to the Electrical characteristics section for the actual values of V
25
and
Avg_Slope.
Note: The sensor has a startup time after waking from power down mode before it can output
V
SENSE
at the correct level. The ADC also has a startup time after power-on, so to minimize
the delay, the ADON and TSVREFE bits should be set at the same time.
11.11 ADC interrupts
An interrupt can be produced on end of conversion for regular and injected groups and
when the analog watchdog status bit is set. Separate interrupt enable bits are available for
flexibility.
Note: ADC1 and ADC2 interrupts are mapped onto the same interrupt vector. ADC3 interrupts are
mapped onto a separate interrupt vector.
Two other flags are present in the ADC_SR register, but there is no interrupt associated with
them:
JSTRT (Start of conversion for injected group channels)
STRT (Start of conversion for regular group channels)

Table 71. ADC interrupts
Interrupt event Event flag Enable Control bit
End of conversion regular group EOC EOCIE
End of conversion injected group JEOC JEOCIE
Analog watchdog status bit is set AWD AWDIE
Analog-to-digital converter (ADC) RM0008
228/1093 Doc ID 13902 Rev 13
11.12 ADC registers
Refer to Section 2.1 on page 46 for a list of abbreviations used in register descriptions.
The peripheral registers have to be accessed by words (32-bit).
11.12.1 ADC status register (ADC_SR)
Address offset: 0x00
Reset value: 0x0000 0000


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
STRT JSTRT JEOC EOC AWD
rc_w0 rc_w0 rc_w0 rc_w0 rc_w0
Bits 31:5 Reserved, must be kept at reset value.
Bit 4 STRT: Regular channel Start flag
This bit is set by hardware when regular channel conversion starts. It is cleared by software.
0: No regular channel conversion started
1: Regular channel conversion has started
Bit 3 JSTRT: Injected channel Start flag
This bit is set by hardware when injected channel group conversion starts. It is cleared by
software.
0: No injected group conversion started
1: Injected group conversion has started
Bit 2 JEOC: Injected channel end of conversion
This bit is set by hardware at the end of all injected group channel conversion. It is cleared by
software.
0: Conversion is not complete
1: Conversion complete
Bit 1 EOC: End of conversion
This bit is set by hardware at the end of a group channel conversion (regular or injected). It is
cleared by software or by reading the ADC_DR.
0: Conversion is not complete
1: Conversion complete
Bit 0 AWD: Analog watchdog flag
This bit is set by hardware when the converted voltage crosses the values programmed in
the ADC_LTR and ADC_HTR registers. It is cleared by software.
0: No Analog watchdog event occurred
1: Analog watchdog event occurred
RM0008 Analog-to-digital converter (ADC)
Doc ID 13902 Rev 13 229/1093
11.12.2 ADC control register 1 (ADC_CR1)
Address offset: 0x04
Reset value: 0x0000 0000


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
AWDEN JAWDEN
Reserved
DUALMOD[3:0]
rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DISCNUM[2:0]
JDISCE
N
DISC
EN
JAUTO
AWD
SGL
SCAN JEOC IE AWDIE EOCIE AWDCH[4:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:24 Reserved, must be kept at reset value.
Bit 23 AWDEN: Analog watchdog enable on regular channels
This bit is set/reset by software.
0: Analog watchdog disabled on regular channels
1: Analog watchdog enabled on regular channels
Bit 22 JAWDEN: Analog watchdog enable on injected channels
This bit is set/reset by software.
0: Analog watchdog disabled on injected channels
1: Analog watchdog enabled on injected channels
Bits 21:20 Reserved, must be kept at reset value.
Bits 19:16 DUALMOD[3:0]: Dual mode selection
These bits are written by software to select the operating mode.
0000: Independent mode.
0001: Combined regular simultaneous + injected simultaneous mode
0010: Combined regular simultaneous + alternate trigger mode
0011: Combined injected simultaneous + fast interleaved mode
0100: Combined injected simultaneous + slow Interleaved mode
0101: Injected simultaneous mode only
0110: Regular simultaneous mode only
0111: Fast interleaved mode only
1000: Slow interleaved mode only
1001: Alternate trigger mode only
Note: These bits are reserved in ADC2 and ADC3.
In dual mode, a change of channel configuration generates a restart that can produce a
loss of synchronization. It is recommended to disable dual mode before any
configuration change.
Bits 15:13 DISCNUM[2:0]: Discontinuous mode channel count
These bits are written by software to define the number of regular channels to be converted
in discontinuous mode, after receiving an external trigger.
000: 1 channel
001: 2 channels
.......
111: 8 channels
Analog-to-digital converter (ADC) RM0008
230/1093 Doc ID 13902 Rev 13
Bit 12 JDISCEN: Discontinuous mode on injected channels
This bit set and cleared by software to enable/disable discontinuous mode on injected group
channels
0: Discontinuous mode on injected channels disabled
1: Discontinuous mode on injected channels enabled
Bit 11 DISCEN: Discontinuous mode on regular channels
This bit set and cleared by software to enable/disable Discontinuous mode on regular
channels.
0: Discontinuous mode on regular channels disabled
1: Discontinuous mode on regular channels enabled
Bit 10 JAUTO: Automatic Injected Group conversion
This bit set and cleared by software to enable/disable automatic injected group conversion
after regular group conversion.
0: Automatic injected group conversion disabled
1: Automatic injected group conversion enabled
Bit 9 AWDSGL: Enable the watchdog on a single channel in scan mode
This bit set and cleared by software to enable/disable the analog watchdog on the channel
identified by the AWDCH[4:0] bits.
0: Analog watchdog enabled on all channels
1: Analog watchdog enabled on a single channel
Bit 8 SCAN: Scan mode
This bit is set and cleared by software to enable/disable Scan mode. In Scan mode, the
inputs selected through the ADC_SQRx or ADC_JSQRx registers are converted.
0: Scan mode disabled
1: Scan mode enabled
Note: An EOC or JEOC interrupt is generated only on the end of conversion of the last
channel if the corresponding EOCIE or JEOCIE bit is set
Bit 7 JEOCIE: Interrupt enable for injected channels
This bit is set and cleared by software to enable/disable the end of conversion interrupt for
injected channels.
0: JEOC interrupt disabled
1: JEOC interrupt enabled. An interrupt is generated when the JEOC bit is set.
Bit 6 AWDIE: Analog watchdog interrupt enable
This bit is set and cleared by software to enable/disable the analog watchdog interrupt. In
Scan mode if the watchdog thresholds are crossed, scan is aborted only if this bit is enabled.
0: Analog watchdog interrupt disabled
1: Analog watchdog interrupt enabled
Bit 5 EOCIE: Interrupt enable for EOC
This bit is set and cleared by software to enable/disable the End of Conversion interrupt.
0: EOC interrupt disabled
1: EOC interrupt enabled. An interrupt is generated when the EOC bit is set.
RM0008 Analog-to-digital converter (ADC)
Doc ID 13902 Rev 13 231/1093
11.12.3 ADC control register 2 (ADC_CR2)
Address offset: 0x08
Reset value: 0x0000 0000


Bits 4:0 AWDCH[4:0]: Analog watchdog channel select bits
These bits are set and cleared by software. They select the input channel to be guarded by
the Analog watchdog.
00000: ADC analog Channel0
00001: ADC analog Channel1
....
01111: ADC analog Channel15
10000: ADC analog Channel16
10001: ADC analog Channel17
Other values reserved.
Note: ADC1 analog Channel16 and Channel17 are internally connected to the temperature
sensor and to V
REFINT
, respectively.
ADC2 analog inputs Channel16 and Channel17 are internally connected to V
SS
.
ADC3 analog inputs Channel9, Channel14, Channel15, Channel16 and Channel17 are
connected to V
SS
.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
TSVRE
FE
SWSTA
RT
JSWST
ART
EXTTR
IG
EXTSEL[2:0] Res.
rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JEXTT
RIG
JEXTSEL[2:0] ALIGN Reserved DMA
Reserved
RST
CAL
CAL CONT ADON
rw rw rw rw rw Res. rw rw rw rw rw
Bits 31:24 Reserved, must be kept at reset value.
Bit 23 TSVREFE: Temperature sensor and V
REFINT
enable
This bit is set and cleared by software to enable/disable the temperature sensor and V
REFINT

channel. In devices with dual ADCs this bit is present only in ADC1.
0: Temperature sensor and V
REFINT
channel disabled
1: Temperature sensor and V
REFINT
channel enabled
Bit 22 SWSTART: Start conversion of regular channels
This bit is set by software to start conversion and cleared by hardware as soon as conversion
starts. It starts a conversion of a group of regular channels if SWSTART is selected as trigger
event by the EXTSEL[2:0] bits.
0: Reset state
1: Starts conversion of regular channels
Bit 21 JSWSTART: Start conversion of injected channels
This bit is set by software and cleared by software or by hardware as soon as the conversion
starts. It starts a conversion of a group of injected channels (if JSWSTART is selected as
trigger event by the JEXTSEL[2:0] bits.
0: Reset state
1: Starts conversion of injected channels
Analog-to-digital converter (ADC) RM0008
232/1093 Doc ID 13902 Rev 13
Bit 20 EXTTRIG: External trigger conversion mode for regular channels
This bit is set and cleared by software to enable/disable the external trigger used to start
conversion of a regular channel group.
0: Conversion on external event disabled
1: Conversion on external event enabled
Bits 19:17 EXTSEL[2:0]: External event select for regular group
These bits select the external event used to trigger the start of conversion of a regular group:
For ADC1 and ADC2, the assigned triggers are:
000: Timer 1 CC1 event
001: Timer 1 CC2 event
010: Timer 1 CC3 event
011: Timer 2 CC2 event
100: Timer 3 TRGO event
101: Timer 4 CC4 event
110: EXTI line 11/TIM8_TRGO event (TIM8_TRGO is available only in high-density and XL-
density devices)
111: SWSTART
For ADC3, the assigned triggers are:
000: Timer 3 CC1 event
001: Timer 2 CC3 event
010: Timer 1 CC3 event
011: Timer 8 CC1 event
100: Timer 8 TRGO event
101: Timer 5 CC1 event
110: Timer 5 CC3 event
111: SWSTART
Bit 16 Reserved, must be kept at reset value.
Bit 15 JEXTTRIG: External trigger conversion mode for injected channels
This bit is set and cleared by software to enable/disable the external trigger used to start
conversion of an injected channel group.
0: Conversion on external event disabled
1: Conversion on external event enabled
RM0008 Analog-to-digital converter (ADC)
Doc ID 13902 Rev 13 233/1093
Bits 14:12 JEXTSEL[2:0]: External event select for injected group
These bits select the external event used to trigger the start of conversion of an injected
group:
For ADC1 and ADC2 the assigned triggers are:
000: Timer 1 TRGO event
001: Timer 1 CC4 event
010: Timer 2 TRGO event
011: Timer 2 CC1 event
100: Timer 3 CC4 event
101: Timer 4 TRGO event
110: EXTI line15/TIM8_CC4 event (TIM8_CC4 is available only in high-density and XL-
density devices)
111: JSWSTART
For ADC3 the assigned triggers are:
000: Timer 1 TRGO event
001: Timer 1 CC4 event
010: Timer 4 CC3 event
011: Timer 8 CC2 event
100: Timer 8 CC4 event
101: Timer 5 TRGO event
110: Timer 5 CC4 event
111: JSWSTART
Bit 11 ALIGN: Data alignment
This bit is set and cleared by software. Refer to Figure 27.and Figure 28.
0: Right Alignment
1: Left Alignment
Bits 10:9 Reserved, must be kept at reset value.
Bit 8 DMA: Direct memory access mode
This bit is set and cleared by software. Refer to the DMA controller chapter for more details.
0: DMA mode disabled
1: DMA mode enabled
Only ADC1 and ADC3 can generate a DMA request.
Bits 7:4 Reserved, must be kept at reset value.
Bit 3 RSTCAL: Reset calibration
This bit is set by software and cleared by hardware. It is cleared after the calibration registers
are initialized.
0: Calibration register initialized.
1: Initialize calibration register.
Note: If RSTCAL is set when conversion is ongoing, additional cycles are required to clear the
calibration registers.
Bit 2 CAL: A/D Calibration
This bit is set by software to start the calibration. It is reset by hardware after calibration is
complete.
0: Calibration completed
1: Enable calibration
Analog-to-digital converter (ADC) RM0008
234/1093 Doc ID 13902 Rev 13
Bit 1 CONT: Continuous conversion
This bit is set and cleared by software. If set conversion takes place continuously till this bit is
reset.
0: Single conversion mode
1: Continuous conversion mode
Bit 0 ADON: A/D converter ON / OFF
This bit is set and cleared by software. If this bit holds a value of zero and a 1 is written to it
then it wakes up the ADC from Power Down state.
Conversion starts when this bit holds a value of 1 and a 1 is written to it. The application
should allow a delay of t
STAB
between power up and start of conversion. Refer to Figure 23.
0: Disable ADC conversion/calibration and go to power down mode.
1: Enable ADC and to start conversion
Note: If any other bit in this register apart from ADON is changed at the same time, then
conversion is not triggered. This is to prevent triggering an erroneous conversion.
RM0008 Analog-to-digital converter (ADC)
Doc ID 13902 Rev 13 235/1093
11.12.4 ADC sample time register 1 (ADC_SMPR1)
Address offset: 0x0C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
SMP17[2:0] SMP16[2:0] SMP15[2:1]
rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMP
15_0
SMP14[2:0] SMP13[2:0] SMP12[2:0] SMP11[2:0] SMP10[2:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:24 Reserved, must be kept at reset value.
Bits 23:0 SMPx[2:0]: Channel x Sample time selection
These bits are written by software to select the sample time individually for each channel.
During sample cycles channel selection bits must remain unchanged.
000: 1.5 cycles
001: 7.5 cycles
010: 13.5 cycles
011: 28.5 cycles
100: 41.5 cycles
101: 55.5 cycles
110: 71.5 cycles
111: 239.5 cycles
Note: ADC1 analog Channel16 and Channel 17 are internally connected to the temperature
sensor and to V
REFINT
, respectively.
ADC2 analog input Channel16 and Channel17 are internally connected to V
SS
.
ADC3 analog inputs Channel14, Channel15, Channel16 and Channel17 are connected
to V
SS
.
Analog-to-digital converter (ADC) RM0008
236/1093 Doc ID 13902 Rev 13
11.12.5 ADC sample time register 2 (ADC_SMPR2)
Address offset: 0x10
Reset value: 0x0000 0000

11.12.6 ADC injected channel data offset register x (ADC_JOFRx)(x=1..4)
Address offset: 0x14-0x20
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved SMP9[2:0] SMP8[2:0] SMP7[2:0] SMP6[2:0] SMP5[2:1]
Res. rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMP
5_0
SMP4[2:0] SMP3[2:0] SMP2[2:0] SMP1[2:0] SMP0[2:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:30 Reserved, must be kept at reset value.
Bits 29:0 SMPx[2:0]: Channel x Sample time selection
These bits are written by software to select the sample time individually for each channel.
During sample cycles channel selection bits must remain unchanged.
000: 1.5 cycles
001: 7.5 cycles
010: 13.5 cycles
011: 28.5 cycles
100: 41.5 cycles
101: 55.5 cycles
110: 71.5 cycles
111: 239.5 cycles
Note: ADC3 analog input Channel9 is connected to V
SS
.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
JOFFSETx[11:0]
rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:12 Reserved, must be kept at reset value.
Bits 11:0 JOFFSETx[11:0]: Data offset for injected channel x
These bits are written by software to define the offset to be subtracted from the raw
converted data when converting injected channels. The conversion result can be read from
in the ADC_JDRx registers.
RM0008 Analog-to-digital converter (ADC)
Doc ID 13902 Rev 13 237/1093
11.12.7 ADC watchdog high threshold register (ADC_HTR)
Address offset: 0x24
Reset value: 0x0000 0FFF

11.12.8 ADC watchdog low threshold register (ADC_LTR)
Address offset: 0x28
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
HT[11:0]
rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:12 Reserved, must be kept at reset value.
Bits 11:0 HT[11:0]: Analog watchdog high threshold
These bits are written by software to define the high threshold for the analog watchdog.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
LT[11:0]
rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:12 Reserved, must be kept at reset value.
Bits 11:0 LT[11:0]: Analog watchdog low threshold
These bits are written by software to define the low threshold for the analog watchdog.
Analog-to-digital converter (ADC) RM0008
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11.12.9 ADC regular sequence register 1 (ADC_SQR1)
Address offset: 0x2C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
L[3:0] SQ16[4:1]
rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ16_0 SQ15[4:0] SQ14[4:0] SQ13[4:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:24 Reserved, must be kept at reset value.
Bits 23:20 L[3:0]: Regular channel sequence length
These bits are written by software to define the total number of conversions in the regular
channel conversion sequence.
0000: 1 conversion
0001: 2 conversions
.....
1111: 16 conversions
Bits 19:15 SQ16[4:0]: 16th conversion in regular sequence
These bits are written by software with the channel number (0..17) assigned as the 16th in
the conversion sequence.
Bits 14:10 SQ15[4:0]: 15th conversion in regular sequence
Bits 9:5 SQ14[4:0]: 14th conversion in regular sequence
Bits 4:0 SQ13[4:0]: 13th conversion in regular sequence
RM0008 Analog-to-digital converter (ADC)
Doc ID 13902 Rev 13 239/1093
11.12.10 ADC regular sequence register 2 (ADC_SQR2)
Address offset: 0x30
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
SQ12[4:0] SQ11[4:0] SQ10[4:1]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ10_
0
SQ9[4:0] SQ8[4:0] SQ7[4:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:30 Reserved, must be kept at reset value.
Bits 29:26 SQ12[4:0]: 12th conversion in regular sequence
These bits are written by software with the channel number (0..17) assigned as the 12th in the
sequence to be converted.
Bits 24:20 SQ11[4:0]: 11th conversion in regular sequence
Bits 19:15 SQ10[4:0]: 10th conversion in regular sequence
Bits 14:10 SQ9[4:0]: 9th conversion in regular sequence
Bits 9:5 SQ8[4:0]: 8th conversion in regular sequence
Bits 4:0 SQ7[4:0]: 7th conversion in regular sequence
Analog-to-digital converter (ADC) RM0008
240/1093 Doc ID 13902 Rev 13
11.12.11 ADC regular sequence register 3 (ADC_SQR3)
Address offset: 0x34
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
SQ6[4:0] SQ5[4:0] SQ4[4:1]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ4_0 SQ3[4:0] SQ2[4:0] SQ1[4:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:30 Reserved, must be kept at reset value.
Bits 29:25 SQ6[4:0]: 6th conversion in regular sequence
These bits are written by software with the channel number (0..17) assigned as the 6th in the
sequence to be converted.
Bits 24:20 SQ5[4:0]: 5th conversion in regular sequence
Bits 19:15 SQ4[4:0]: 4th conversion in regular sequence
Bits 14:10 SQ3[4:0]: 3rd conversion in regular sequence
Bits 9:5 SQ2[4:0]: 2nd conversion in regular sequence
Bits 4:0 SQ1[4:0]: 1st conversion in regular sequence
RM0008 Analog-to-digital converter (ADC)
Doc ID 13902 Rev 13 241/1093
11.12.12 ADC injected sequence register (ADC_JSQR)
Address offset: 0x38
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
JL[1:0] JSQ4[4:1]
rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JSQ4_0 JSQ3[4:0] JSQ2[4:0] JSQ1[4:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:22 Reserved, must be kept at reset value.
Bits 21:20 JL[1:0]: Injected sequence length
These bits are written by software to define the total number of conversions in the injected
channel conversion sequence.
00: 1 conversion
01: 2 conversions
10: 3 conversions
11: 4 conversions
Bits 19:15 JSQ4[4:0]: 4th conversion in injected sequence (when JL[1:0] = 3)
(1)
These bits are written by software with the channel number (0..17) assigned as the 4th in
the sequence to be converted.
Note: Unlike a regular conversion sequence, if JL[1:0] length is less than four, the channels
are converted in a sequence starting from (4-JL). Example: ADC_JSQR[21:0] = 10
00011 00011 00111 00010 means that a scan conversion will convert the following
channel sequence: 7, 3, 3. (not 2, 7, 3)
Bits 14:10 JSQ3[4:0]: 3rd conversion in injected sequence (when JL[1:0] = 3)
Bits 9:5 JSQ2[4:0]: 2nd conversion in injected sequence (when JL[1:0] = 3)
Bits 4:0 JSQ1[4:0]: 1st conversion in injected sequence (when JL[1:0] = 3)
1. When JL=3 ( 4 injected conversions in the sequencer), the ADC converts the channels in this order:
JSQ1[4:0] >> JSQ2[4:0] >> JSQ3[4:0] >> JSQ4[4:0]
When JL=2 ( 3 injected conversions in the sequencer), the ADC converts the channels in this order:
JSQ2[4:0] >> JSQ3[4:0] >> JSQ4[4:0]
When JL=1 ( 2 injected conversions in the sequencer), the ADC converts the channels in this order:
JSQ3[4:0] >> JSQ4[4:0]
When JL=0 (1 injected conversion in the sequencer), the ADC converts only JSQ4[4:0] channel
Analog-to-digital converter (ADC) RM0008
242/1093 Doc ID 13902 Rev 13
11.12.13 ADC injected data register x (ADC_JDRx) (x= 1..4)
Address offset: 0x3C - 0x48
Reset value: 0x0000 0000

11.12.14 ADC regular data register (ADC_DR)
Address offset: 0x4C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA[15:0]
r r r r r r r r r r r r r r r r
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 JDATA[15:0]: Injected data
These bits are read only. They contain the conversion result from injected channel x. The
data is left or right-aligned as shown in Figure 27 and Figure 28.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADC2DATA[15:0]
r r r r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA[15:0]
r r r r r r r r r r r r r r r r
Bits 31:16 ADC2DATA[15:0]: ADC2 data
In ADC1: In dual mode, these bits contain the regular data of ADC2. Refer to Section 11.9:
Dual ADC mode.
In ADC2 and ADC3: these bits are not used.
Bits 15:0 DATA[15:0]: Regular data
These bits are read only. They contain the conversion result from the regular channels. The
data is left or right-aligned as shown in Figure 27 and Figure 28.
RM0008 Analog-to-digital converter (ADC)
Doc ID 13902 Rev 13 243/1093
11.12.15 ADC register map
The following table summarizes the ADC registers.

Table 72. ADC register map and reset values
Offset Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9 8 7 6 5 4 3 2 1 0
0x00
ADC_SR
Reserved
S
T
R
T
J
S
T
R
T
J
E
O
C
E
O
C
A
W
D
Reset value 0 0 0 0 0
0x04
ADC_CR1
Reserved
A
W
D
E
N
J
A
W
D
E
N
R
e
s
e
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v
e
d
DUALMOD
[3:0]
DISC
NUM [2:0]
J
D
I
S
C
E
N
D
I
S
C
E
N
J
A
U
T
O
A
W
D

S
G
L
S
C
A
N
J
E
O
C

I
E
A
W
D
I
E
E
O
C
I
E
AWDCH[4:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x08
ADC_CR2
Reserved
T
S
V
R
E
F
E
S
W
S
T
A
R
T
J
S
W
S
T
A
R
T
E
X
T
T
R
I
G
EXTSEL
[2:0]
R
e
s
e
r
v
e
d
J
E
X
T
T
R
I
G
JEXTSEL
[2:0]
A
L
I
G
N
R
e
s
e
r
v
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d
D
M
A
Reserved
R
S
T
C
A
L
C
A
L
C
O
N
T
A
D
O
N
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x0C
ADC_SMPR1 Sample time bits SMPx_x
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x10
ADC_SMPR2 Sample time bits SMPx_x
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x14
ADC_JOFR1
Reserved
JOFFSET1[11:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0
0x18
ADC_JOFR2
Reserved
JOFFSET2[11:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0
0x1C
ADC_JOFR3
Reserved
JOFFSET3[11:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0
0x20
ADC_JOFR4
Reserved
JOFFSET4[11:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0
0x24
ADC_HTR
Reserved
HT[11:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0
0x28
ADC_LTR
Reserved
LT[11:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0
0x2C
ADC_SQR1
Reserved
L[3:0]
SQ16[4:0] 16th
conversion in
regular sequence
bits
SQ15[4:0] 15th
conversion in
regular sequence
bits
SQ14[4:0] 14th
conversion in
regular sequence
bits
SQ13[4:0] 13th
conversion in
regular sequence
bits
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x30
ADC_SQR2
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SQ12[4:0] 12th
conversion in
regular sequence
bits
SQ11[4:0] 11th
conversion in
regular sequence
bits
SQ10[4:0] 10th
conversion in
regular sequence
bits
SQ9[4:0] 9th
conversion in
regular sequence
bits
SQ8[4:0] 8th
conversion in
regular sequence
bits
SQ7[4:0] 7th
conversion in
regular sequence
bits
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x34
ADC_SQR3
R
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SQ6[4:0] 6th
conversion in
regular sequence
bits
SQ5[4:0] 5th
conversion in
regular sequence
bits
SQ4[4:0] 4th
conversion in
regular sequence
bits
SQ3[4:0] 3rd
conversion in
regular sequence
bits
SQ2[4:0] 2nd
conversion in
regular sequence
bits
SQ1[4:0] 1st
conversion in
regular sequence
bits
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Analog-to-digital converter (ADC) RM0008
244/1093 Doc ID 13902 Rev 13
Refer to Table 1 on page 24 for the register boundary addresses.
0x38
ADC_JSQR
Reserved
JL[1:0]
JSQ4[4:0] 4th
conversion in
injected sequence
bits
JSQ3[4:0] 3rd
conversion in
injected sequence
bits
JSQ2[4:0] 2nd
conversion in
injected sequence
bits
JSQ1[4:0] 1st
conversion in
injected sequence
bits
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x3C
ADC_JDR1
Reserved
JDATA[15:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x40
ADC_JDR2
Reserved
JDATA[15:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x44
ADC_JDR3
Reserved
JDATA[15:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x48
ADC_JDR4
Reserved
JDATA[15:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x4C
ADC_DR ADC2DATA[15:0] Regular DATA[15:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 72. ADC register map and reset values (continued)
Offset Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9 8 7 6 5 4 3 2 1 0
RM0008 Digital-to-analog converter (DAC)
Doc ID 13902 Rev 13 245/1093

12 Digital-to-analog converter (DAC)
Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx
microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx
microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
High-density devices are STM32F101xx and STM32F103xx microcontrollers where the
Flash memory density ranges between 256 and 512 Kbytes.
XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the
Flash memory density ranges between 768 Kbytes and 1 Mbyte.
Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
This section applies to connectivity line, high-density and XL-density STM32F101xx and
STM32F103xx devices only.
12.1 DAC introduction
The DAC module is a 12-bit, voltage output digital-to-analog converter. The DAC can be
configured in 8- or 12-bit mode and may be used in conjunction with the DMA controller. In
12-bit mode, the data could be left- or right-aligned. The DAC has two output channels, each
with its own converter. In dual DAC channel mode, conversions could be done
independently or simultaneously when both channels are grouped together for synchronous
update operation. An input reference pin V
REF+
(shared with ADC) is available for better
resolution.
12.2 DAC main features
Two DAC converters: one output channel each
Left or right data alignment in 12-bit mode
Synchronized update capability
Noise-wave generation
Triangular-wave generation
Dual DAC channel independent or simultaneous conversions
DMA capability for each channel
External triggers for conversion
Input voltage reference V
REF+
The block diagram of a DAC channel is shown in Figure 40 and the pin description is given
in Table 73.

Digital-to-analog converter (DAC) RM0008
246/1093 Doc ID 13902 Rev 13
Figure 40. DAC channel block diagram
1. In connectivity line devices, the TIM8_TRGO trigger is replaced by TIM3_TRGO .

Note: Once the DAC channelx is enabled, the corresponding GPIO pin (PA4 or PA5) is
automatically connected to the analog converter output (DAC_OUTx). In order to avoid
parasitic consumption, the PA4 or PA5 pin should first be configured to analog (AIN).
Table 73. DAC pins
Name Signal type Remarks
V
REF+
Input, analog reference
positive
The higher/positive reference voltage for the DAC,
2.4 V V
REF
+ V
DDA
(3.3 V)
V
DDA
Input, analog supply Analog power supply
V
SSA
Input, analog supply
ground
Ground for analog power supply
DAC_OUTx Analog output signal DAC channelx analog output
V
DDA
V
SSA
V
REF+
DAC_OUTx
Control logicx
DHRx
12-bit
12-bit
LFSRx trianglex
DMA requestx
TSELx[2:0] bits
TIM4_TRGO
TIM5_TRGO
TIM6_TRGO
TIM7_TRGO
TIM2_TRGO
TIM8_TRGO
(1)
EXTI_9
DMAENx
TENx
MAMPx[3:0] bits
WAVENx[1:0] bits
SWTRIGx
DORx
Digital-to-analog
converterx
12-bit
DAC control register
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RM0008 Digital-to-analog converter (DAC)
Doc ID 13902 Rev 13 247/1093

12.3 DAC functional description
12.3.1 DAC channel enable
Each DAC channel can be powered on by setting its corresponding ENx bit in the DAC_CR
register. The DAC channel is then enabled after a startup time t
WAKEUP
.
Note: The ENx bit enables the analog DAC Channelx macrocell only. The DAC Channelx digital
interface is enabled even if the ENx bit is reset.
12.3.2 DAC output buffer enable
The DAC integrates two output buffers that can be used to reduce the output impedance,
and to drive external loads directly without having to add an external operational amplifier.
Each DAC channel output buffer can be enabled and disabled using the corresponding
BOFFx bit in the DAC_CR register.
12.3.3 DAC data format
Depending on the selected configuration mode, the data has to be written in the specified
register as described below:
Single DAC channelx, there are three possibilities:
8-bit right alignment: user has to load data into DAC_DHR8Rx [7:0] bits (stored
into DHRx[11:4] bits)
12-bit left alignment: user has to load data into DAC_DHR12Lx [15:4] bits (stored
into DHRx[11:0] bits)
12-bit right alignment: user has to load data into DAC_DHR12Rx [11:0] bits
(stored into DHRx[11:0] bits)
Depending on the loaded DAC_DHRyyyx register, the data written by the user will be shifted
and stored into the DHRx (Data Holding Registerx, that are internal non-memory-mapped
registers). The DHRx register will then be loaded into the DORx register either
automatically, by software trigger or by an external event trigger.

Digital-to-analog converter (DAC) RM0008
248/1093 Doc ID 13902 Rev 13
Figure 41. Data registers in single DAC channel mode
Dual DAC channels, there are three possibilities:
8-bit right alignment: data for DAC channel1 to be loaded into DAC_DHR8RD [7:0]
bits (stored into DHR1[11:4] bits) and data for DAC channel2 to be loaded into
DAC_DHR8RD [15:8] bits (stored into DHR2[11:4] bits)
12-bit left alignment: data for DAC channel1 to be loaded into DAC_DHR12LD
[15:4] bits (stored into DHR1[11:0] bits) and data for DAC channel2 to be loaded
into DAC_DHR12LD [31:20] bits (stored into DHR2[11:0] bits)
12-bit right alignment: data for DAC channel1 to be loaded into DAC_DHR12RD
[11:0] bits (stored into DHR1[11:0] bits) and data for DAC channel2 to be loaded
into DAC_DHR12LD [27:16] bits (stored into DHR2[11:0] bits)
Depending on the loaded DAC_DHRyyyD register, the data written by the user will be
shifted and stored into the DHR1 and DHR2 (Data Holding Registers, that are internal non-
memory-mapped registers). The DHR1 and DHR2 registers will then be loaded into the
DOR1 and DOR2 registers, respectively, either automatically, by software trigger or by an
external event trigger.
Figure 42. Data registers in dual DAC channel mode
12.3.4 DAC conversion
The DAC_DORx cannot be written directly and any data transfer to the DAC channelx must
be performed by loading the DAC_DHRx register (write on DAC_DHR8Rx, DAC_DHR12Lx,
DAC_DHR12Rx, DAC_DHR8RD, DAC_DHR12LD or DAC_DHR12LD).
Data stored into the DAC_DHRx register are automatically transferred to the DAC_DORx
register after one APB1 clock cycle, if no hardware trigger is selected (TENx bit in DAC_CR
register is reset). However, when a hardware trigger is selected (TENx bit in DAC_CR
register is set) and a trigger occurs, the transfer is performed three APB1 clock cycles later.
When DAC_DORx is loaded with the DAC_DHRx contents, the analog output voltage
becomes available after a time of t
SETTLING
that depends on the power supply voltage and
the analog output load.
31 24 15 7 0
8-bit right aligned
12-bit left aligned
12-bit right aligned
ai14710
31 24 15 7 0
8-bit right aligned
12-bit left aligned
12-bit right aligned
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RM0008 Digital-to-analog converter (DAC)
Doc ID 13902 Rev 13 249/1093

Figure 43. Timing diagram for conversion with trigger disabled TEN = 0
12.3.5 DAC output voltage
Digital inputs are converted to output voltages on a linear conversion between 0 and V
REF+
.
The analog output voltages on each DAC channel pin are determined by the following
equation:
12.3.6 DAC trigger selection
If the TENx control bit is set, conversion can then be triggered by an external event (timer
counter, external interrupt line). The TSELx[2:0] control bits determine which out of 8 possi-
ble events will trigger conversion as shown in Table 74.

Each time a DAC interface detects a rising edge on the selected timer TRGO output, or on
the selected external interrupt line 9, the last data stored into the DAC_DHRx register is
transferred into the DAC_DORx register. The DAC_DORx register is updated three APB1
cycles after the trigger occurs.
If the software trigger is selected, the conversion starts once the SWTRIG bit is set.
SWTRIG is reset by hardware once the DAC_DORx register has been loaded with the
DAC_DHRx register contents.
APB1_CLK
0x1AC
0x1AC
t
SETTLING
DHR
DOR
Output voltage
available on DAC_OUT pin
ai14711b
DACoutput V
REF
DOR
4095
-------------- =
Table 74. External triggers
Source Type TSEL[2:0]
Timer 6 TRGO event
Internal signal from on-chip
timers
000
Timer 3 TRGO event in
connectivity line devices or
Timer 8 TRGO in high-density
and XL-density devices
001
Timer 7 TRGO event 010
Timer 5 TRGO event 011
Timer 2 TRGO event 100
Timer 4 TRGO event 101
EXTI line9 External pin 110
SWTRIG Software control bit 111

Digital-to-analog converter (DAC) RM0008
250/1093 Doc ID 13902 Rev 13
Note: 1 TSELx[2:0] bit cannot be changed when the ENx bit is set.
2 When software trigger is selected, it takes only one APB1 clock cycle for DAC_DHRx-to-
DAC_DORx register transfer.
12.3.7 DMA request
Each DAC channel has a DMA capability. Two DMA channels are used to service DAC
channel DMA requests.
A DAC DMA request is generated when an external trigger (but not a software trigger)
occurs while the DMAENx bit is set. The value of the DAC_DHRx register is then transferred
to the DAC_DORx register.
In dual mode, if both DMAENx bits are set, two DMA requests are generated. If only one
DMA request is needed, you should set only the corresponding DMAENx bit. In this way, the
application can manage both DAC channels in dual mode by using one DMA request and a
unique DMA channel.
The DAC DMA request is not queued so that if a second external trigger arrives before the
acknowledgement of the last request, then the new request will not be serviced and no error
is reported
12.3.8 Noise generation
In order to generate a variable-amplitude pseudonoise, a Linear Feedback Shift Register is
available. The DAC noise generation is selected by setting WAVEx[1:0] to 01. The
preloaded value in the LFSR is 0xAAA. This register is updated, three APB1 clock cycles
after each trigger event, following a specific calculation algorithm.
Figure 44. DAC LFSR register calculation algorithm
The LFSR value, that may be masked partially or totally by means of the MAMPx[3:0] bits in
the DAC_CR register, is added up to the DAC_DHRx contents without overflow and this
value is then stored into the DAC_DORx register.
If LFSR is 0x0000, a 1 is injected into it (antilock-up mechanism).
It is possible to reset LFSR wave generation by resetting the WAVEx[1:0] bits.
11 10 9 8 7 6 5 4 3 2 1 0
12
NOR
X
12
X
0
X X
4
X
6
XOR
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RM0008 Digital-to-analog converter (DAC)
Doc ID 13902 Rev 13 251/1093

Figure 45. DAC conversion (SW trigger enabled) with LFSR wave generation
Note: DAC trigger must be enabled for noise generation, by setting the TENx bit in the DAC_CR
register.
12.3.9 Triangle-wave generation
It is possible to add a small-amplitude triangular waveform on a DC or slowly varying signal.
DAC triangle-wave generation is selected by setting WAVEx[1:0] to 10. The amplitude is
configured through the MAMPx[3:0] bits in the DAC_CR register. An internal triangle counter
is incremented three APB1 clock cycles after each trigger event. The value of this counter is
then added to the DAC_DHRx register without overflow and the sum is stored into the
DAC_DORx register. The triangle counter is incremented while it is less than the maximum
amplitude defined by the MAMPx[3:0] bits. Once the configured amplitude is reached, the
counter is decremented down to 0, then incremented again and so on.
It is possible to reset triangle wave generation by resetting WAVEx[1:0] bits.
Figure 46. DAC triangle wave generation
APB1_CLK
0x00
0xAAA
DHR
DOR
ai14714
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SWTRIG
MAMPx[3:0] max amplitude
+ DAC_DHRx base value
DAC_DHRx base value

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252/1093 Doc ID 13902 Rev 13
Figure 47. DAC conversion (SW trigger enabled) with triangle wave generation
Note: 1 DAC trigger must be enabled for noise generation, by setting the TENx bit in the DAC_CR
register.
2 MAMPx[3:0] bits must be configured before enabling the DAC, otherwise they cannot be
changed.
12.4 Dual DAC channel conversion
To efficiently use the bus bandwidth in applications that require the two DAC channels at the
same time, three dual registers are implemented: DHR8RD, DHR12RD and DHR12LD. A
unique register access is then required to drive both DAC channels at the same time.
Eleven possible conversion modes are possible using the two DAC channels and these dual
registers. All the conversion modes can nevertheless be obtained using separate DHRx
registers if needed.
All modes are described in the paragraphs below.
12.4.1 Independent trigger without wave generation
To configure the DAC in this conversion mode, the following sequence is required:
Set the two DAC channel trigger enable bits TEN1 and TEN2
Configure different trigger sources by setting different values in the TSEL1[2:0] and
TSEL2[2:0] bits
Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD,
DAC_DHR12LD or DAC_DHR8RD)
When a DAC channel1 trigger arrives, the DHR1 register is transferred into DAC_DOR1
(three APB1 clock cycles later).
When a DAC channel2 trigger arrives, the DHR2 register is transferred into DAC_DOR2
(three APB1 clock cycles later).
APB1_CLK
0xABE
0xABE
DHR
DOR
ai14714
0xABF
SWTRIG
0xAC0
RM0008 Digital-to-analog converter (DAC)
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12.4.2 Independent trigger with same LFSR generation
To configure the DAC in this conversion mode, the following sequence is required:
Set the two DAC channel trigger enable bits TEN1 and TEN2
Configure different trigger sources by setting different values in the TSEL1[2:0] and
TSEL2[2:0] bits
Configure the two DAC channel WAVEx[1:0] bits as 01 and the same LFSR mask
value in the MAMPx[3:0] bits
Load the dual DAC channel data into the desired DHR register (DHR12RD, DHR12LD
or DHR8RD)
When a DAC channel1 trigger arrives, the LFSR1 counter, with the same mask, is added to
the DHR1 register and the sum is transferred into DAC_DOR1 (three APB1 clock cycles
later). Then the LFSR1 counter is updated.
When a DAC channel2 trigger arrives, the LFSR2 counter, with the same mask, is added to
the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock cycles
later). Then the LFSR2 counter is updated.
12.4.3 Independent trigger with different LFSR generation
To configure the DAC in this conversion mode, the following sequence is required:
Set the two DAC channel trigger enable bits TEN1 and TEN2
Configure different trigger sources by setting different values in the TSEL1[2:0] and
TSEL2[2:0] bits
Configure the two DAC channel WAVEx[1:0] bits as 01 and set different LFSR masks
values in the MAMP1[3:0] and MAMP2[3:0] bits
Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD,
DAC_DHR12LD or DAC_DHR8RD)
When a DAC channel1 trigger arrives, the LFSR1 counter, with the mask configured by
MAMP1[3:0], is added to the DHR1 register and the sum is transferred into DAC_DOR1
(three APB1 clock cycles later). Then the LFSR1 counter is updated.
When a DAC channel2 trigger arrives, the LFSR2 counter, with the mask configured by
MAMP2[3:0], is added to the DHR2 register and the sum is transferred into DAC_DOR2
(three APB1 clock cycles later). Then the LFSR2 counter is updated.
12.4.4 Independent trigger with same triangle generation
To configure the DAC in this conversion mode, the following sequence is required:
Set the two DAC channel trigger enable bits TEN1 and TEN2
Configure different trigger sources by setting different values in the TSEL1[2:0] and
TSEL2[2:0] bits
Configure the two DAC channel WAVEx[1:0] bits as 1x and the same maximum
amplitude value in the MAMPx[3:0] bits
Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD,
DAC_DHR12LD or DAC_DHR8RD)
When a DAC channel1 trigger arrives, the DAC channel1 triangle counter, with the same
triangle amplitude, is added to the DHR1 register and the sum is transferred into

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DAC_DOR1 (three APB1 clock cycles later). The DAC channel1 triangle counter is then
updated.
When a DAC channel2 trigger arrives, the DAC channel2 triangle counter, with the same
triangle amplitude, is added to the DHR2 register and the sum is transferred into
DAC_DOR2 (three APB1 clock cycles later). The DAC channel2 triangle counter is then
updated.
12.4.5 Independent trigger with different triangle generation
To configure the DAC in this conversion mode, the following sequence is required:
Set the two DAC channel trigger enable bits TEN1 and TEN2
Configure different trigger sources by setting different values in the TSEL1[2:0] and
TSEL2[2:0] bits
Configure the two DAC channel WAVEx[1:0] bits as 1x and set different maximum
amplitude values in the MAMP1[3:0] and MAMP2[3:0] bits
Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD,
DAC_DHR12LD or DAC_DHR8RD)
When a DAC channel1 trigger arrives, the DAC channel1 triangle counter, with a triangle
amplitude configured by MAMP1[3:0], is added to the DHR1 register and the sum is
transferred into DAC_DOR1 (three APB1 clock cycles later). The DAC channel1 triangle
counter is then updated.
When a DAC channel2 trigger arrives, the DAC channel2 triangle counter, with a triangle
amplitude configured by MAMP2[3:0], is added to the DHR2 register part and the sum is
transferred into DAC_DOR2 (three APB1 clock cycles later). The DAC channel2 triangle
counter is then updated.
12.4.6 Simultaneous software start
To configure the DAC in this conversion mode, the following sequence is required:
Load the dual DAC channel data to the desired DHR register (DAC_DHR12RD,
DAC_DHR12LD or DAC_DHR8RD)
In this configuration, one APB1 clock cycle later, the DHR1 and DHR2 registers are
transferred into DAC_DOR1 and DAC_DOR2, respectively.
12.4.7 Simultaneous trigger without wave generation
To configure the DAC in this conversion mode, the following sequence is required:
Set the two DAC channel trigger enable bits TEN1 and TEN2
Configure the same trigger source for both DAC channels by setting the same value in
the TSEL1[2:0] and TSEL2[2:0] bits
Load the dual DAC channel data to the desired DHR register (DAC_DHR12RD,
DAC_DHR12LD or DAC_DHR8RD)
When a trigger arrives, the DHR1 and DHR2 registers are transferred into DAC_DOR1 and
DAC_DOR2, respectively (after three APB1 clock cycles).
RM0008 Digital-to-analog converter (DAC)
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12.4.8 Simultaneous trigger with same LFSR generation
To configure the DAC in this conversion mode, the following sequence is required:
Set the two DAC channel trigger enable bits TEN1 and TEN2
Configure the same trigger source for both DAC channels by setting the same value in
the TSEL1[2:0] and TSEL2[2:0] bits
Configure the two DAC channel WAVEx[1:0] bits as 01 and the same LFSR mask
value in the MAMPx[3:0] bits
Load the dual DAC channel data to the desired DHR register (DHR12RD, DHR12LD or
DHR8RD)
When a trigger arrives, the LFSR1 counter, with the same mask, is added to the DHR1
register and the sum is transferred into DAC_DOR1 (three APB1 clock cycles later). The
LFSR1 counter is then updated. At the same time, the LFSR2 counter, with the same mask,
is added to the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock
cycles later). The LFSR2 counter is then updated.
12.4.9 Simultaneous trigger with different LFSR generation
To configure the DAC in this conversion mode, the following sequence is required:
Set the two DAC channel trigger enable bits TEN1 and TEN2
Configure the same trigger source for both DAC channels by setting the same value in
the TSEL1[2:0] and TSEL2[2:0] bits
Configure the two DAC channel WAVEx[1:0] bits as 01 and set different LFSR masks
values using the MAMP1[3:0] and MAMP2[3:0] bits
Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD,
DAC_DHR12LD or DAC_DHR8RD)
When a trigger arrives, the LFSR1 counter, with the mask configured by MAMP1[3:0], is
added to the DHR1 register and the sum is transferred into DAC_DOR1 (three APB1 clock
cycles later). The LFSR1 counter is then updated.
At the same time, the LFSR2 counter, with the mask configured by MAMP2[3:0], is added to
the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock cycles
later). The LFSR2 counter is then updated.
12.4.10 Simultaneous trigger with same triangle generation
To configure the DAC in this conversion mode, the following sequence is required:
Set the two DAC channel trigger enable bits TEN1 and TEN2
Configure the same trigger source for both DAC channels by setting the same value in
the TSEL1[2:0] and TSEL2[2:0] bits
Configure the two DAC channel WAVEx[1:0] bits as 1x and the same maximum
amplitude value using the MAMPx[3:0] bits
Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD,
DAC_DHR12LD or DAC_DHR8RD)
When a trigger arrives, the DAC channel1 triangle counter, with the same triangle amplitude,
is added to the DHR1 register and the sum is transferred into DAC_DOR1 (three APB1 clock
cycles later). The DAC channel1 triangle counter is then updated.
At the same time, the DAC channel2 triangle counter, with the same triangle amplitude, is

Digital-to-analog converter (DAC) RM0008
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added to the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock
cycles later). The DAC channel2 triangle counter is then updated.
12.4.11 Simultaneous trigger with different triangle generation
To configure the DAC in this conversion mode, the following sequence is required:
Set the two DAC channel trigger enable bits TEN1 and TEN2
Configure the same trigger source for both DAC channels by setting the same value in
the TSEL1[2:0] and TSEL2[2:0] bits
Configure the two DAC channel WAVEx[1:0] bits as 1x and set different maximum
amplitude values in the MAMP1[3:0] and MAMP2[3:0] bits
Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD,
DAC_DHR12LD or DAC_DHR8RD)
When a trigger arrives, the DAC channel1 triangle counter, with a triangle amplitude
configured by MAMP1[3:0], is added to the DHR1 register and the sum is transferred into
DAC_DOR1 (three APB1 clock cycles later). Then the DAC channel1 triangle counter is
updated.
At the same time, the DAC channel2 triangle counter, with a triangle amplitude configured
by MAMP2[3:0], is added to the DHR2 register and the sum is transferred into DAC_DOR2
(three APB1 clock cycles later). Then the DAC channel2 triangle counter is updated.
12.5 DAC registers
The peripheral registers have to be accessed by words (32-bit).
12.5.1 DAC control register (DAC_CR)
Address offset: 0x00
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
DMA
EN2
MAMP2[3:0] WAVE2[1:0] TSEL2[2:0] TEN2 BOFF2 EN2
rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
DMA
EN1
MAMP1[3:0] WAVE1[1:0] TSEL1[2:0] TEN1 BOFF1 EN1
rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:29 Reserved.
Bit 28 DMAEN2: DAC channel2 DMA enable
This bit is set and cleared by software.
0: DAC channel2 DMA mode disabled
1: DAC channel2 DMA mode enabled
RM0008 Digital-to-analog converter (DAC)
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Bit 27:24 MAMP2[3:0]: DAC channel2 mask/amplitude selector
These bits are written by software to select mask in wave generation mode or amplitude in
triangle generation mode.
0000: Unmask bit0 of LFSR/ Triangle Amplitude equal to 1
0001: Unmask bits[1:0] of LFSR/ Triangle Amplitude equal to 3
0010: Unmask bits[2:0] of LFSR/ Triangle Amplitude equal to 7
0011: Unmask bits[3:0] of LFSR/ Triangle Amplitude equal to 15
0100: Unmask bits[4:0] of LFSR/ Triangle Amplitude equal to 31
0101: Unmask bits[5:0] of LFSR/ Triangle Amplitude equal to 63
0110: Unmask bits[6:0] of LFSR/ Triangle Amplitude equal to 127
0111: Unmask bits[7:0] of LFSR/ Triangle Amplitude equal to 255
1000: Unmask bits[8:0] of LFSR/ Triangle Amplitude equal to 511
1001: Unmask bits[9:0] of LFSR/ Triangle Amplitude equal to 1023
1010: Unmask bits[10:0] of LFSR/ Triangle Amplitude equal to 2047
1011: Unmask bits[11:0] of LFSR/ Triangle Amplitude equal to 4095
Bit 23:22 WAVE2[1:0]: DAC channel2 noise/triangle wave generation enable
These bits are set/reset by software.
00: wave generation disabled
01: Noise wave generation enabled
1x: Triangle wave generation enabled
Note: only used if bit TEN2 = 1 (DAC channel2 trigger enabled)
Bits 21:19 TSEL2[2:0]: DAC channel2 trigger selection
These bits select the external event used to trigger DAC channel2
000: Timer 6 TRGO event
001: Timer 3 TRGO event in connectivity line devices, Timer 8 TRGO in high-density and
XL-density devices
010: Timer 7 TRGO event
011: Timer 5 TRGO event
100: Timer 2 TRGO event
101: Timer 4 TRGO event
110: External line9
111: Software trigger
Note: only used if bit TEN2 = 1 (DAC channel2 trigger enabled)
Bit 18 TEN2: DAC channel2 trigger enable
This bit set and cleared by software to enable/disable DAC channel2 trigger
0: DAC channel2 trigger disabled and data written into DAC_DHRx register is transferred
one APB1 clock cycle later to the DAC_DOR2 register.
1: DAC channel2 trigger enabled and data transfer from DAC_DHRx register is transferred
three APB1 clock cycles later to the DAC_DOR2 register.
Note: When software trigger is selected, it takes only one APB1 clock cycle for DAC_DHRx to
DAC_DOR2 register transfer.
Bit 17 BOFF2: DAC channel2 output buffer disable
This bit set and cleared by software to enable/disable DAC channel2 output buffer.
0: DAC channel2 output buffer enabled
1: DAC channel2 output buffer disabled
Bit 16 EN2: DAC channel2 enable
This bit set and cleared by software to enable/disable DAC channel2.
0: DAC channel2 disabled
1: DAC channel2 enabled

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Bits 15:13 Reserved.
Bit 12 DMAEN1: DAC channel1 DMA enable
This bit is set and cleared by software.
0: DAC channel1 DMA mode disabled
1: DAC channel1 DMA mode enabled
Bits 11:8 MAMP1[3:0]: DAC channel1 mask/amplitude selector
These bits are written by software to select mask in wave generation mode or amplitude in
triangle generation mode.
0000: Unmask bit0 of LFSR/ Triangle Amplitude equal to 1
0001: Unmask bits[1:0] of LFSR/ Triangle Amplitude equal to 3
0010: Unmask bits[2:0] of LFSR/ Triangle Amplitude equal to 7
0011: Unmask bits[3:0] of LFSR/ Triangle Amplitude equal to 15
0100: Unmask bits[4:0] of LFSR/ Triangle Amplitude equal to 31
0101: Unmask bits[5:0] of LFSR/ Triangle Amplitude equal to 63
0110: Unmask bits[6:0] of LFSR/ Triangle Amplitude equal to 127
0111: Unmask bits[7:0] of LFSR/ Triangle Amplitude equal to 255
1000: Unmask bits[8:0] of LFSR/ Triangle Amplitude equal to 511
1001: Unmask bits[9:0] of LFSR/ Triangle Amplitude equal to 1023
1010: Unmask bits[10:0] of LFSR/ Triangle Amplitude equal to 2047
1011: Unmask bits[11:0] of LFSR/ Triangle Amplitude equal to 4095
Bits 7:6 WAVE1[1:0]: DAC channel1 noise/triangle wave generation enable
These bits are set/reset by software.
00: wave generation disabled
01: Noise wave generation enabled
1x: Triangle wave generation enabled
Note: only used if bit TEN1 = 1 (DAC channel1 trigger enabled)
Bits 5:3 TSEL1[2:0]: DAC channel1 trigger selection
These bits select the external event used to trigger DAC channel1
000: Timer 6 TRGO event
001: Timer 3 TRGO event in connectivity line devices, Timer 8 TRGO in high-density and
XL-density devices
010: Timer 7 TRGO event
011: Timer 5 TRGO event
100: Timer 2 TRGO event
101: Timer 4 TRGO event
110: External line9
111: Software trigger
Note: only used if bit TEN1 = 1 (DAC channel1 trigger enabled)
Bit 2 TEN1: DAC channel1 trigger enable
This bit set and cleared by software to enable/disable DAC channel1 trigger
0: DAC channel1 trigger disabled and data written into DAC_DHRx register is transferred
one APB1 clock cycle later to the DAC_DOR1 register.
1: DAC channel1 trigger enabled and data transfer from DAC_DHRx register is transferred
three APB1 clock cycles later to the DAC_DOR1 register.
Note: When software trigger is selected, it takes only one APB1 clock cycle for DAC_DHRx to
DAC_DOR1 register transfer.
RM0008 Digital-to-analog converter (DAC)
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12.5.2 DAC software trigger register (DAC_SWTRIGR)
Address offset: 0x04
Reset value: 0x0000 0000

Bit 1 BOFF1: DAC channel1 output buffer disable
This bit set and cleared by software to enable/disable DAC channel1 output buffer.
0: DAC channel1 output buffer enabled
1: DAC channel1 output buffer disabled
Bit 0 EN1: DAC channel1 enable
This bit set and cleared by software to enable/disable DAC channel1.
0: DAC channel1 disabled
1: DAC channel1 enabled
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
SWTRI
G2
SWTRI
G1
w w
Bits 31:2 Reserved.
Bit 1 SWTRIG2: DAC channel2 software trigger
This bit is set and cleared by software to enable/disable the software trigger.
0: Software trigger disabled
1: Software trigger enabled
Note: This bit is reset by hardware (one APB1 clock cycle later) once the DAC_DHR2 register
value is loaded to the DAC_DOR2 register.
Bit 0 SWTRIG1: DAC channel1 software trigger
This bit is set and cleared by software to enable/disable the software trigger.
0: Software trigger disabled
1: Software trigger enabled
Note: This bit is reset by hardware (one APB1 clock cycle later) once the DAC_DHR1 register
value is loaded to the DAC_DOR1 register.

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12.5.3 DAC channel1 12-bit right-aligned data holding register
(DAC_DHR12R1)
Address offset: 0x08
Reset value: 0x0000 0000

12.5.4 DAC channel1 12-bit left aligned data holding register
(DAC_DHR12L1)
Address offset: 0x0C
Reset value: 0x0000 0000

12.5.5 DAC channel1 8-bit right aligned data holding register
(DAC_DHR8R1)
Address offset: 0x10
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
DACC1DHR[11:0]
rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:12 Reserved.
Bit 11:0 DACC1DHR[11:0]: DAC channel1 12-bit right-aligned data
These bits are written by software which specify 12-bit data for DAC channel1.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DHR[11:0]
Reserved
rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:16 Reserved.
Bit 15:4 DACC1DHR[11:0]: DAC channel1 12-bit left-aligned data
These bits are written by software which specify 12-bit data for DAC channel1.
Bits 3:0 Reserved.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
DACC1DHR[7:0]
rw rw rw rw rw rw rw rw
Bits 31:8 Reserved.
Bits 7:0 DACC1DHR[7:0]: DAC channel1 8-bit right-aligned data
These bits are written by software which specify 8-bit data for DAC channel1.
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12.5.6 DAC channel2 12-bit right aligned data holding register
(DAC_DHR12R2)
Address offset: 0x14
Reset value: 0x0000 0000

12.5.7 DAC channel2 12-bit left aligned data holding register
(DAC_DHR12L2)
Address offset: 0x18
Reset value: 0x0000 0000

12.5.8 DAC channel2 8-bit right-aligned data holding register
(DAC_DHR8R2)
Address offset: 0x1C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
DACC2DHR[11:0]
rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:12 Reserved.
Bits 11:0 DACC2DHR[11:0]: DAC channel2 12-bit right-aligned data
These bits are written by software which specify 12-bit data for DAC channel2.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC2DHR[11:0]
Reserved
rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:16 Reserved.
Bits 15:4 DACC2DHR[11:0]: DAC channel2 12-bit left-aligned data
These bits are written by software which specify 12-bit data for DAC channel2.
Bits 3:0 Reserved.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
DACC2DHR[7:0]
rw rw rw rw rw rw rw rw
Bits 31:8 Reserved.
Bits 7:0 DACC2DHR[7:0]: DAC channel2 8-bit right-aligned data
These bits are written by software which specify 8-bit data for DAC channel2.

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12.5.9 Dual DAC 12-bit right-aligned data holding register
(DAC_DHR12RD)
Address offset: 0x20
Reset value: 0x0000 0000

12.5.10 DUAL DAC 12-bit left aligned data holding register
(DAC_DHR12LD)
Address offset: 0x24
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
DACC2DHR[11:0]
rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
DACC1DHR[11:0]
rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:28 Reserved.
Bits 27:16 DACC2DHR[11:0]: DAC channel2 12-bit right-aligned data
These bits are written by software which specify 12-bit data for DAC channel2.
Bits 15:12 Reserved.
Bits 11:0 DACC1DHR[11:0]: DAC channel1 12-bit right-aligned data
These bits are written by software which specify 12-bit data for DAC channel1.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DACC2DHR[11:0]
Reserved
rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DHR[11:0]
Reserved
rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:20 DACC2DHR[11:0]: DAC channel2 12-bit left-aligned data
These bits are written by software which specify 12-bit data for DAC channel2.
Bits 19:16 Reserved.
Bits 15:4 DACC1DHR[11:0]: DAC channel1 12-bit left-aligned data
These bits are written by software which specify 12-bit data for DAC channel1.
Bits 3:0 Reserved.
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12.5.11 DUAL DAC 8-bit right aligned data holding register
(DAC_DHR8RD)
Address offset: 0x28
Reset value: 0x0000 0000

12.5.12 DAC channel1 data output register (DAC_DOR1)
Address offset: 0x2C
Reset value: 0x0000 0000

12.5.13 DAC channel2 data output register (DAC_DOR2)
Address offset: 0x30
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC2DHR[7:0] DACC1DHR[7:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:16 Reserved.
Bits 15:8 DACC2DHR[7:0]: DAC channel2 8-bit right-aligned data
These bits are written by software which specify 8-bit data for DAC channel2.
Bits 7:0 DACC1DHR[7:0]: DAC channel1 8-bit right-aligned data
These bits are written by software which specify 8-bit data for DAC channel1.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
DACC1DOR[11:0]
r r r r r r r r r r r r
Bits 31:12 Reserved.
Bit 11:0 DACC1DOR[11:0]: DAC channel1 data output
These bits are read only, they contain data output for DAC channel1.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
DACC2DOR[11:0]
r r r r r r r r r r r r
Bits 31:12 Reserved.
Bit 11:0 DACC2DOR[11:0]: DAC channel2 data output
These bits are read only, they contain data output for DAC channel2.

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12.5.14 DAC register map
The following table summarizes the DAC registers.

Note: Refer to Table 3 on page 50 for the register boundary addresses.
Table 75. DAC register map
Offset Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9 8 7 6 5 4 3 2 1 0
0x00
DAC_CR
Reserved
D
M
A
E
N
2
MAMP2[3:0]
WAVE
2[2:0]
TSEL2[2:0]
T
E
N
2
B
O
F
F
2
E
N
2
Reserved
D
M
A
E
N
1
MAMP1[3:0]
WAVE
1[2:0]
TSEL1
[2:0]
T
E
N
1
B
O
F
F
1
E
N
1
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x04
DAC_SWTRIG
R
Reserved
S
W
T
R
I
G
2
S
W
T
R
I
G
1
Reset value 0 0
0x08
DAC_DHR12R
1
Reserved
DACC1DHR[11:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0
0x0C
DAC_DHR12L
1
Reserved
DACC1DHR[11:0]
Reserved
Reset value 0 0 0 0 0 0 0 0 0 0 0 0
0x10
DAC_DHR8R1
Reserved
DACC1DHR[7:0]
Reset value 0 0 0 0 0 0 0 0
0x14
DAC_DHR12R
2
Reserved
DACC2DHR[11:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0
0x18
DAC_DHR12L
2
Reserved
DACC2DHR[11:0]
Reserved
Reset value 0 0 0 0 0 0 0 0 0 0 0 0
0x1C
DAC_DHR8R2
Reserved
DACC2DHR[7:0]
0x20
DAC_DHR12R
D
Reserved
DACC2DHR[11:0]
Reserved
DACC1DHR[11:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x24
DAC_DHR12L
D
DACC2DHR[11:0]
Reserved
DACC1DHR[11:0]
Reserved
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x28
DAC_DHR8RD
Reserved
DACC2DHR[7:0] DACC1DHR[7:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x2C
DAC_DOR1
Reserved
DACC1DOR[11:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0
0x30
DAC_DOR2
Reserved
DACC2DOR[11:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0
RM0008 Direct memory access controller (DMA)
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13 Direct memory access controller (DMA)
Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx
microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx
microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
High-density devices are STM32F101xx and STM32F103xx microcontrollers where the
Flash memory density ranges between 256 and 512 Kbytes.
XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the
Flash memory density ranges between 768 Kbytes and 1 Mbyte.
Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
This section applies to the whole STM32F10xxx family, unless otherwise specified.
13.1 DMA introduction
Direct memory access (DMA) is used in order to provide high-speed data transfer between
peripherals and memory as well as memory to memory. Data can be quickly moved by DMA
without any CPU actions. This keeps CPU resources free for other operations.
The two DMA controllers have 12 channels in total (7 for DMA1 and 5 for DMA2), each
dedicated to managing memory access requests from one or more peripherals. It has an
arbiter for handling the priority between DMA requests.
13.2 DMA main features
12 independently configurable channels (requests): 7 for DMA1 and 5 for DMA2
Each of the 12 channels is connected to dedicated hardware DMA requests, software
trigger is also supported on each channel. This configuration is done by software.
Priorities between requests from channels of one DMA are software programmable (4
levels consisting of very high, high, medium, low) or hardware in case of equality
(request 1 has priority over request 2, etc.)
Independent source and destination transfer size (byte, half word, word), emulating
packing and unpacking. Source/destination addresses must be aligned on the data
size.
Support for circular buffer management
3 event flags (DMA Half Transfer, DMA Transfer complete and DMA Transfer Error)
logically ORed together in a single interrupt request for each channel
Memory-to-memory transfer
Peripheral-to-memory and memory-to-peripheral, and peripheral-to-peripheral
transfers
Access to Flash, SRAM, APB1, APB2 and AHB peripherals as source and destination
Programmable number of data to be transferred: up to 65536

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266/1093 Doc ID 13902 Rev 13
The block diagram is shown in Figure 48.
Figure 48. DMA block diagram in connectivity line devices
FLTF
Ch.1
Ch.2
Ch.7
Arbiter
Cortex-M3
SRAM
AHB Slave
DMA1
Code
DCode
System
DMA request
APB1
Flash
Bridge 1
Bridge 2
Ch.1
Ch.2
Ch.5
Arbiter
AHB Slave
DMA2
APB2
ai15811b
DMA request
B
u
s

m
a
t
r
i
x
DMA
D
M
A
Reset & clock
control (RCC)
GPOC
USART1
SP1
TM1
ADC2
ADC1
GPOE
GPOD
GPOB
GPOA
EXT
AFO
DAC SP3/2S
TM2
PWR
BKP
CAN1
CAN2
2C2
2C1
UART5
UART4
USART3
USART2
SP2/2S
WDG
WWDG
RTC
TM7
TM6
TM5
TM4
TM3
USB OTG FS
Ethernet MAC
D
M
A
RM0008 Direct memory access controller (DMA)
Doc ID 13902 Rev 13 267/1093

Figure 49. DMA block diagram in low-, medium- high- and XL-density devices
1. The DMA2 controller is available only in high-density and XL-density devices.
1. ADC3, SPI/I2S3, UART4, SDIO, TIM5, TIM6, DAC, TIM7, TIM8 DMA requests are available only in high-
density devices
13.3 DMA functional description
The DMA controller performs direct memory transfer by sharing the system bus with the
Cortex-M3 core. The DMA request may stop the CPU access to the system bus for some
bus cycles, when the CPU and DMA are targeting the same destination (memory or
peripheral). The bus matrix implements round-robin scheduling, thus ensuring at least half
of the system bus bandwidth (both to memory and peripheral) for the CPU.
13.3.1 DMA transactions
After an event, the peripheral sends a request signal to the DMA Controller. The DMA
controller serves the request depending on the channel priorities. As soon as the DMA
Controller accesses the peripheral, an Acknowledge is sent to the peripheral by the DMA
Controller. The peripheral releases its request as soon as it gets the Acknowledge from the
DMA Controller. Once the request is deasserted by the peripheral, the DMA Controller
release the Acknowledge. If there are more requests, the peripheral can initiate the next
transaction.
FLITF
Ch.1
Ch.2
Ch.7
Arbiter
Cortex-M3
SRAM
AHB Slave
DMA1
ICode
DCode
System
DMA request
APB2
Flash
Bridge 2
Bridge 1
USART1
SPI1
ADC1
ADC3
USART2
USART3
UART4
I2C2
I2C1
TIM2
TIM3
TIM4
Ch.1
Ch.2
Ch.5
Arbiter
AHB Slave
DMA2
FSMC
SDIO
APB1
DMA request
TIM1 SPI/I2S3
SPI/I2S2
TIM8
TIM5
TIM6
TIM7
ai14801b
DMA request
B
u
s

m
a
t
r
i
x
DMA
D
M
A
Reset & clock control
(RCC)
AHB System

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268/1093 Doc ID 13902 Rev 13
In summary, each DMA transfer consists of three operations:
The loading of data from the peripheral data register or a location in memory
addressed through an internal current peripheral/memory address register. The start
address used for the first transfer is the base peripheral/memory address programmed
in the DMA_CPARx or DMA_CMARx register
The storage of the data loaded to the peripheral data register or a location in memory
addressed through an internal current peripheral/memory address register. The start
address used for the first transfer is the base peripheral/memory address programmed
in the DMA_CPARx or DMA_CMARx register
The post-decrementing of the DMA_CNDTRx register, which contains the number of
transactions that have still to be performed.
13.3.2 Arbiter
The arbiter manages the channel requests based on their priority and launches the
peripheral/memory access sequences.
The priorities are managed in two stages:
Software: each channel priority can be configured in the DMA_CCRx register. There
are four levels:
Very high priority
High priority
Medium priority
Low priority
Hardware: if 2 requests have the same software priority level, the channel with the
lowest number will get priority versus the channel with the highest number. For
example, channel 2 gets priority over channel 4.
Note: In high-density, XL-density and connectivity line devices, the DMA1 controller has priority
over the DMA2 controller.
13.3.3 DMA channels
Each channel can handle DMA transfer between a peripheral register located at a fixed
address and a memory address. The amount of data to be transferred (up to 65535) is
programmable. The register which contains the amount of data items to be transferred is
decremented after each transaction.
Programmable data sizes
Transfer data sizes of the peripheral and memory are fully programmable through the PSIZE
and MSIZE bits in the DMA_CCRx register.
Pointer incrementation
Peripheral and memory pointers can optionally be automatically post-incremented after
each transaction depending on the PINC and MINC bits in the DMA_CCRx register. If
incremented mode is enabled, the address of the next transfer will be the address of the
previous one incremented by 1, 2 or 4 depending on the chosen data size. The first transfer
address is the one programmed in the DMA_CPARx/DMA_CMARx registers. During
transfer operations, these registers keep the initially programmed value. The current transfer
RM0008 Direct memory access controller (DMA)
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addresses (in the current internal peripheral/memory address register) are not accessible by
software.
If the channel is configured in noncircular mode, no DMA request is served after the last
transfer (that is once the number of data items to be transferred has reached zero). In order
to reload a new number of data items to be transferred into the DMA_CNDTRx register, the
DMA channel must be disabled.
Note: If a DMA channel is disabled, the DMA registers are not reset. The DMA channel registers
(DMA_CCRx, DMA_CPARx and DMA_CMARx) retain the initial values programmed during
the channel configuration phase.
In circular mode, after the last transfer, the DMA_CNDTRx register is automatically reloaded
with the initially programmed value. The current internal address registers are reloaded with
the base address values from the DMA_CPARx/DMA_CMARx registers.
Channel configuration procedure
The following sequence should be followed to configure a DMA channelx (where x is the
channel number).
1. Set the peripheral register address in the DMA_CPARx register. The data will be
moved from/ to this address to/ from the memory after the peripheral event.
2. Set the memory address in the DMA_CMARx register. The data will be written to or
read from this memory after the peripheral event.
3. Configure the total number of data to be transferred in the DMA_CNDTRx register.
After each peripheral event, this value will be decremented.
4. Configure the channel priority using the PL[1:0] bits in the DMA_CCRx register
5. Configure data transfer direction, circular mode, peripheral & memory incremented
mode, peripheral & memory data size, and interrupt after half and/or full transfer in the
DMA_CCRx register
6. Activate the channel by setting the ENABLE bit in the DMA_CCRx register.
As soon as the channel is enabled, it can serve any DMA request from the peripheral
connected on the channel.
Once half of the bytes are transferred, the half-transfer flag (HTIF) is set and an interrupt is
generated if the Half-Transfer Interrupt Enable bit (HTIE) is set. At the end of the transfer,
the Transfer Complete Flag (TCIF) is set and an interrupt is generated if the Transfer
Complete Interrupt Enable bit (TCIE) is set.
Circular mode
Circular mode is available to handle circular buffers and continuous data flows (e.g. ADC
scan mode). This feature can be enabled using the CIRC bit in the DMA_CCRx register.
When circular mode is activated, the number of data to be transferred is automatically
reloaded with the initial value programmed during the channel configuration phase, and the
DMA requests continue to be served.
Memory-to-memory mode
The DMA channels can also work without being triggered by a request from a peripheral.
This mode is called Memory to Memory mode.
If the MEM2MEM bit in the DMA_CCRx register is set, then the channel initiates transfers as
soon as it is enabled by software by setting the Enable bit (EN) in the DMA_CCRx register.

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The transfer stops once the DMA_CNDTRx register reaches zero. Memory to Memory
mode may not be used at the same time as Circular mode.
13.3.4 Programmable data width, data alignment and endians
When PSIZE and MSIZE are not equal, the DMA performs some data alignments as
described in Table 76: Programmable data width & endian behavior (when bits PINC =
MINC = 1).

Addressing an AHB peripheral that does not support byte or halfword write
operations
When the DMA initiates an AHB byte or halfword write operation, the data are duplicated on
the unused lanes of the HWDATA[31:0] bus. So when the used AHB slave peripheral does
not support byte or halfword write operations (when HSIZE is not used by the peripheral)
Table 76. Programmable data width & endian behavior (when bits PINC = MINC = 1)
Source
port
width
Destination
port width
Number
of data
items to
transfer
(NDT)
Source content:
address / data
Transfer operations
Destination
content:
address / data
8 8 4
@0x0 / B0
@0x1 / B1
@0x2 / B2
@0x3 / B3
1: READ B0[7:0] @0x0 then WRITE B0[7:0] @0x0
2: READ B1[7:0] @0x1 then WRITE B1[7:0] @0x1
3: READ B2[7:0] @0x2 then WRITE B2[7:0] @0x2
4: READ B3[7:0] @0x3 then WRITE B3[7:0] @0x3
@0x0 / B0
@0x1 / B1
@0x2 / B2
@0x3 / B3
8 16 4
@0x0 / B0
@0x1 / B1
@0x2 / B2
@0x3 / B3
1: READ B0[7:0] @0x0 then WRITE 00B0[15:0] @0x0
2: READ B1[7:0] @0x1 then WRITE 00B1[15:0] @0x2
3: READ B3[7:0] @0x2 then WRITE 00B2[15:0] @0x4
4: READ B4[7:0] @0x3 then WRITE 00B3[15:0] @0x6
@0x0 / 00B0
@0x2 / 00B1
@0x4 / 00B2
@0x6 / 00B3
8 32 4
@0x0 / B0
@0x1 / B1
@0x2 / B2
@0x3 / B3
1: READ B0[7:0] @0x0 then WRITE 000000B0[31:0] @0x0
2: READ B1[7:0] @0x1 then WRITE 000000B1[31:0] @0x4
3: READ B3[7:0] @0x2 then WRITE 000000B2[31:0] @0x8
4: READ B4[7:0] @0x3 then WRITE 000000B3[31:0] @0xC
@0x0 / 000000B0
@0x4 / 000000B1
@0x8 / 000000B2
@0xC / 000000B3
16 8 4
@0x0 / B1B0
@0x2 / B3B2
@0x4 / B5B4
@0x6 / B7B6
1: READ B1B0[15:0] @0x0 then WRITE B0[7:0] @0x0
2: READ B3B2[15:0] @0x2 then WRITE B2[7:0] @0x1
3: READ B5B4[15:0] @0x4 then WRITE B4[7:0] @0x2
4: READ B7B6[15:0] @0x6 then WRITE B6[7:0] @0x3
@0x0 / B0
@0x1 / B2
@0x2 / B4
@0x3 / B6
16 16 4
@0x0 / B1B0
@0x2 / B3B2
@0x4 / B5B4
@0x6 / B7B6
1: READ B1B0[15:0] @0x0 then WRITE B1B0[15:0] @0x0
2: READ B3B2[15:0] @0x2 then WRITE B3B2[15:0] @0x2
3: READ B5B4[15:0] @0x4 then WRITE B5B4[15:0] @0x4
4: READ B7B6[15:0] @0x6 then WRITE B7B6[15:0] @0x6
@0x0 / B1B0
@0x2 / B3B2
@0x4 / B5B4
@0x6 / B7B6
16 32 4
@0x0 / B1B0
@0x2 / B3B2
@0x4 / B5B4
@0x6 / B7B6
1: READ B1B0[15:0] @0x0 then WRITE 0000B1B0[31:0] @0x0
2: READ B3B2[15:0] @0x2 then WRITE 0000B3B2[31:0] @0x4
3: READ B5B4[15:0] @0x4 then WRITE 0000B5B4[31:0] @0x8
4: READ B7B6[15:0] @0x6 then WRITE 0000B7B6[31:0] @0xC
@0x0 / 0000B1B0
@0x4 / 0000B3B2
@0x8 / 0000B5B4
@0xC / 0000B7B6
32 8 4
@0x0 / B3B2B1B0
@0x4 / B7B6B5B4
@0x8 / BBBAB9B8
@0xC / BFBEBDBC
1: READ B3B2B1B0[31:0] @0x0 then WRITE B0[7:0] @0x0
2: READ B7B6B5B4[31:0] @0x4 then WRITE B4[7:0] @0x1
3: READ BBBAB9B8[31:0] @0x8 then WRITE B8[7:0] @0x2
4: READ BFBEBDBC[31:0] @0xC then WRITE BC[7:0] @0x3
@0x0 / B0
@0x1 / B4
@0x2 / B8
@0x3 / BC
32 16 4
@0x0 / B3B2B1B0
@0x4 / B7B6B5B4
@0x8 / BBBAB9B8
@0xC / BFBEBDBC
1: READ B3B2B1B0[31:0] @0x0 then WRITE B1B0[7:0] @0x0
2: READ B7B6B5B4[31:0] @0x4 then WRITE B5B4[7:0] @0x1
3: READ BBBAB9B8[31:0] @0x8 then WRITE B9B8[7:0] @0x2
4: READ BFBEBDBC[31:0] @0xC then WRITE BDBC[7:0] @0x3
@0x0 / B1B0
@0x2 / B5B4
@0x4 / B9B8
@0x6 / BDBC
32 32 4
@0x0 / B3B2B1B0
@0x4 / B7B6B5B4
@0x8 / BBBAB9B8
@0xC / BFBEBDBC
1: READ B3B2B1B0[31:0] @0x0 then WRITE B3B2B1B0[31:0] @0x0
2: READ B7B6B5B4[31:0] @0x4 then WRITE B7B6B5B4[31:0] @0x4
3: READ BBBAB9B8[31:0] @0x8 then WRITE BBBAB9B8[31:0] @0x8
4: READ BFBEBDBC[31:0] @0xC then WRITE BFBEBDBC[31:0] @0xC
@0x0 / B3B2B1B0
@0x4 / B7B6B5B4
@0x8 / BBBAB9B8
@0xC / BFBEBDBC
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and does not generate any error, the DMA writes the 32 HWDATA bits as shown in the two
examples below:
To write the halfword 0xABCD, the DMA sets the HWDATA bus to 0xABCDABCD
with HSIZE = HalfWord
To write the byte 0xAB, the DMA sets the HWDATA bus to 0xABABABAB with
HSIZE = Byte
Assuming that the AHB/APB bridge is an AHB 32-bit slave peripheral that does not take the
HSIZE data into account, it will transform any AHB byte or halfword operation into a 32-bit
APB operation in the following manner:
an AHB byte write operation of the data 0xB0 to 0x0 (or to 0x1, 0x2 or 0x3) will be
converted to an APB word write operation of the data 0xB0B0B0B0 to 0x0
an AHB halfword write operation of the data 0xB1B0 to 0x0 (or to 0x2) will be
converted to an APB word write operation of the data 0xB1B0B1B0 to 0x0
For instance, if you want to write the APB backup registers (16-bit registers aligned to a 32-
bit address boundary), you must configure the memory source size (MSIZE) to 16-bit and
the peripheral destination size (PSIZE) to 32-bit.
13.3.5 Error management
A DMA transfer error can be generated by reading from or writing to a reserved address
space. When a DMA transfer error occurs during a DMA read or a write access, the faulty
channel is automatically disabled through a hardware clear of its EN bit in the corresponding
Channel configuration register (DMA_CCRx). The channel's transfer error interrupt flag
(TEIF) in the DMA_IFR register is set and an interrupt is generated if the transfer error
interrupt enable bit (TEIE) in the DMA_CCRx register is set.
13.3.6 Interrupts
An interrupt can be produced on a Half-transfer, Transfer complete or Transfer error for each
DMA channel. Separate interrupt enable bits are available for flexibility.

Note: In high-density and XL-density devices, DMA2 Channel4 and DMA2 Channel5 interrupts are
mapped onto the same interrupt vector. In connectivity line devices, DMA2 Channel4 and
DMA2 Channel5 interrupts have separate interrupt vectors. All other DMA1 and DMA2
Channel interrupts have their own interrupt vector.
Table 77. DMA interrupt requests
Interrupt event Event flag Enable Control bit
Half-transfer HTIF HTIE
Transfer complete TCIF TCIE
Transfer error TEIF TEIE

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13.3.7 DMA request mapping
DMA1 controller
The 7 requests from the peripherals (TIMx[1,2,3,4], ADC1, SPI1, SPI/I2S2, I2Cx[1,2] and
USARTx[1,2,3]) are simply logically ORed before entering the DMA1, this means that only
one request must be enabled at a time. Refer to Figure 50: DMA1 request mapping.
The peripheral DMA requests can be independently activated/de-activated by programming
the DMA control bit in the registers of the corresponding peripheral.
Figure 50. DMA1 request mapping
Fixed hardware priority
Channel 3
internal
HW request 3
High priority
Low priority
Peripheral
Channel 2
HW request 2
Channel 1
SW trigger (MEM2MEM bit)
Channel 1 EN bit
HW request 1
Channel 4
HW request 4
DMA1
Channel 5
HW request 5
Channel 6
HW REQUEST 6
Channel 7
HW request 7
request
ADC1
USART1_TX
TIM1_CH4
SPI1_TX
USART3_TX
USART1_RX
TIM1_UP
I2C1_TX
TIM3_CH1
I2C1_RX
TIM2_CH2
SPI1_RX
TIM1_CH2
TIM4_CH3
TIM2_CH1
SPI/I2S2_TX
I2C2_RX
USART2_RX
TIM3_TRIG
TIM1_CH3
USART2_TX
TIM2_CH4
TIM4_UP
SPI/I2S2_RX
I2C2_TX
TIM1_TRIG
TIM4_CH2
TIM3_CH4
TIM3_UP
USART3_RX
TIM3_CH3
TIM1_CH1
TIM2_UP
TIM2_CH3
TIM4_CH1
Channel 2 EN bit
Channel 3 EN bit
Channel 4 EN bit
Channel 5 EN bit
Channel 6 EN bit
Channel 7 EN bit
SW trigger (MEM2MEM bit)
SW trigger (MEM2MEM bit)
SW trigger (MEM2MEM bit)
SW trigger (MEM2MEM bit)
SW TRIGGER (MEM2MEM bit)
SW trigger (MEM2MEM bit)
request signals
TIM1_COM
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Table 78 lists the DMA requests for each channel.

DMA2 controller
The 5 requests from the peripherals (TIMx[5,6,7,8], ADC3, SPI/I2S3, UART4,
DAC_Channel[1,2] and SDIO) are simply logically ORed before entering the DMA2, this
means that only one request must be enabled at a time. Refer to Figure 51: DMA2 request
mapping.
The peripheral DMA requests can be independently activated/de-activated by programming
the DMA control bit in the registers of the corresponding peripheral.
Note: The DMA2 controller and its relative requests are available only in high-density, XL-density
and connectivity line devices.
Table 78. Summary of DMA1 requests for each channel
Peripherals Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7
ADC1 ADC1
SPI/I
2
S SPI1_RX SPI1_TX
SPI2/I2S2_R
X
SPI2/I2S2_T
X
USART USART3_TX USART3_RX USART1_TX USART1_RX USART2_RX USART2_TX
I
2
C I2C2_TX I2C2_RX I2C1_TX I2C1_RX
TIM1 TIM1_CH1 TIM1_CH2
TIM1_CH4
TIM1_TRIG
TIM1_COM
TIM1_UP TIM1_CH3
TIM2 TIM2_CH3 TIM2_UP TIM2_CH1
TIM2_CH2
TIM2_CH4
TIM3 TIM3_CH3
TIM3_CH4
TIM3_UP
TIM3_CH1
TIM3_TRIG
TIM4 TIM4_CH1 TIM4_CH2 TIM4_CH3 TIM4_UP

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Figure 51. DMA2 request mapping
Table 79 lists the DMA2 requests for each channel.

13.4 DMA registers
Refer to Section 2.1 on page 46 for a list of abbreviations used in register descriptions.
Table 79. Summary of DMA2 requests for each channel
Peripherals Channel 1 Channel 2 Channel 3 Channel 4 Channel 5
ADC3
(1)
1. ADC3, SDIO and TIM8 DMA requests are available only in high-density and XL-density devices.
ADC3
SPI/I2S3 SPI/I2S3_RX SPI/I2S3_TX
UART4 UART4_RX UART4_TX
SDIO
(1)
SDIO
TIM5
TIM5_CH4
TIM5_TRIG
TIM5_CH3
TIM5_UP
TIM5_CH2 TIM5_CH1
TIM6/
DAC_Channel1

TIM6_UP/
DAC_Channel1

AES AES_OUT AES_IN
Fixed hardware priority
Channel 3
internal
HW request 3
HIGH PRIORITY
LOW PRIORITY
Peripheral request signals
Channel 2
HW request 2
Channel 1
SW trigger (MEM2MEM bit)
Channel 1 EN bit
HW request 1
Channel 4
HW request 4
DMA2
Channel 5
HW request 5
request
TIM5_CH2
SDIO
TIM5_CH4
TIM8_UP
TIM7_UP/DAC_Channel2
TIM8_CH3
TIM5_TRIG
Channel 2 EN bit
Channel 3 EN bit
Channel 4 EN bit
Channel 5 EN bit
SW trigger (MEM2MEM bit)
SW trigger (MEM2MEM bit)
SW trigger (MEM2MEM bit)
SW trigger (MEM2MEM bit)
SPI/I2S3_RX
TIM8_CH4
TIM5_UP
TIM5_CH3
TIM8_TRIG
TIM8_COM
SPI/I2S3_TX
TIM8_CH1
UART4_RX
TIM6_UP/DAC_Channel1
ADC3
UART4_TX
TIM8_CH2
TIM5_CH1
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Note: In the following registers, all bits related to channel6 and channel7 are not relevant for DMA2
since it has only 5 channels.
The peripheral registers can be accessed by bytes (8-bit), half-words (16-bit) or words (32-
bit).
13.4.1 DMA interrupt status register (DMA_ISR)
Address offset: 0x00
Reset value: 0x0000 0000


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
TEIF7 HTIF7 TCIF7 GIF7 TEIF6 HTIF6 TCIF6 GIF6 TEIF5 HTIF5 TCIF5 GIF5
r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TEIF4 HTIF4 TCIF4 GIF4 TEIF3 HTIF3 TCIF3 GIF3 TEIF2 HTIF2 TCIF2 GIF2 TEIF1 HTIF1 TCIF1 GIF1
r r r r r r r r r r r r r r r r
Bits 31:28 Reserved, must be kept at reset value.
Bits 27, 23, 19, 15,
11, 7, 3
TEIFx: Channel x transfer error flag (x = 1 ..7)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_IFCR register.
0: No transfer error (TE) on channel x
1: A transfer error (TE) occurred on channel x
Bits 26, 22, 18, 14,
10, 6, 2
HTIFx: Channel x half transfer flag (x = 1 ..7)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_IFCR register.
0: No half transfer (HT) event on channel x
1: A half transfer (HT) event occurred on channel x
Bits 25, 21, 17, 13,
9, 5, 1
TCIFx: Channel x transfer complete flag (x = 1 ..7)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_IFCR register.
0: No transfer complete (TC) event on channel x
1: A transfer complete (TC) event occurred on channel x
Bits 24, 20, 16, 12,
8, 4, 0
GIFx: Channel x global interrupt flag (x = 1 ..7)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_IFCR register.
0: No TE, HT or TC event on channel x
1: A TE, HT or TC event occurred on channel x

Direct memory access controller (DMA) RM0008
276/1093 Doc ID 13902 Rev 13
13.4.2 DMA interrupt flag clear register (DMA_IFCR)
Address offset: 0x04
Reset value: 0x0000 0000


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
CTEIF7 CHTIF7 CTCIF7 CGIF7 CTEIF6 CHTIF6 CTCIF6 CGIF6 CTEIF5 CHTIF5 CTCIF5 CGIF5
w w w w w w w w w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTEIF4 CHTIF4 CTCIF4 CGIF4 CTEIF3 CHTIF3 CTCIF3 CGIF3 CTEIF2 CHTIF2 CTCIF2 CGIF2 CTEIF1 CHTIF1 CTCIF1 CGIF1
w w w w w w w w w w w w w w w w
Bits 31:28 Reserved, must be kept at reset value.
Bits 27, 23, 19, 15,
11, 7, 3
CTEIFx: Channel x transfer error clear (x = 1 ..7)
This bit is set and cleared by software.
0: No effect
1: Clears the corresponding TEIF flag in the DMA_ISR register
Bits 26, 22, 18, 14,
10, 6, 2
CHTIFx: Channel x half transfer clear (x = 1 ..7)
This bit is set and cleared by software.
0: No effect
1: Clears the corresponding HTIF flag in the DMA_ISR register
Bits 25, 21, 17, 13,
9, 5, 1
CTCIFx: Channel x transfer complete clear (x = 1 ..7)
This bit is set and cleared by software.
0: No effect
1: Clears the corresponding TCIF flag in the DMA_ISR register
Bits 24, 20, 16, 12,
8, 4, 0
CGIFx: Channel x global interrupt clear (x = 1 ..7)
This bit is set and cleared by software.
0: No effect
1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register
RM0008 Direct memory access controller (DMA)
Doc ID 13902 Rev 13 277/1093

13.4.3 DMA channel x configuration register (DMA_CCRx) (x = 1..7,
where x = channel number)
Address offset: 0x08 + 0d20 (channel number 1)
Reset value: 0x0000 0000


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res.
MEM2
MEM
PL[1:0] MSIZE[1:0] PSIZE[1:0] MINC PINC CIRC DIR TEIE HTIE TCIE EN
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:15 Reserved, must be kept at reset value.
Bit 14 MEM2MEM: Memory to memory mode
This bit is set and cleared by software.
0: Memory to memory mode disabled
1: Memory to memory mode enabled
Bits 13:12 PL[1:0]: Channel priority level
These bits are set and cleared by software.
00: Low
01: Medium
10: High
11: Very high
Bits 11:10 MSIZE[1:0]: Memory size
These bits are set and cleared by software.
00: 8-bits
01: 16-bits
10: 32-bits
11: Reserved
Bits 9:8 PSIZE[1:0]: Peripheral size
These bits are set and cleared by software.
00: 8-bits
01: 16-bits
10: 32-bits
11: Reserved
Bit 7 MINC: Memory increment mode
This bit is set and cleared by software.
0: Memory increment mode disabled
1: Memory increment mode enabled
Bit 6 PINC: Peripheral increment mode
This bit is set and cleared by software.
0: Peripheral increment mode disabled
1: Peripheral increment mode enabled
Bit 5 CIRC: Circular mode
This bit is set and cleared by software.
0: Circular mode disabled
1: Circular mode enabled

Direct memory access controller (DMA) RM0008
278/1093 Doc ID 13902 Rev 13
13.4.4 DMA channel x number of data register (DMA_CNDTRx) (x = 1..7),
where x = channel number)
Address offset: 0x0C + 0d20 (channel number 1)
Reset value: 0x0000 0000


Bit 4 DIR: Data transfer direction
This bit is set and cleared by software.
0: Read from peripheral
1: Read from memory
Bit 3 TEIE: Transfer error interrupt enable
This bit is set and cleared by software.
0: TE interrupt disabled
1: TE interrupt enabled
Bit 2 HTIE: Half transfer interrupt enable
This bit is set and cleared by software.
0: HT interrupt disabled
1: HT interrupt enabled
Bit 1 TCIE: Transfer complete interrupt enable
This bit is set and cleared by software.
0: TC interrupt disabled
1: TC interrupt enabled
Bit 0 EN: Channel enable
This bit is set and cleared by software.
0: Channel disabled
1: Channel enabled
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 NDT[15:0]: Number of data to transfer
Number of data to be transferred (0 up to 65535). This register can only be written when the
channel is disabled. Once the channel is enabled, this register is read-only, indicating the
remaining bytes to be transmitted. This register decrements after each DMA transfer.
Once the transfer is completed, this register can either stay at zero or be reloaded
automatically by the value previously programmed if the channel is configured in auto-reload
mode.
If this register is zero, no transaction can be served whether the channel is enabled or not.
RM0008 Direct memory access controller (DMA)
Doc ID 13902 Rev 13 279/1093

13.4.5 DMA channel x peripheral address register (DMA_CPARx) (x = 1..7),
where x = channel number)
Address offset: 0x10 + 0d20 (channel number 1)
Reset value: 0x0000 0000
This register must not be written when the channel is enabled.


13.4.6 DMA channel x memory address register (DMA_CMARx) (x = 1..7),
where x = channel number)
Address offset: 0x14 + 0d20 (channel number 1)
Reset value: 0x0000 0000
This register must not be written when the channel is enabled.


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:0 PA[31:0]: Peripheral address
Base address of the peripheral data register from/to which the data will be read/written.
When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a half-
word address.
When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word
address.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:0 MA[31:0]: Memory address
Base address of the memory area from/to which the data will be read/written.
When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a
half-word address.
When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word
address.

Direct memory access controller (DMA) RM0008
280/1093 Doc ID 13902 Rev 13
13.4.7 DMA register map
The following table gives the DMA register map and the reset values.

Table 80. DMA register map and reset values
Offset Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9 8 7 6 5 4 3 2 1 0
0x000
DMA_ISR
Reserved
T
E
I
F
7
H
T
I
F
7

T
C
I
F
7
G
I
F
7
T
E
I
F
6
H
T
I
F
6

T
C
I
F
6
G
I
F
6
T
E
I
F
5
H
T
I
F
5

T
C
I
F
5
G
I
F
5
T
E
I
F
4
H
T
I
F
4

T
C
I
F
4
G
I
F
4
T
E
I
F
3
H
T
I
F
3

T
C
I
F
3
G
I
F
3
T
E
I
F
2
H
T
I
F
2

T
C
I
F
2
G
I
F
2
T
E
I
F
1
H
T
I
F
1

T
C
I
F
1
G
I
F
1
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x004
DMA_IFCR
Reserved
C
T
E
I
F
7
C
H
T
I
F
7

C
T
C
I
F
7
C
G
I
F
7
C
T
E
I
F
6
C
H
T
I
F
6

C
T
C
I
F
6
C
G
I
F
6
C
T
E
I
F
5
C
H
T
I
F
5

C
T
C
I
F
5
C
G
I
F
5
C
T
E
I
F
4
C
H
T
I
F
4

C
T
C
I
F
4
C
G
I
F
4
C
T
E
I
F
3
C
H
T
I
F
3

C
T
C
I
F
3
C
G
I
F
3
C
T
E
I
F
2
C
H
T
I
F
2

C
T
C
I
F
2
C
G
I
F
2
C
T
E
I
F
1
C
H
T
I
F
1

C
T
C
I
F
1
C
G
I
F
1
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x008
DMA_CCR1
Reserved
M
E
M
2
M
E
M
PL
[1:0]
M

S
I
Z
E

[
1
:
0
]
P
S
I
Z
E

[
1
:
0
]
M
I
N
C
P
I
N
C
C
I
R
C
D
I
R
T
E
I
E
H
T
I
E
T
C
I
E
E
N
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x00C
DMA_CNDTR1
Reserved
NDT[15:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x010
DMA_CPAR1 PA[31:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x014
DMA_CMAR1 MA[31:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x018 Reserved
0x01C
DMA_CCR2
Reserved
M
E
M
2
M
E
M
PL
[1:0]
M

S
I
Z
E

[
1
:
0
]
P
S
I
Z
E

[
1
:
0
]
M
I
N
C
P
I
N
C
C
I
R
C
D
I
R
T
E
I
E
H
T
I
E
T
C
I
E
E
N
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x020
DMA_CNDTR2
Reserved
NDT[15:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x024
DMA_CPAR2 PA[31:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x028
DMA_CMAR2 MA[31:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x02C Reserved
0x030
DMA_CCR3
Reserved
M
E
M
2
M
E
M
PL
[1:0]
M

S
I
Z
E

[
1
:
0
]
P
S
I
Z
E

[
1
:
0
]
M
I
N
C
P
I
N
C
C
I
R
C
D
I
R
T
E
I
E
H
T
I
E
T
C
I
E
E
N
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x034
DMA_CNDTR3
Reserved
NDT[15:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x038
DMA_CPAR3 PA[31:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x03C
DMA_CMAR3 MA[31:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x040 Reserved
0x044
DMA_CCR4
Reserved
M
E
M
2
M
E
M
PL
[1:0]
M

S
I
Z
E

[
1
:
0
]
P
S
I
Z
E

[
1
:
0
]
M
I
N
C
P
I
N
C
C
I
R
C
D
I
R
T
E
I
E
H
T
I
E
T
C
I
E
E
N
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x048
DMA_CNDTR4
Reserved
NDT[15:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RM0008 Direct memory access controller (DMA)
Doc ID 13902 Rev 13 281/1093

Refer to for the register boundary addresses.
0x04C
DMA_CPAR4 PA[31:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x050
DMA_CMAR4 MA[31:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x054 Reserved
0x058
DMA_CCR5
Reserved
M
E
M
2
M
E
M
PL
[1:0]
M

S
I
Z
E

[
1
:
0
]
P
S
I
Z
E

[
1
:
0
]
M
I
N
C
P
I
N
C
C
I
R
C
D
I
R
T
E
I
E
H
T
I
E
T
C
I
E
E
N
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x05C
DMA_CNDTR5
Reserved
NDT[15:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x060
DMA_CPAR5 PA[31:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x064
DMA_CMAR5 MA[31:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x068 Reserved
0x06C
DMA_CCR6
Reserved
M
E
M
2
M
E
M
PL
[1:0]
M

S
I
Z
E

[
1
:
0
]
P
S
I
Z
E

[
1
:
0
]
M
I
N
C
P
I
N
C
C
I
R
C
D
I
R
T
E
I
E
H
T
I
E
T
C
I
E
E
N
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x070
DMA_CNDTR6
Reserved
NDT[15:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x074
DMA_CPAR6 PA[31:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x078
DMA_CMAR6 MA[31:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x07C Reserved
0x080
DMA_CCR7
Reserved
M
E
M
2
M
E
M
PL
[1:0]
M

S
I
Z
E

[
1
:
0
]
P
S
I
Z
E

[
1
:
0
]
M
I
N
C
P
I
N
C
C
I
R
C
D
I
R
T
E
I
E
H
T
I
E
T
C
I
E
E
N
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x084
DMA_CNDTR7
Reserved
NDT[15:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x088
DMA_CPAR7 PA[31:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x08C
DMA_CMAR7 MA[31:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x090 Reserved
Table 80. DMA register map and reset values (continued)
Offset Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9 8 7 6 5 4 3 2 1 0

Advanced-control timers (TIM1&TIM8) RM0008
282/1093 Doc ID 13902 Rev 13
14 Advanced-control timers (TIM1&TIM8)
Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx
microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx
microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
High-density devices are STM32F101xx and STM32F103xx microcontrollers where the
Flash memory density ranges between 256 and 512 Kbytes.
XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the
Flash memory density ranges between 768 Kbytes and 1 Mbyte.
Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
Low- and medium-density STM32F103xx devices, and the STM32F105xx/STM32F107xx
connectivity line devices, contain one advanced-control timer (TIM1) whereas high-density
and XL-density STM32F103xx devices feature two advance-control timers (TIM1 and TIM8).
14.1 TIM1&TIM8 introduction
The advanced-control timers (TIM1&TIM8) consist of a 16-bit auto-reload counter driven by
a programmable prescaler.
It may be used for a variety of purposes, including measuring the pulse lengths of input
signals (input capture) or generating output waveforms (output compare, PWM,
complementary PWM with dead-time insertion).
Pulse lengths and waveform periods can be modulated from a few microseconds to several
milliseconds using the timer prescaler and the RCC clock controller prescalers.
The advanced-control (TIM1&TIM8) and general-purpose (TIMx) timers are completely
independent, and do not share any resources. They can be synchronized together as
described in Section 14.3.20.
RM0008 Advanced-control timers (TIM1&TIM8)
Doc ID 13902 Rev 13 283/1093

14.2 TIM1&TIM8 main features
TIM1&TIM8 timer features include:
16-bit up, down, up/down auto-reload counter.
16-bit programmable prescaler allowing dividing (also on the fly) the counter clock
frequency either by any factor between 1 and 65535.
Up to 4 independent channels for:
Input Capture
Output Compare
PWM generation (Edge and Center-aligned Mode)
One-pulse mode output
Complementary outputs with programmable dead-time
Synchronization circuit to control the timer with external signals and to interconnect
several timers together.
Repetition counter to update the timer registers only after a given number of cycles of
the counter.
Break input to put the timers output signals in reset state or in a known state.
Interrupt/DMA generation on the following events:
Update: counter overflow/underflow, counter initialization (by software or
internal/external trigger)
Trigger event (counter start, stop, initialization or count by internal/external trigger)
Input capture
Output compare
Break input
Supports incremental (quadrature) encoder and hall-sensor circuitry for positioning
purposes
Trigger input for external clock or cycle-by-cycle current management

Advanced-control timers (TIM1&TIM8) RM0008
284/1093 Doc ID 13902 Rev 13
Figure 52. Advanced-control timer block diagram
Prescaler
AutoReload Register
COUNTER
Capture/Compare 1 Register
Capture/Compare 2 Register
U
U
U
CC1I
CC2I
ETR
Trigger
Controller
+/-
Stop, Clear or Up/Down
TI1FP1
TI2FP2
ITR0
ITR1
ITR2
TRGI
Controller
Encoder
Interface
Capture/Compare 3 Register
U
CC3I
output
control
DTG
DTG registers
TRGO
OC1REF
OC2REF
OC3REF
REP Register
U
Repetition
counter
UI
Reset, Enable, Up/Down, Count
Capture/Compare 4 Register
U
CC4I
OC4REF
CK_PSC
TI4
Prescaler
Prescaler
IC4PS
IC3PS
IC1
IC2
Prescaler
Prescaler
Input Filter &
Edge detector
IC2PS
IC1PS
TI1FP1
output
control
DTG
output
control
DTG
output
control
Reg
event
Notes:
Preload registers transferred
to active registers on U event
according to control bit
interrupt & DMA output
Input Filter
Polarity Selection & Edge
Detector & Prescaler
ETRP
TGI
TRC
TRC
IC3
IC4
ITR
ETRF
TRC
TI1F_ED
Input Filter &
Edge detector
Input Filter &
Edge detector
Input Filter &
Edge detector
CC1I
CC2I
CC3I
CC4I
TI1FP2
TI2FP1
TI2FP2
TI3FP3
TRC
TRC
TI3FP4
TI4FP3
TI4FP4
BI
TI3
TI1
TI2
XOR
TIMx_CH1
TIMx_CH2
TIMx_CH3
TIMx_CH4
BRK
TIMx_BKIN
OC1
OC2
OC3
TIMx_CH1
TIMx_CH2
TIMx_CH3
TIMx_CH3N
OC3N
TIMx_CH2N
OC2N
TIMx_CH1N
OC1N
OC4
TIMx_CH4
TIMx_ETR
to other timers
Mode
Slave
PSC CNT
Internal Clock (CK_INT)
CK_CNT
ETRF
Clock failure event from clock controller
Polarity Selection
CSS (Clock Security system
CK_TIM18 from RCC
to DAC/ADC
ITR3
RM0008 Advanced-control timers (TIM1&TIM8)
Doc ID 13902 Rev 13 285/1093

14.3 TIM1&TIM8 functional description
14.3.1 Time-base unit
The main block of the programmable advanced-control timer is a 16-bit counter with its
related auto-reload register. The counter can count up, down or both up and down. The
counter clock can be divided by a prescaler.
The counter, the auto-reload register and the prescaler register can be written or read by
software. This is true even when the counter is running.
The time-base unit includes:
Counter register (TIMx_CNT)
Prescaler register (TIMx_PSC)
Auto-reload register (TIMx_ARR)
Repetition counter register (TIMx_RCR)
The auto-reload register is preloaded. Writing to or reading from the auto-reload register
accesses the preload register. The content of the preload register are transferred into the
shadow register permanently or at each update event (UEV), depending on the auto-reload
preload enable bit (ARPE) in TIMx_CR1 register. The update event is sent when the counter
reaches the overflow (or underflow when downcounting) and if the UDIS bit equals 0 in the
TIMx_CR1 register. It can also be generated by software. The generation of the update
event is described in detailed for each configuration.
The counter is clocked by the prescaler output CK_CNT, which is enabled only when the
counter enable bit (CEN) in TIMx_CR1 register is set (refer also to the slave mode controller
description to get more details on counter enabling).
Note that the counter starts counting 1 clock cycle after setting the CEN bit in the TIMx_CR1
register.
Prescaler description
The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It
is based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register).
It can be changed on the fly as this control register is buffered. The new prescaler ratio is
taken into account at the next update event.
Figure 54 and Figure 55 give some examples of the counter behavior when the prescaler
ratio is changed on the fly:

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Figure 53. Counter timing diagram with prescaler division change from 1 to 2
Figure 54. Counter timing diagram with prescaler division change from 1 to 4
14.3.2 Counter modes
Upcounting mode
In upcounting mode, the counter counts from 0 to the auto-reload value (content of the
TIMx_ARR register), then restarts from 0 and generates a counter overflow event.
If the repetition counter is used, the update event (UEV) is generated after upcounting is
repeated for the number of times programmed in the repetition counter register
(TIMx_RCR). Else the update event is generated at each counter overflow.
Setting the UG bit in the TIMx_EGR register (by software or by using the slave mode
controller) also generates an update event.
The UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1
register. This is to avoid updating the shadow registers while writing new values in the
CK_PSC
00
CEN
Timer clock = CK_CNT
Counter register
Update event (UEV)
0
F9 FA FB FC F7
Prescaler control register 0 1
Write a new value in TIMx_PSC
01 02 03
Prescaler buffer 0 1
Prescaler counter 0 1 0 1 0 1 0 1
F8
CK_PSC
00
CEN
Timer clock = CK_CNT
Counter register
Update event (UEV)
0
F9 FA FB FC F7
Prescaler control register 0 3
Write a new value in TIMx_PSC
Prescaler buffer 0 3
Prescaler counter 0 1 2 3 0 1 2 3
F8 01
RM0008 Advanced-control timers (TIM1&TIM8)
Doc ID 13902 Rev 13 287/1093

preload registers. Then no update event occurs until the UDIS bit has been written to 0.
However, the counter restarts from 0, as well as the counter of the prescaler (but the
prescale rate does not change). In addition, if the URS bit (update request selection) in
TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without
setting the UIF flag (thus no interrupt or DMA request is sent). This is to avoid generating
both update and capture interrupts when clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIMx_SR register) is set (depending on the URS bit):
The repetition counter is reloaded with the content of TIMx_RCR register,
The auto-reload shadow register is updated with the preload value (TIMx_ARR),
The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC
register).
The following figures show some examples of the counter behavior for different clock
frequencies when TIMx_ARR=0x36.
Figure 55. Counter timing diagram, internal clock divided by 1
Figure 56. Counter timing diagram, internal clock divided by 2
CK_PSC
00
CNT_EN
Timer clock = CK_CNT
Counter register
Update interrupt flag (UIF)
Counter overflow
Update event (UEV)
01 02 03 04 05 06 07 32 33 34 35 36 31
CK_PSC
0035 0000 0001 0002 0003
CNT_EN
Timer clock = CK_CNT
Counter register
Update interrupt flag (UIF)
0034 0036
Counter overflow
Update event (UEV)

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Figure 57. Counter timing diagram, internal clock divided by 4
Figure 58. Counter timing diagram, internal clock divided by N
Figure 59. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not
preloaded)
CK_PSC
0000 0001
CNT_EN
Timer clock = CK_CNT
Counter register
Update interrupt flag (UIF)
0035 0036
Counter overflow
Update event (UEV)
Timer clock = CK_CNT
Counter register 00 1F 20
Update interrupt flag (UIF)
Counter overflow
Update event (UEV)
CK_PSC
CK_PSC
00
CEN
Timer clock = CK_CNT
Counter register
Update interrupt flag (UIF)
Counter overflow
Update event (UEV)
01 02 03 04 05 06 07 32 33 34 35 36 31
Auto-reload register FF 36
Write a new value in TIMx_ARR
RM0008 Advanced-control timers (TIM1&TIM8)
Doc ID 13902 Rev 13 289/1093

Figure 60. Counter timing diagram, update event when ARPE=1
(TIMx_ARR preloaded)
Downcounting mode
In downcounting mode, the counter counts from the auto-reload value (content of the
TIMx_ARR register) down to 0, then restarts from the auto-reload value and generates a
counter underflow event.
If the repetition counter is used, the update event (UEV) is generated after downcounting is
repeated for the number of times programmed in the repetition counter register
(TIMx_RCR). Else the update event is generated at each counter underflow.
Setting the UG bit in the TIMx_EGR register (by software or by using the slave mode
controller) also generates an update event.
The UEV update event can be disabled by software by setting the UDIS bit in TIMx_CR1
register. This is to avoid updating the shadow registers while writing new values in the
preload registers. Then no update event occurs until UDIS bit has been written to 0.
However, the counter restarts from the current auto-reload value, whereas the counter of the
prescaler restarts from 0 (but the prescale rate doesnt change).
In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the
UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or
DMA request is sent). This is to avoid generating both update and capture interrupts when
clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIMx_SR register) is set (depending on the URS bit):
The repetition counter is reloaded with the content of TIMx_RCR register
The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC
register)
The auto-reload active register is updated with the preload value (content of the
TIMx_ARR register). Note that the auto-reload is updated before the counter is
reloaded, so that the next period is the expected one
CK_PSC
00
CEN
Timer clock = CK_CNT
Counter register
Update interrupt flag (UIF)
Counter overflow
Update event (UEV)
01 02 03 04 05 06 07 F1 F2 F3 F4 F5 F0
Auto-reload preload register F5 36
Auto-reload shadow register F5 36
Write a new value in TIMx_ARR

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The following figures show some examples of the counter behavior for different clock
frequencies when TIMx_ARR=0x36.
Figure 61. Counter timing diagram, internal clock divided by 1
Figure 62. Counter timing diagram, internal clock divided by 2
Figure 63. Counter timing diagram, internal clock divided by 4
CK_PSC
36
CNT_EN
Timer clock = CK_CNT
Counter register
Update interrupt flag (UIF)
Counter underflow (cnt_udf)
Update event (UEV)
35 34 33 32 31 30 2F 04 03 02 01 00 05
CK_PSC
0001 0036 0035 0034 0033
CNT_EN
Timer clock = CK_CNT
Counter register
Update interrupt flag (UIF)
0002 0000
Counter underflow
Update event (UEV)
CK_PSC
0036 0035
CNT_EN
Timer clock = CK_CNT
Counter register
Update interrupt flag (UIF)
0001 0000
Counter underflow
Update event (UEV)
RM0008 Advanced-control timers (TIM1&TIM8)
Doc ID 13902 Rev 13 291/1093

Figure 64. Counter timing diagram, internal clock divided by N
Figure 65. Counter timing diagram, update event when repetition counter
is not used
Center-aligned mode (up/down counting)
In center-aligned mode, the counter counts from 0 to the auto-reload value (content of the
TIMx_ARR register) 1, generates a counter overflow event, then counts from the auto-
reload value down to 1 and generates a counter underflow event. Then it restarts counting
from 0.
Center-aligned mode is active when the CMS bits in TIMx_CR1 register are not equal to
'00'. The Output compare interrupt flag of channels configured in output is set when: the
counter counts down (Center aligned mode 1, CMS = "01"), the counter counts up (Center
aligned mode 2, CMS = "10") the counter counts up and down (Center aligned mode 3,
CMS = "11").
In this mode, the DIR direction bit in the TIMx_CR1 register cannot be written. It is updated
by hardware and gives the current direction of the counter.
The update event can be generated at each counter overflow and at each counter underflow
or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode
controller) also generates an update event. In this case, the counter restarts counting from
0, as well as the counter of the prescaler.
Timer clock = CK_CNT
Counter register 36 20 1F
Update interrupt flag (UIF)
Counter underflow
Update event (UEV)
CK_PSC
00
CK_PSC
36
CEN
Timer clock = CK_CNT
Counter register
Update interrupt flag (UIF)
Counter underflow
Update event (UEV)
35 34 33 32 31 30 2F 04 03 02 01 00 05
Auto-reload register FF 36
Write a new value in TIMx_ARR

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The UEV update event can be disabled by software by setting the UDIS bit in the TIMx_CR1
register. This is to avoid updating the shadow registers while writing new values in the
preload registers. Then no update event occurs until UDIS bit has been written to 0.
However, the counter continues counting up and down, based on the current auto-reload
value.
In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the
UG bit generates an UEV update event but without setting the UIF flag (thus no interrupt or
DMA request is sent). This is to avoid generating both update and capture interrupts when
clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIMx_SR register) is set (depending on the URS bit):
The repetition counter is reloaded with the content of TIMx_RCR register
The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC
register)
The auto-reload active register is updated with the preload value (content of the
TIMx_ARR register). Note that if the update source is a counter overflow, the auto-
reload is updated before the counter is reloaded, so that the next period is the expected
one (the counter is loaded with the new value).
The following figures show some examples of the counter behavior for different clock
frequencies.
Figure 66. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6
1. Here, center-aligned mode 1 is used (for more details refer to Section 14.4: TIM1&TIM8 registers on page 323).
CK_PSC
02
CNT_EN
Timer clock = CK_CNT
Counter register
Update interrupt flag (UIF)
Counter underflow
Update event (UEV)
03 04 05 06 05 04 03 03 02 01 00 01 04
Counter overflow

RM0008 Advanced-control timers (TIM1&TIM8)
Doc ID 13902 Rev 13 293/1093

Figure 67. Counter timing diagram, internal clock divided by 2
Figure 68. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36
1. Center-aligned mode 2 or 3 is used with an UIF on overflow.
Figure 69. Counter timing diagram, internal clock divided by N
CK_PSC
0002 0000 0001 0002 0003
CNT_EN
Timer clock = CK_CNT
Counter register
Update interrupt flag (UIF)
0003 0001
Counter underflow
Update event (UEV)
CK_PSC
0036 0035
CNT_EN
Timer clock = CK_CNT
Counter register
Update interrupt flag (UIF)
0034 0035
Counter overflow
Update event (UEV)
Timer clock = CK_CNT
Counter register 00 20 1F
Update interrupt flag (UIF)
Counter underflow
Update event (UEV)
CK_PSC
01

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Figure 70. Counter timing diagram, update event with ARPE=1 (counter underflow)
Figure 71. Counter timing diagram, Update event with ARPE=1 (counter overflow)
14.3.3 Repetition counter
Section 14.3.1: Time-base unit describes how the update event (UEV) is generated with
respect to the counter overflows/underflows. It is actually generated only when the repetition
counter has reached zero. This can be useful when generating PWM signals.
This means that data are transferred from the preload registers to the shadow registers
(TIMx_ARR auto-reload register, TIMx_PSC prescaler register, but also TIMx_CCRx
capture/compare registers in compare mode) every N counter overflows or underflows,
where N is the value in the TIMx_RCR repetition counter register.
CK_PSC
00
CEN
Timer clock = CK_CNT
Counter register
Update interrupt flag (UIF)
Counter underflow
Update event (UEV)
01 02 03 04 05 06 07 05 04 03 02 01 06
Auto-reload preload register FD 36
Write a new value in TIMx_ARR
Auto-reload active register FD 36
CK_PSC
36
CEN
Timer clock = CK_CNT
Counter register
Update interrupt flag (UIF)
Counter overflow
Update event (UEV)
35 34 33 32 31 30 2F F8 F9 FA FB FC F7
Auto-reload preload register FD 36
Write a new value in TIMx_ARR
Auto-reload active register FD 36
RM0008 Advanced-control timers (TIM1&TIM8)
Doc ID 13902 Rev 13 295/1093

The repetition counter is decremented:
At each counter overflow in upcounting mode,
At each counter underflow in downcounting mode,
At each counter overflow and at each counter underflow in center-aligned mode.
Although this limits the maximum number of repetition to 128 PWM cycles, it makes it
possible to update the duty cycle twice per PWM period. When refreshing compare
registers only once per PWM period in center-aligned mode, maximum resolution is
2xT
ck
, due to the symmetry of the pattern.
The repetition counter is an auto-reload type; the repetition rate is maintained as defined by
the TIMx_RCR register value (refer to Figure 72). When the update event is generated by
software (by setting the UG bit in TIMx_EGR register) or by hardware through the slave
mode controller, it occurs immediately whatever the value of the repetition counter is and the
repetition counter is reloaded with the content of the TIMx_RCR register.
Figure 72. Update rate examples depending on mode and TIMx_RCR register
settings
Center-aligned mode Edge-aligned mode
UEV Update Event: Preload registers transferred to active registers and update interrupt generated
Counter
TIMx_RCR = 0
TIMx_RCR = 1
TIMx_RCR = 2
TIMx_RCR = 3
Update Event if the repetition counter underflow occurs when the counter is equal to
to the auto-reload value.
UEV
TIMx_RCR = 3
and
re-synchronization
(by SW)
(by SW)
TIMx_CNT
(by SW)
Upcounting Downcounting
UEV
UEV
UEV
UEV

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14.3.4 Clock selection
The counter clock can be provided by the following clock sources:
Internal clock (CK_INT)
External clock mode1: external input pin
External clock mode2: external trigger input ETR
Internal trigger inputs (ITRx): using one timer as prescaler for another timer, for
example, you can configure Timer 1 to act as a prescaler for Timer 2. Refer to Using
one timer as prescaler for another for more details.
Internal clock source (CK_INT)
If the slave mode controller is disabled (SMS=000), then the CEN, DIR (in the TIMx_CR1
register) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed
only by software (except UG which remains cleared automatically). As soon as the CEN bit
is written to 1, the prescaler is clocked by the internal clock CK_INT.
Figure 73 shows the behavior of the control circuit and the upcounter in normal mode,
without prescaler.
Figure 73. Control circuit in normal mode, internal clock divided by 1
External clock source mode 1
This mode is selected when SMS=111 in the TIMx_SMCR register. The counter can count
at each rising or falling edge on a selected input.
Figure 74. TI2 external clock connection example
Internal clock
00
Counter clock = CK_CNT = CK_PSC
Counter register 01 02 03 04 05 06 07 32 33 34 35 36 31
CEN=CNT_EN
UG
CNT_INIT
CK_INT
encoder
mode
external clock
mode 1
external clock
mode 2
internal clock
mode
ETRF
TRGI
TI1F
TI2F or
or
or
(internal clock)
CK_PSC
ECE
TIMx_SMCR
SMS[2:0]
ITRx
TI1_ED
TI1FP1
TI2FP2
ETRF
TIMx_SMCR
TS[2:0]
TI2
0
1
TIMx_CCER
CC2P
Filter
ICF[3:0]
TIMx_CCMR1
Edge
Detector
TI2F_Rising
TI2F_Falling
110
0xx
100
101
111
RM0008 Advanced-control timers (TIM1&TIM8)
Doc ID 13902 Rev 13 297/1093

For example, to configure the upcounter to count in response to a rising edge on the TI2
input, use the following procedure:
1. Configure channel 2 to detect rising edges on the TI2 input by writing CC2S = 01 in
the TIMx_CCMR1 register.
2. Configure the input filter duration by writing the IC2F[3:0] bits in the TIMx_CCMR1
register (if no filter is needed, keep IC2F=0000).
3. Select rising edge polarity by writing CC2P=0 in the TIMx_CCER register.
4. Configure the timer in external clock mode 1 by writing SMS=111 in the TIMx_SMCR
register.
5. Select TI2 as the trigger input source by writing TS=110 in the TIMx_SMCR register.
6. Enable the counter by writing CEN=1 in the TIMx_CR1 register.
Note: The capture prescaler is not used for triggering, so you dont need to configure it.
When a rising edge occurs on TI2, the counter counts once and the TIF flag is set.
The delay between the rising edge on TI2 and the actual clock of the counter is due to the
resynchronization circuit on TI2 input.
Figure 75. Control circuit in external clock mode 1
External clock source mode 2
This mode is selected by writing ECE=1 in the TIMx_SMCR register.
The counter can count at each rising or falling edge on the external trigger input ETR.
The Figure 76 gives an overview of the external trigger input block.
Figure 76. External trigger input block
Counter clock = CK_CNT = CK_PSC
Counter register 35 36 34
TI2
CNT_EN
TIF
Write TIF=0
ETR
0
1
TIMx_SMCR
ETP
divider
/1, /2, /4, /8
ETPS[1:0]
ETRP
filter
ETF[3:0]
downcounter
f
DTS
TIMx_SMCR TIMx_SMCR
ETR pin
CK_INT
encoder
mode
external clock
mode 1
external clock
mode 2
internal clock
mode
ETRF
TRGI
TI1F
TI2F or
or
or
(internal clock)
CK_PSC
ECE
TIMx_SMCR
SMS[2:0]

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For example, to configure the upcounter to count each 2 rising edges on ETR, use the
following procedure:
1. As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register.
2. Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register
3. Select rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR
register
4. Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register.
5. Enable the counter by writing CEN=1 in the TIMx_CR1 register.
The counter counts once each 2 ETR rising edges.
The delay between the rising edge on ETR and the actual clock of the counter is due to the
resynchronization circuit on the ETRP signal.
Figure 77. Control circuit in external clock mode 2
14.3.5 Capture/compare channels
Each Capture/Compare channel is built around a capture/compare register (including a
shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and
an output stage (with comparator and output control).
Figure 78 to Figure 81 give an overview of one Capture/Compare channel.
The input stage samples the corresponding TIx input to generate a filtered signal TIxF.
Then, an edge detector with polarity selection generates a signal (TIxFPx) which can be
used as trigger input by the slave mode controller or as the capture command. It is
prescaled before the capture register (ICxPS).
Counter clock = CK_CNT = CK_PSC
Counter register 35 36 34
ETR
CNT_EN
f
CK_INT
ETRP
ETRF
RM0008 Advanced-control timers (TIM1&TIM8)
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Figure 78. Capture/compare channel (example: channel 1 input stage)
The output stage generates an intermediate waveform which is then used for reference:
OCxRef (active high). The polarity acts at the end of the chain.
Figure 79. Capture/compare channel 1 main circuit
TI1
0
1
TIMx_CCER
CC1P
divider
/1, /2, /4, /8
ICPS[1:0]
TI1F_ED
filter
ICF[3:0]
downcounter
TIMx_CCMR1
Edge
Detector
TI1F_Rising
TI1F_Falling
to the slave mode controller
TI1FP1
11
01
TIMx_CCMR1
CC1S[1:0]
IC1
TI2FP1
TRC
(from channel 2)
(from slave mode
controller)
10
f
DTS
TIMx_CCER
CC1E
IC1PS
TI1F
0
1
TI2F_rising
TI2F_falling
(from channel 2)
CC1E
Capture/compare shadow register
comparator
Capture/compare preload register
Counter
IC1PS
CC1S[0]
CC1S[1]
capture
input
mode
S
R
read CCR1H
read CCR1L
read_in_progress
capture_transfer
CC1S[0]
CC1S[1]
S
R
write CCR1H
write CCR1L
write_in_progress
output
mode
UEV
OC1PE
(from time
compare_transfer
APB Bus
8 8
h
i
g
h
l
o
w
(
i
f

1
6
-
b
i
t
)
MCU-peripheral interface
TIM1_CCMR1
OC1PE
base unit)
CNT>CCR1
CNT=CCR1
TIM1_EGR
CC1G

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Figure 80. Output stage of capture/compare channel (channel 1 to 3)
Figure 81. Output stage of capture/compare channel (channel 4)
The capture/compare block is made of one preload register and one shadow register. Write
and read always access the preload register.
In capture mode, captures are actually done in the shadow register, which is copied into the
preload register.
In compare mode, the content of the preload register is copied into the shadow register
which is compared to the counter.
14.3.6 Input capture mode
In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the
value of the counter after a transition detected by the corresponding ICx signal. When a
capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or
a DMA request can be sent if they are enabled. If a capture occurs while the CCxIF flag was
already high, then the over-capture flag CCxOF (TIMx_SR register) is set. CCxIF can be
cleared by software by writing it to 0 or by reading the captured data stored in the
TIMx_CCRx register. CCxOF is cleared when you write it to 0.
Output mode
CNT>CCR1
CNT=CCR1 controller
TIM1_CCMR1
OC1M[2:0]
OC1REF
OC1CE
Dead-time
generator
OC1_DT
OC1N_DT
DTG[7:0]
TIM1_BDTR
0
0
CC1E
TIM1_CCER
CC1NE
0
1
CC1P
TIM1_CCER
0
1
CC1NP
TIM1_CCER
Output
enable
circuit
OC1
Output
enable
circuit
OC1N
CC1E TIM1_CCER CC1NE
OSSI TIM1_BDTR MOE OSSR
0x
10
11
11
10
x0
ETR
Output mode
CNT > CCR4
CNT = CCR4 controller
TIM1_CCMR2
OC2M[2:0]
OC4 REF
0
1
CC4P
TIM1_CCER
Output
enable
circuit
OC4
CC4E TIM1_CCER
OSSI TIM1_BDTR MOE
To the master mode
controller
TIM1_CR2 OIS4
ETR
RM0008 Advanced-control timers (TIM1&TIM8)
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The following example shows how to capture the counter value in TIMx_CCR1 when TI1
input rises. To do this, use the following procedure:
Select the active input: TIMx_CCR1 must be linked to the TI1 input, so write the CC1S
bits to 01 in the TIMx_CCMR1 register. As soon as CC1S becomes different from 00,
the channel is configured in input and the TIMx_CCR1 register becomes read-only.
Program the input filter duration you need with respect to the signal you connect to the
timer (when the input is one of the TIx (ICxF bits in the TIMx_CCMRx register). Lets
imagine that, when toggling, the input signal is not stable during at must 5 internal clock
cycles. We must program a filter duration longer than these 5 clock cycles. We can
validate a transition on TI1 when 8 consecutive samples with the new level have been
detected (sampled at f
DTS
frequency). Then write IC1F bits to 0011 in the
TIMx_CCMR1 register.
Select the edge of the active transition on the TI1 channel by writing CC1P bit to 0 in
the TIMx_CCER register (rising edge in this case).
Program the input prescaler. In our example, we wish the capture to be performed at
each valid transition, so the prescaler is disabled (write IC1PS bits to 00 in the
TIMx_CCMR1 register).
Enable capture from the counter into the capture register by setting the CC1E bit in the
TIMx_CCER register.
If needed, enable the related interrupt request by setting the CC1IE bit in the
TIMx_DIER register, and/or the DMA request by setting the CC1DE bit in the
TIMx_DIER register.
When an input capture occurs:
The TIMx_CCR1 register gets the value of the counter on the active transition.
CC1IF flag is set (interrupt flag). CC1OF is also set if at least two consecutive captures
occurred whereas the flag was not cleared.
An interrupt is generated depending on the CC1IE bit.
A DMA request is generated depending on the CC1DE bit.
In order to handle the overcapture, it is recommended to read the data before the
overcapture flag. This is to avoid missing an overcapture which could happen after reading
the flag and before reading the data.
Note: IC interrupt and/or DMA requests can be generated by software by setting the
corresponding CCxG bit in the TIMx_EGR register.
14.3.7 PWM input mode
This mode is a particular case of input capture mode. The procedure is the same except:
Two ICx signals are mapped on the same TIx input.
These 2 ICx signals are active on edges with opposite polarity.
One of the two TIxFP signals is selected as trigger input and the slave mode controller
is configured in reset mode.

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For example, you can measure the period (in TIMx_CCR1 register) and the duty cycle (in
TIMx_CCR2 register) of the PWM applied on TI1 using the following procedure (depending
on CK_INT frequency and prescaler value):
Select the active input for TIMx_CCR1: write the CC1S bits to 01 in the TIMx_CCMR1
register (TI1 selected).
Select the active polarity for TI1FP1 (used both for capture in TIMx_CCR1 and counter
clear): write the CC1P bit to 0 (active on rising edge).
Select the active input for TIMx_CCR2: write the CC2S bits to 10 in the TIMx_CCMR1
register (TI1 selected).
Select the active polarity for TI1FP2 (used for capture in TIMx_CCR2): write the CC2P
bit to 1 (active on falling edge).
Select the valid trigger input: write the TS bits to 101 in the TIMx_SMCR register
(TI1FP1 selected).
Configure the slave mode controller in reset mode: write the SMS bits to 100 in the
TIMx_SMCR register.
Enable the captures: write the CC1E and CC2E bits to 1 in the TIMx_CCER register.
Figure 82. PWM input mode timing
1. The PWM input mode can be used only with the TIMx_CH1/TIMx_CH2 signals due to the fact that only
TI1FP1 and TI2FP2 are connected to the slave mode controller.
14.3.8 Forced output mode
In output mode (CCxS bits = 00 in the TIMx_CCMRx register), each output compare signal
(OCxREF and then OCx/OCxN) can be forced to active or inactive level directly by software,
independently of any comparison between the output compare register and the counter.
To force an output compare signal (OCXREF/OCx) to its active level, you just need to write
101 in the OCxM bits in the corresponding TIMx_CCMRx register. Thus OCXREF is forced
high (OCxREF is always active high) and OCx get opposite value to CCxP polarity bit.
For example: CCxP=0 (OCx active high) => OCx is forced to high level.
The OCxREF signal can be forced low by writing the OCxM bits to 100 in the TIMx_CCMRx
register.
TI1
TIMx_CNT 0000 0001 0002 0003 0004 0000 0004
TIMx_CCR1
TIMx_CCR2
0004
0002
IC1 capture
IC2 capture
reset counter
IC2 capture
pulse width
IC1 capture
period
measurement measurement
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Anyway, the comparison between the TIMx_CCRx shadow register and the counter is still
performed and allows the flag to be set. Interrupt and DMA requests can be sent
accordingly. This is described in the output compare mode section below.
14.3.9 Output compare mode
This function is used to control an output waveform or indicating when a period of time has
elapsed.
When a match is found between the capture/compare register and the counter, the output
compare function:
Assigns the corresponding output pin to a programmable value defined by the output
compare mode (OCxM bits in the TIMx_CCMRx register) and the output polarity (CCxP
bit in the TIMx_CCER register). The output pin can keep its level (OCXM=000), be set
active (OCxM=001), be set inactive (OCxM=010) or can toggle (OCxM=011) on match.
Sets a flag in the interrupt status register (CCxIF bit in the TIMx_SR register).
Generates an interrupt if the corresponding interrupt mask is set (CCXIE bit in the
TIMx_DIER register).
Sends a DMA request if the corresponding enable bit is set (CCxDE bit in the
TIMx_DIER register, CCDS bit in the TIMx_CR2 register for the DMA request
selection).
The TIMx_CCRx registers can be programmed with or without preload registers using the
OCxPE bit in the TIMx_CCMRx register.
In output compare mode, the update event UEV has no effect on OCxREF and OCx output.
The timing resolution is one count of the counter. Output compare mode can also be used to
output a single pulse (in One Pulse mode).
Procedure:
1. Select the counter clock (internal, external, prescaler).
2. Write the desired data in the TIMx_ARR and TIMx_CCRx registers.
3. Set the CCxIE bit if an interrupt request is to be generated.
4. Select the output mode. For example:
Write OCxM = 011 to toggle OCx output pin when CNT matches CCRx
Write OCxPE = 0 to disable preload register
Write CCxP = 0 to select active high polarity
Write CCxE = 1 to enable the output
5. Enable the counter by setting the CEN bit in the TIMx_CR1 register.
The TIMx_CCRx register can be updated at any time by software to control the output
waveform, provided that the preload register is not enabled (OCxPE=0, else TIMx_CCRx
shadow register is updated only at the next update event UEV). An example is given in
Figure 83.

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Figure 83. Output compare mode, toggle on OC1.
14.3.10 PWM mode
Pulse Width Modulation mode allows you to generate a signal with a frequency determined
by the value of the TIMx_ARR register and a duty cycle determined by the value of the
TIMx_CCRx register.
The PWM mode can be selected independently on each channel (one PWM per OCx
output) by writing 110 (PWM mode 1) or 111 (PWM mode 2) in the OCxM bits in the
TIMx_CCMRx register. You must enable the corresponding preload register by setting the
OCxPE bit in the TIMx_CCMRx register, and eventually the auto-reload preload register (in
upcounting or center-aligned modes) by setting the ARPE bit in the TIMx_CR1 register.
As the preload registers are transferred to the shadow registers only when an update event
occurs, before starting the counter, you have to initialize all the registers by setting the UG
bit in the TIMx_EGR register.
OCx polarity is software programmable using the CCxP bit in the TIMx_CCER register. It
can be programmed as active high or active low. OCx output is enabled by a combination of
the CCxE, CCxNE, MOE, OSSI and OSSR bits (TIMx_CCER and TIMx_BDTR registers).
Refer to the TIMx_CCER register description for more details.
In PWM mode (1 or 2), TIMx_CNT and TIMx_CCRx are always compared to determine
whether TIMx_CCRx TIMx_CNT or TIMx_CNT TIMx_CCRx (depending on the direction
of the counter).
The timer is able to generate PWM in edge-aligned mode or center-aligned mode
depending on the CMS bits in the TIMx_CR1 register.
oc1ref=OC1
TIM1_CNT B200 B201 0039
TIM1_CCR1 003A
Write B201h in the CC1R register
Match detected on CCR1
Interrupt generated if enabled
003B
B201
003A
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PWM edge-aligned mode
Upcounting configuration
Upcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to the
Upcounting mode on page 286.
In the following example, we consider PWM mode 1. The reference PWM signal
OCxREF is high as long as TIMx_CNT < TIMx_CCRx else it becomes low. If the
compare value in TIMx_CCRx is greater than the auto-reload value (in TIMx_ARR)
then OCxREF is held at 1. If the compare value is 0 then OCxRef is held at 0.
Figure 84 shows some edge-aligned PWM waveforms in an example where
TIMx_ARR=8.
Figure 84. Edge-aligned PWM waveforms (ARR=8)
Downcounting configuration
Downcounting is active when DIR bit in TIMx_CR1 register is high. Refer to the
Downcounting mode on page 289
In PWM mode 1, the reference signal OCxRef is low as long as
TIMx_CNT > TIMx_CCRx else it becomes high. If the compare value in TIMx_CCRx is
greater than the auto-reload value in TIMx_ARR, then OCxREF is held at 1. 0% PWM
is not possible in this mode.
PWM center-aligned mode
Center-aligned mode is active when the CMS bits in TIMx_CR1 register are different from
00 (all the remaining configurations having the same effect on the OCxRef/OCx signals).
The compare flag is set when the counter counts up, when it counts down or both when it
counts up and down depending on the CMS bits configuration. The direction bit (DIR) in the
TIMx_CR1 register is updated by hardware and must not be changed by software. Refer to
the Center-aligned mode (up/down counting) on page 291.
Figure 85 shows some center-aligned PWM waveforms in an example where:
TIMx_ARR=8,
PWM mode is the PWM mode 1,
The flag is set when the counter counts down corresponding to the center-aligned
mode 1 selected for CMS=01 in TIMx_CR1 register.
Counter register
1
0 1 2 3 4 5 6 7 8 0 1
0
OCXREF
CCxIF
OCXREF
CCxIF
OCXREF
CCxIF
OCXREF
CCxIF
CCRx=4
CCRx=8
CCRx>8
CCRx=0

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Figure 85. Center-aligned PWM waveforms (ARR=8)
Hints on using center-aligned mode:
When starting in center-aligned mode, the current up-down configuration is used. It
means that the counter counts up or down depending on the value written in the DIR bit
in the TIMx_CR1 register. Moreover, the DIR and CMS bits must not be changed at the
same time by the software.
Writing to the counter while running in center-aligned mode is not recommended as it
can lead to unexpected results. In particular:
The direction is not updated if you write a value in the counter that is greater than
the auto-reload value (TIMx_CNT>TIMx_ARR). For example, if the counter was
counting up, it continues to count up.
The direction is updated if you write 0 or write the TIMx_ARR value in the counter
but no Update Event UEV is generated.
The safest way to use center-aligned mode is to generate an update by software
(setting the UG bit in the TIMx_EGR register) just before starting the counter and not to
write the counter while it is running.
CCxF
0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1 Counter register
CCRx = 4
OCxREF
CMS=01
CMS=10
CMS=11
CCxF
CCRx = 7
OCxREF
CMS=10 or 11
CCxF
CCRx = 8
OCxREF
CMS=01
CMS=10
CMS=11
'1'
CCxF
CCRx > 8
OCxREF
CMS=01
CMS=10
CMS=11
'1'
CCxF
CCRx = 0
OCxREF
CMS=01
CMS=10
CMS=11
'0'
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14.3.11 Complementary outputs and dead-time insertion
The advanced-control timers (TIM1&TIM8) can output two complementary signals and
manage the switching-off and the switching-on instants of the outputs.
This time is generally known as dead-time and you have to adjust it depending on the
devices you have connected to the outputs and their characteristics (intrinsic delays of level-
shifters, delays due to power switches...)
You can select the polarity of the outputs (main output OCx or complementary OCxN)
independently for each output. This is done by writing to the CCxP and CCxNP bits in the
TIMx_CCER register.
The complementary signals OCx and OCxN are activated by a combination of several
control bits: the CCxE and CCxNE bits in the TIMx_CCER register and the MOE, OISx,
OISxN, OSSI and OSSR bits in the TIMx_BDTR and TIMx_CR2 registers. Refer to Table 83:
Output control bits for complementary OCx and OCxN channels with break feature on
page 339 for more details. In particular, the dead-time is activated when switching to the
IDLE state (MOE falling down to 0).
Dead-time insertion is enabled by setting both CCxE and CCxNE bits, and the MOE bit if the
break circuit is present. There is one 10-bit dead-time generator for each channel. From a
reference waveform OCxREF, it generates 2 outputs OCx and OCxN. If OCx and OCxN are
active high:
The OCx output signal is the same as the reference signal except for the rising edge,
which is delayed relative to the reference rising edge.
The OCxN output signal is the opposite of the reference signal except for the rising
edge, which is delayed relative to the reference falling edge.
If the delay is greater than the width of the active output (OCx or OCxN) then the
corresponding pulse is not generated.
The following figures show the relationships between the output signals of the dead-time
generator and the reference signal OCxREF. (we suppose CCxP=0, CCxNP=0, MOE=1,
CCxE=1 and CCxNE=1 in these examples)
Figure 86. Complementary output with dead-time insertion.
Figure 87. Dead-time waveforms with delay greater than the negative pulse.
delay
delay
OCxREF
OCx
OCxN
delay
OCxREF
OCx
OCxN

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Figure 88. Dead-time waveforms with delay greater than the positive pulse.
The dead-time delay is the same for each of the channels and is programmable with the
DTG bits in the TIMx_BDTR register. Refer to Section 14.4.18: TIM1&TIM8 break and dead-
time register (TIMx_BDTR) on page 343 for delay calculation.
Re-directing OCxREF to OCx or OCxN
In output mode (forced, output compare or PWM), OCxREF can be re-directed to the OCx
output or to OCxN output by configuring the CCxE and CCxNE bits in the TIMx_CCER
register.
This allows you to send a specific waveform (such as PWM or static active level) on one
output while the complementary remains at its inactive level. Other alternative possibilities
are to have both outputs at inactive level or both outputs active and complementary with
dead-time.
Note: When only OCxN is enabled (CCxE=0, CCxNE=1), it is not complemented and becomes
active as soon as OCxREF is high. For example, if CCxNP=0 then OCxN=OCxRef. On the
other hand, when both OCx and OCxN are enabled (CCxE=CCxNE=1) OCx becomes
active when OCxREF is high whereas OCxN is complemented and becomes active when
OCxREF is low.
14.3.12 Using the break function
When using the break function, the output enable signals and inactive levels are modified
according to additional control bits (MOE, OSSI and OSSR bits in the TIMx_BDTR register,
OISx and OISxN bits in the TIMx_CR2 register). In any case, the OCx and OCxN outputs
cannot be set both to active level at a given time. Refer to Table 83: Output control bits for
complementary OCx and OCxN channels with break feature on page 339 for more details.
The break source can be either the break input pin or a clock failure event, generated by the
Clock Security System (CSS), from the Reset Clock Controller. For further information on
the Clock Security System, refer to Section 7.2.7: Clock security system (CSS) on page 94.
When exiting from reset, the break circuit is disabled and the MOE bit is low. You can enable
the break function by setting the BKE bit in the TIMx_BDTR register. The break input
polarity can be selected by configuring the BKP bit in the same register. BKE and BKP can
be modified at the same time. When the BKE and BKP bits are written, a delay of 1 APB
clock cycle is applied before the writing is effective. Consequently, it is necessary to wait 1
APB clock period to correctly read back the bit after the write operation.
Because MOE falling edge can be asynchronous, a resynchronization circuit has been
inserted between the actual signal (acting on the outputs) and the synchronous control bit
(accessed in the TIMx_BDTR register). It results in some delays between the asynchronous
and the synchronous signals. In particular, if you write MOE to 1 whereas it was low, you
delay
OCxREF
OCx
OCxN
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must insert a delay (dummy instruction) before reading it correctly. This is because you write
the asynchronous signal and read the synchronous signal.
When a break occurs (selected level on the break input):
The MOE bit is cleared asynchronously, putting the outputs in inactive state, idle state
or in reset state (selected by the OSSI bit). This feature functions even if the MCU
oscillator is off.
Each output channel is driven with the level programmed in the OISx bit in the
TIMx_CR2 register as soon as MOE=0. If OSSI=0 then the timer releases the enable
output else the enable output remains high.
When complementary outputs are used:
The outputs are first put in reset state inactive state (depending on the polarity).
This is done asynchronously so that it works even if no clock is provided to the
timer.
If the timer clock is still present, then the dead-time generator is reactivated in
order to drive the outputs with the level programmed in the OISx and OISxN bits
after a dead-time. Even in this case, OCx and OCxN cannot be driven to their
active level together. Note that because of the resynchronization on MOE, the
dead-time duration is a bit longer than usual (around 2 ck_tim clock cycles).
If OSSI=0 then the timer releases the enable outputs else the enable outputs
remain or become high as soon as one of the CCxE or CCxNE bits is high.
The break status flag (BIF bit in the TIMx_SR register) is set. An interrupt can be
generated if the BIE bit in the TIMx_DIER register is set. A DMA request can be sent if
the BDE bit in the TIMx_DIER register is set.
If the AOE bit in the TIMx_BDTR register is set, the MOE bit is automatically set again
at the next update event UEV. This can be used to perform a regulation, for instance.
Else, MOE remains low until you write it to 1 again. In this case, it can be used for
security and you can connect the break input to an alarm from power drivers, thermal
sensors or any security components.
Note: The break inputs is acting on level. Thus, the MOE cannot be set while the break input is
active (neither automatically nor by software). In the meantime, the status flag BIF cannot be
cleared.
The break can be generated by the BRK input which has a programmable polarity and an
enable bit BKE in the TIMx_BDTR Register.
In addition to the break input and the output management, a write protection has been
implemented inside the break circuit to safeguard the application. It allows you to freeze the
configuration of several parameters (dead-time duration, OCx/OCxN polarities and state
when disabled, OCxM configurations, break enable and polarity). You can choose from 3
levels of protection selected by the LOCK bits in the TIMx_BDTR register. Refer to
Section 14.4.18: TIM1&TIM8 break and dead-time register (TIMx_BDTR) on page 343. The
LOCK bits can be written only once after an MCU reset.
The Figure 89 shows an example of behavior of the outputs in response to a break.

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Figure 89. Output behavior in response to a break.
delay
OCxREF
BREAK (MOE
OCx
(OCxN not implemented, CCxP=0, OISx=1)
OCx
(OCxN not implemented, CCxP=0, OISx=0)
OCx
(OCxN not implemented, CCxP=1, OISx=1)
OCx
(OCxN not implemented, CCxP=1, OISx=0)
OCx
OCxN
(CCxE=1, CCxP=0, OISx=0, CCxNE=1, CCxNP=0, OISxN=1)
delay delay
delay
OCx
OCxN
(CCxE=1, CCxP=0, OISx=1, CCxNE=1, CCxNP=1, OISxN=1)
delay delay
delay
OCx
OCxN
(CCxE=1, CCxP=0, OISx=0, CCxNE=0, CCxNP=0, OISxN=1)
)
delay
OCx
OCxN
(CCxE=1, CCxP=0, OISx=1, CCxNE=0, CCxNP=0, OISxN=0)
OCx
OCxN
(CCxE=1, CCxP=0, CCxNE=0, CCxNP=0, OISx=OISxN=0 or OISx=OISxN=1)
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14.3.13 Clearing the OCxREF signal on an external event
The OCxREF signal for a given channel can be driven Low by applying a High level to the
ETRF input (OCxCE enable bit of the corresponding TIMx_CCMRx register set to 1). The
OCxREF signal remains Low until the next update event, UEV, occurs.
This function can only be used in output compare and PWM modes, and does not work in
forced mode.
For example, the OCxREF signal) can be connected to the output of a comparator to be
used for current handling. In this case, the ETR must be configured as follow:
1. The External Trigger Prescaler should be kept off: bits ETPS[1:0] of the TIMx_SMCR
register set to 00.
2. The external clock mode 2 must be disabled: bit ECE of the TIMx_SMCR register set to
0.
3. The External Trigger Polarity (ETP) and the External Trigger Filter (ETF) can be
configured according to the user needs.
Figure 90 shows the behavior of the OCxREF signal when the ETRF Input becomes High,
for both values of the enable bit OCxCE. In this example, the timer TIMx is programmed in
PWM mode.
Figure 90. Clearing TIMx OCxREF
OCxREF
counter (CNT)
OCxREF
ETRF
(OCxCE=0)
(OCxCE=1)
OCREF_CLR
becomes high
OCREF_CLR
still high
(CCRx)

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14.3.14 6-step PWM generation
When complementary outputs are used on a channel, preload bits are available on the
OCxM, CCxE and CCxNE bits. The preload bits are transferred to the shadow bits at the
COM commutation event. Thus you can program in advance the configuration for the next
step and change the configuration of all the channels at the same time. COM can be
generated by software by setting the COM bit in the TIMx_EGR register or by hardware (on
TRGI rising edge).
A flag is set when the COM event occurs (COMIF bit in the TIMx_SR register), which can
generate an interrupt (if the COMIE bit is set in the TIMx_DIER register) or a DMA request
(if the COMDE bit is set in the TIMx_DIER register).
The Figure 91 describes the behavior of the OCx and OCxN outputs when a COM event
occurs, in 3 different examples of programmed configurations.
Figure 91. 6-step generation, COM example (OSSR=1)
(CCRx)
OCx
OCxN
Write COM to 1
counter (CNT)
OCxREF
COM event
CCxE=1
CCxNE=0
OCxM=100
OCx
OCxN
CCxE=0
CCxNE=1
OCxM=101
OCx
OCxN
CCxE=1
CCxNE=0
OCxM=100
Example 1
Example 2
Example 3
write OCxM to 100
CCxE=1
CCxNE=0
OCxM=100 (forced inactive)
CCxE=1
CCxNE=0
OCxM=100 (forced inactive)
Write CCxNE to 1
and OCxM to 101
write CCxNE to 0
and OCxM to 100
CCxE=1
CCxNE=0
OCxM=100 (forced inactive)
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14.3.15 One-pulse mode
One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to
be started in response to a stimulus and to generate a pulse with a programmable length
after a programmable delay.
Starting the counter can be controlled through the slave mode controller. Generating the
waveform can be done in output compare mode or PWM mode. You select One-pulse mode
by setting the OPM bit in the TIMx_CR1 register. This makes the counter stop automatically
at the next update event UEV.
A pulse can be correctly generated only if the compare value is different from the counter
initial value. Before starting (when the timer is waiting for the trigger), the configuration must
be:
In upcounting: CNT < CCRx ARR (in particular, 0 < CCRx)
In downcounting: CNT > CCRx
Figure 92. Example of one pulse mode.
For example you may want to generate a positive pulse on OC1 with a length of t
PULSE
and
after a delay of t
DELAY
as soon as a positive edge is detected on the TI2 input pin.
Lets use TI2FP2 as trigger 1:
Map TI2FP2 to TI2 by writing CC2S=01 in the TIMx_CCMR1 register.
TI2FP2 must detect a rising edge, write CC2P=0 in the TIMx_CCER register.
Configure TI2FP2 as trigger for the slave mode controller (TRGI) by writing TS=110 in
the TIMx_SMCR register.
TI2FP2 is used to start the counter by writing SMS to 110 in the TIMx_SMCR register
(trigger mode).
TI2
OC1REF
C
o
u
n
t
e
r
t
0
TIM1_ARR
TIM1_CCR1
OC1
t
DELAY
t
PULSE

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The OPM waveform is defined by writing the compare registers (taking into account the
clock frequency and the counter prescaler).
The t
DELAY
is defined by the value written in the TIMx_CCR1 register.
The t
PULSE
is defined by the difference between the auto-reload value and the compare
value (TIMx_ARR - TIMx_CCR1).
Lets say you want to build a waveform with a transition from 0 to 1 when a compare
match occurs and a transition from 1 to 0 when the counter reaches the auto-reload
value. To do this you enable PWM mode 2 by writing OC1M=111 in the TIMx_CCMR1
register. You can optionally enable the preload registers by writing OC1PE=1 in the
TIMx_CCMR1 register and ARPE in the TIMx_CR1 register. In this case you have to
write the compare value in the TIMx_CCR1 register, the auto-reload value in the
TIMx_ARR register, generate an update by setting the UG bit and wait for external
trigger event on TI2. CC1P is written to 0 in this example.
In our example, the DIR and CMS bits in the TIMx_CR1 register should be low.
You only want 1 pulse (Single mode), so you write '1 in the OPM bit in the TIMx_CR1
register to stop the counter at the next update event (when the counter rolls over from the
auto-reload value back to 0). When OPM bit in the TIMx_CR1 register is set to '0', so the
Repetitive Mode is selected.
Particular case: OCx fast enable:
In One-pulse mode, the edge detection on TIx input set the CEN bit which enables the
counter. Then the comparison between the counter and the compare value makes the
output toggle. But several clock cycles are needed for these operations and it limits the
minimum delay t
DELAY
min we can get.
If you want to output a waveform with the minimum delay, you can set the OCxFE bit in the
TIMx_CCMRx register. Then OCxRef (and OCx) are forced in response to the stimulus,
without taking in account the comparison. Its new level is the same as if a compare match
had occurred. OCxFE acts only if the channel is configured in PWM1 or PWM2 mode.
14.3.16 Encoder interface mode
To select Encoder Interface mode write SMS=001 in the TIMx_SMCR register if the
counter is counting on TI2 edges only, SMS=010 if it is counting on TI1 edges only and
SMS=011 if it is counting on both TI1 and TI2 edges.
Select the TI1 and TI2 polarity by programming the CC1P and CC2P bits in the TIMx_CCER
register. When needed, you can program the input filter as well.
The two inputs TI1 and TI2 are used to interface to an incremental encoder. Refer to
Table 81. The counter is clocked by each valid transition on TI1FP1 or TI2FP2 (TI1 and TI2
after input filter and polarity selection, TI1FP1=TI1 if not filtered and not inverted,
TI2FP2=TI2 if not filtered and not inverted) assuming that it is enabled (CEN bit in
TIMx_CR1 register written to 1). The sequence of transitions of the two inputs is evaluated
and generates count pulses as well as the direction signal. Depending on the sequence the
counter counts up or down, the DIR bit in the TIMx_CR1 register is modified by hardware
accordingly. The DIR bit is calculated at each transition on any input (TI1 or TI2), whatever
the counter is counting on TI1 only, TI2 only or both TI1 and TI2.
Encoder interface mode acts simply as an external clock with direction selection. This
means that the counter just counts continuously between 0 and the auto-reload value in the
TIMx_ARR register (0 to ARR or ARR down to 0 depending on the direction). So you must
configure TIMx_ARR before starting. in the same way, the capture, compare, prescaler,
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repetition counter, trigger output features continue to work as normal. Encoder mode and
External clock mode 2 are not compatible and must not be selected together.
In this mode, the counter is modified automatically following the speed and the direction of
the incremental encoder and its content, therefore, always represents the encoders
position. The count direction correspond to the rotation direction of the connected sensor.
The table summarizes the possible combinations, assuming TI1 and TI2 dont switch at the
same time.

An external incremental encoder can be connected directly to the MCU without external
interface logic. However, comparators are normally be used to convert the encoders
differential outputs to digital signals. This greatly increases noise immunity. The third
encoder output which indicate the mechanical zero position, may be connected to an
external interrupt input and trigger a counter reset.
The Figure 93 gives an example of counter operation, showing count signal generation and
direction control. It also shows how input jitter is compensated where both edges are
selected. This might occur if the sensor is positioned near to one of the switching points. For
this example we assume that the configuration is the following:
CC1S=01 (TIMx_CCMR1 register, TI1FP1 mapped on TI1).
CC2S=01 (TIMx_CCMR2 register, TI1FP2 mapped on TI2).
CC1P=0 (TIMx_CCER register, TI1FP1 non-inverted, TI1FP1=TI1).
CC2P=0 (TIMx_CCER register, TI1FP2 non-inverted, TI1FP2= TI2).
SMS=011 (TIMx_SMCR register, both inputs are active on both rising and falling
edges).
CEN=1 (TIMx_CR1 register, Counter enabled).
Table 81. Counting direction versus encoder signals
Active edge
Level on
opposite
signal (TI1FP1
for TI2, TI2FP2
for TI1)
TI1FP1 signal TI2FP2 signal
Rising Falling Rising Falling
Counting on
TI1 only
High Down Up No Count No Count
Low Up Down No Count No Count
Counting on
TI2 only
High No Count No Count Up Down
Low No Count No Count Down Up
Counting on
TI1 and TI2
High Down Up Up Down
Low Up Down Down Up

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Figure 93. Example of counter operation in encoder interface mode.
Figure 94 gives an example of counter behavior when TI1FP1 polarity is inverted (same
configuration as above except CC1P=1).
Figure 94. Example of encoder interface mode with TI1FP1 polarity inverted.
The timer, when configured in Encoder Interface mode provides information on the sensors
current position. You can obtain dynamic information (speed, acceleration, deceleration) by
measuring the period between two encoder events using a second timer configured in
capture mode. The output of the encoder which indicates the mechanical zero can be used
for this purpose. Depending on the time between two events, the counter can also be read
at regular times. You can do this by latching the counter value into a third input capture
register if available (then the capture signal must be periodic and can be generated by
another timer). when available, it is also possible to read its value through a DMA request
generated by a real-time clock.
TI1
forward forward backward jitter jitter
up down up
TI2
Counter
TI1
forward forward backward jitter jitter
up down
TI2
Counter
down
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14.3.17 Timer input XOR function
The TI1S bit in the TIMx_CR2 register, allows the input filter of channel 1 to be connected to
the output of a XOR gate, combining the three input pins TIMx_CH1, TIMx_CH2 and
TIMx_CH3.
The XOR output can be used with all the timer input functions such as trigger or input
capture. An example of this feature used to interface Hall sensors is given in Section 14.3.18
below.
14.3.18 Interfacing with Hall sensors
This is done using the advanced-control timers (TIM1 or TIM8) to generate PWM signals to
drive the motor and another timer TIMx (TIM2, TIM3, TIM4 or TIM5) referred to as
interfacing timer in Figure 95. The interfacing timer captures the 3 timer input pins (CC1,
CC2, CC3) connected through a XOR to the TI1 input channel (selected by setting the TI1S
bit in the TIMx_CR2 register).
The slave mode controller is configured in reset mode; the slave input is TI1F_ED. Thus,
each time one of the 3 inputs toggles, the counter restarts counting from 0. This creates a
time base triggered by any change on the Hall inputs.
On the interfacing timer, capture/compare channel 1 is configured in capture mode,
capture signal is TRC (See Figure 78: Capture/compare channel (example: channel 1 input
stage) on page 299). The captured value, which corresponds to the time elapsed between 2
changes on the inputs, gives information about motor speed.
The interfacing timer can be used in output mode to generate a pulse which changes the
configuration of the channels of the advanced-control timer (TIM1 or TIM8) (by triggering a
COM event). The TIM1 timer is used to generate PWM signals to drive the motor. To do this,
the interfacing timer channel must be programmed so that a positive pulse is generated after
a programmed delay (in output compare or PWM mode). This pulse is sent to the advanced-
control timer (TIM1 or TIM8) through the TRGO output.
Example: you want to change the PWM configuration of your advanced-control timer TIM1
after a programmed delay each time a change occurs on the Hall inputs connected to one of
the TIMx timers.
Configure 3 timer inputs ORed to the TI1 input channel by writing the TI1S bit in the
TIMx_CR2 register to 1,
Program the time base: write the TIMx_ARR to the max value (the counter must be
cleared by the TI1 change. Set the prescaler to get a maximum counter period longer
than the time between 2 changes on the sensors,
Program the channel 1 in capture mode (TRC selected): write the CC1S bits in the
TIMx_CCMR1 register to 01. You can also program the digital filter if needed,
Program the channel 2 in PWM 2 mode with the desired delay: write the OC2M bits to
111 and the CC2S bits to 00 in the TIMx_CCMR1 register,
Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
register to 101,
In the advanced-control timer TIM1, the right ITR input must be selected as trigger input, the
timer is programmed to generate PWM signals, the capture/compare control signals are
preloaded (CCPC=1 in the TIMx_CR2 register) and the COM event is controlled by the
trigger input (CCUS=1 in the TIMx_CR2 register). The PWM control bits (CCxE, OCxM) are

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written after a COM event for the next step (this can be done in an interrupt subroutine
generated by the rising edge of OC2REF).
The Figure 95 describes this example.
Figure 95. Example of hall sensor interface
counter (CNT)
TRGO=OC2REF
(CCR2)
OC1
OC1N
COM
Write CCxE, CCxNE
TIH1
TIH2
TIH3
CCR1
OC2
OC2N
OC3
OC3N
C7A3 C7A8 C794 C7A5 C7AB C796
and OCxM for next step
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14.3.19 TIMx and external trigger synchronization
The TIMx timer can be synchronized with an external trigger in several modes: Reset mode,
Gated mode and Trigger mode.
Slave mode: Reset mode
The counter and its prescaler can be reinitialized in response to an event on a trigger input.
Moreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is
generated. Then all the preloaded registers (TIMx_ARR, TIMx_CCRx) are updated.
In the following example, the upcounter is cleared in response to a rising edge on TI1 input:
Configure the channel 1 to detect rising edges on TI1. Configure the input filter duration
(in this example, we dont need any filter, so we keep IC1F=0000). The capture
prescaler is not used for triggering, so you dont need to configure it. The CC1S bits
select the input capture source only, CC1S = 01 in the TIMx_CCMR1 register. Write
CC1P=0 in TIMx_CCER register to validate the polarity (and detect rising edges only).
Configure the timer in reset mode by writing SMS=100 in TIMx_SMCR register. Select
TI1 as the input source by writing TS=101 in TIMx_SMCR register.
Start the counter by writing CEN=1 in the TIMx_CR1 register.
The counter starts counting on the internal clock, then behaves normally until TI1 rising
edge. When TI1 rises, the counter is cleared and restarts from 0. In the meantime, the
trigger flag is set (TIF bit in the TIMx_SR register) and an interrupt request, or a DMA
request can be sent if enabled (depending on the TIE and TDE bits in TIMx_DIER register).
The following figure shows this behavior when the auto-reload register TIMx_ARR=0x36.
The delay between the rising edge on TI1 and the actual reset of the counter is due to the
resynchronization circuit on TI1 input.
Figure 96. Control circuit in reset mode
00
Counter clock = ck_cnt = ck_psc
Counter register 01 02 03 00 01 02 03 32 33 34 35 36
UG
TI1
31 30
TIF

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Slave mode: Gated mode
The counter can be enabled depending on the level of a selected input.
In the following example, the upcounter counts only when TI1 input is low:
Configure the channel 1 to detect low levels on TI1. Configure the input filter duration
(in this example, we dont need any filter, so we keep IC1F=0000). The capture
prescaler is not used for triggering, so you dont need to configure it. The CC1S bits
select the input capture source only, CC1S=01 in TIMx_CCMR1 register. Write
CC1P=1 in TIMx_CCER register to validate the polarity (and detect low level only).
Configure the timer in gated mode by writing SMS=101 in TIMx_SMCR register. Select
TI1 as the input source by writing TS=101 in TIMx_SMCR register.
Enable the counter by writing CEN=1 in the TIMx_CR1 register (in gated mode, the
counter doesnt start if CEN=0, whatever is the trigger input level).
The counter starts counting on the internal clock as long as TI1 is low and stops as soon as
TI1 becomes high. The TIF flag in the TIMx_SR register is set both when the counter starts
or stops.
The delay between the rising edge on TI1 and the actual stop of the counter is due to the
resynchronization circuit on TI1 input.
Figure 97. Control circuit in gated mode
Counter clock = ck_cnt = ck_psc
Counter register 35 36 37 38 32 33 34
TI1
31 30
cnt_en
TIF
Write TIF=0
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Slave mode: Trigger mode
The counter can start in response to an event on a selected input.
In the following example, the upcounter starts in response to a rising edge on TI2 input:
Configure the channel 2 to detect rising edges on TI2. Configure the input filter duration
(in this example, we dont need any filter, so we keep IC2F=0000). The capture
prescaler is not used for triggering, so you dont need to configure it. The CC2S bits are
configured to select the input capture source only, CC2S=01 in TIMx_CCMR1 register.
Write CC2P=1 in TIMx_CCER register to validate the polarity (and detect low level
only).
Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select
TI2 as the input source by writing TS=110 in TIMx_SMCR register.
When a rising edge occurs on TI2, the counter starts counting on the internal clock and the
TIF flag is set.
The delay between the rising edge on TI2 and the actual start of the counter is due to the
resynchronization circuit on TI2 input.
Figure 98. Control circuit in trigger mode
Slave mode: external clock mode 2 + trigger mode
The external clock mode 2 can be used in addition to another slave mode (except external
clock mode 1 and encoder mode). In this case, the ETR signal is used as external clock
input, and another input can be selected as trigger input (in reset mode, gated mode or
trigger mode). It is recommended not to select ETR as TRGI through the TS bits of
TIMx_SMCR register.
In the following example, the upcounter is incremented at each rising edge of the ETR signal
as soon as a rising edge of TI1 occurs:
1. Configure the external trigger input circuit by programming the TIMx_SMCR register as
follows:
ETF = 0000: no filter
ETPS=00: prescaler disabled
ETP=0: detection of rising edges on ETR and ECE=1 to enable the external clock
mode 2.
Counter clock = ck_cnt = ck_psc
Counter register 35 36 37 38 34
TI2
cnt_en
TIF

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2. Configure the channel 1 as follows, to detect rising edges on TI:
IC1F=0000: no filter.
The capture prescaler is not used for triggering and does not need to be
configured.
CC1S=01in TIMx_CCMR1 register to select only the input capture source
CC1P=0 in TIMx_CCER register to validate the polarity (and detect rising edge
only).
3. Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select
TI1 as the input source by writing TS=101 in TIMx_SMCR register.
A rising edge on TI1 enables the counter and sets the TIF flag. The counter then counts on
ETR rising edges.
The delay between the rising edge of the ETR signal and the actual reset of the counter is
due to the resynchronization circuit on ETRP input.
Figure 99. Control circuit in external clock mode 2 + trigger mode
14.3.20 Timer synchronization
The TIM timers are linked together internally for timer synchronization or chaining. Refer to
Section 15.3.15: Timer synchronization on page 380 for details.
14.3.21 Debug mode
When the microcontroller enters debug mode (Cortex-M3 core halted), the TIMx counter
either continues to work normally or stops, depending on DBG_TIMx_STOP configuration
bit in DBG module. For more details, refer to Section 31.16.2: Debug support for timers,
watchdog, bxCAN and I2C.
Counter clock = CK_CNT = CK_PSC
Counter register 35 36 34
ETR
CEN/CNT_EN
TIF
TI1
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14.4 TIM1&TIM8 registers
Refer toSection 2.1 on page 46 for a list of abbreviations used in register descriptions.
The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).
14.4.1 TIM1&TIM8 control register 1 (TIMx_CR1)
Address offset: 0x00
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
CKD[1:0] ARPE CMS[1:0] DIR OPM URS UDIS CEN
rw rw rw rw rw rw rw rw rw rw
Bits 15:10 Reserved, always read as 0
Bits 9:8 CKD[1:0]: Clock division
This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the
dead-time and sampling clock (t
DTS
)used by the dead-time generators and the digital filters
(ETR, TIx),
00: t
DTS
=t
CK_INT
01: t
DTS
=2*t
CK_INT
10: t
DTS
=4*t
CK_INT
11: Reserved, do not program this value
Bit 7 ARPE: Auto-reload preload enable
0: TIMx_ARR register is not buffered
1: TIMx_ARR register is buffered
Bits 6:5 CMS[1:0]: Center-aligned mode selection
00: Edge-aligned mode. The counter counts up or down depending on the direction bit
(DIR).
01: Center-aligned mode 1. The counter counts up and down alternatively. Output compare
interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set
only when the counter is counting down.
10: Center-aligned mode 2. The counter counts up and down alternatively. Output compare
interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set
only when the counter is counting up.
11: Center-aligned mode 3. The counter counts up and down alternatively. Output compare
interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set
both when the counter is counting up or down.
Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as
the counter is enabled (CEN=1)
Bit 4 DIR: Direction
0: Counter used as upcounter
1: Counter used as downcounter
Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder
mode.
Bit 3 OPM: One pulse mode
0: Counter is not stopped at update event
1: Counter stops counting at the next update event (clearing the bit CEN)

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14.4.2 TIM1&TIM8 control register 2 (TIMx_CR2)
Address offset: 0x04
Reset value: 0x0000

Bit 2 URS: Update request source
This bit is set and cleared by software to select the UEV event sources.
0: Any of the following events generate an update interrupt or DMA request if enabled.
These events can be:
Counter overflow/underflow
Setting the UG bit
Update generation through the slave mode controller
1: Only counter overflow/underflow generates an update interrupt or DMA request if
enabled.
Bit 1 UDIS: Update disable
This bit is set and cleared by software to enable/disable UEV event generation.
0: UEV enabled. The Update (UEV) event is generated by one of the following events:
Counter overflow/underflow
Setting the UG bit
Update generation through the slave mode controller
Buffered registers are then loaded with their preload values.
1: UEV disabled. The Update event is not generated, shadow registers keep their value
(ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is
set or if a hardware reset is received from the slave mode controller.
Bit 0 CEN: Counter enable
0: Counter disabled
1: Counter enabled
Note: External clock, gated mode and encoder mode can work only if the CEN bit has been
previously set by software. However trigger mode can set the CEN bit automatically by
hardware.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res.
OIS4 OIS3N OIS3 OIS2N OIS2 OIS1N OIS1 TI1S MMS[2:0] CCDS CCUS
Res.
CCPC
rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bit 15 Reserved, always read as 0
Bit 14 OIS4: Output Idle state 4 (OC4 output)
refer to OIS1 bit
Bit 13 OIS3N: Output Idle state 3 (OC3N output)
refer to OIS1N bit
Bit 12 OIS3: Output Idle state 3 (OC3 output)
refer to OIS1 bit
Bit 11 OIS2N: Output Idle state 2 (OC2N output)
refer to OIS1N bit
Bit 10 OIS2: Output Idle state 2 (OC2 output)
refer to OIS1 bit
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Bit 9 OIS1N: Output Idle state 1 (OC1N output)
0: OC1N=0 after a dead-time when MOE=0
1: OC1N=1 after a dead-time when MOE=0
Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed
(LOCK bits in TIMx_BDTR register).
Bit 8 OIS1: Output Idle state 1 (OC1 output)
0: OC1=0 (after a dead-time if OC1N is implemented) when MOE=0
1: OC1=1 (after a dead-time if OC1N is implemented) when MOE=0
Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed
(LOCK bits in TIMx_BDTR register).
Bit 7 TI1S: TI1 selection
0: The TIMx_CH1 pin is connected to TI1 input
1: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination)
Bits 6:4 MMS[1:0]: Master mode selection
These bits allow to select the information to be sent in master mode to slave timers for
synchronization (TRGO). The combination is as follows:
000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the
reset is generated by the trigger input (slave mode controller configured in reset mode) then
the signal on TRGO is delayed compared to the actual reset.
001: Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO). It is
useful to start several timers at the same time or to control a window in which a slave timer is
enable. The Counter Enable signal is generated by a logic OR between CEN control bit and
the trigger input when configured in gated mode. When the Counter Enable signal is
controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is
selected (see the MSM bit description in TIMx_SMCR register).
010: Update - The update event is selected as trigger output (TRGO). For instance a master
timer can then be used as a prescaler for a slave timer.
011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be
set (even if it was already high), as soon as a capture or a compare match occurred.
(TRGO).
100: Compare - OC1REF signal is used as trigger output (TRGO)
101: Compare - OC2REF signal is used as trigger output (TRGO)
110: Compare - OC3REF signal is used as trigger output (TRGO)
111: Compare - OC4REF signal is used as trigger output (TRGO)
Bit 3 CCDS: Capture/compare DMA selection
0: CCx DMA request sent when CCx event occurs
1: CCx DMA requests sent when update event occurs
Bit 2 CCUS: Capture/compare control update selection
0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting
the COMG bit only
1: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting
the COMG bit or when an rising edge occurs on TRGI
Note: This bit acts only on channels that have a complementary output.
Bit 1 Reserved, always read as 0
Bit 0 CCPC: Capture/compare preloaded control
0: CCxE, CCxNE and OCxM bits are not preloaded
1: CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated
only when COM bit is set.
Note: This bit acts only on channels that have a complementary output.

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14.4.3 TIM1&TIM8 slave mode control register (TIMx_SMCR)
Address offset: 0x08
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP ECE ETPS[1:0] ETF[3:0] MSM TS[2:0] Res. SMS[2:0]
rw rw rw rw rw rw rw rw rw rw rw rw Res. rw rw rw
Bit 15 ETP: External trigger polarity
This bit selects whether ETR or ETR is used for trigger operations
0: ETR is non-inverted, active at high level or rising edge.
1: ETR is inverted, active at low level or falling edge.
Bit 14 ECE: External clock enable
This bit enables External clock mode 2.
0: External clock mode 2 disabled
1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF
signal.
Note: 1: Setting the ECE bit has the same effect as selecting external clock mode 1 with
TRGI connected to ETRF (SMS=111 and TS=111).
2: It is possible to simultaneously use external clock mode 2 with the following slave
modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be
connected to ETRF in this case (TS bits must not be 111).
3: If external clock mode 1 and external clock mode 2 are enabled at the same time,
the external clock input is ETRF.
Bits 13:12 ETPS[1:0]: External trigger prescaler
External trigger signal ETRP frequency must be at most 1/4 of TIMxCLK frequency. A
prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external
clocks.
00: Prescaler OFF
01: ETRP frequency divided by 2
10: ETRP frequency divided by 4
11: ETRP frequency divided by 8
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Bits 11:8 ETF[3:0]: External trigger filter
This bit-field then defines the frequency used to sample ETRP signal and the length of the
digital filter applied to ETRP. The digital filter is made of an event counter in which N events
are needed to validate a transition on the output:
0000: No filter, sampling is done at f
DTS
0001: f
SAMPLING
=f
CK_INT
, N=2
0010: f
SAMPLING
=f
CK_INT
, N=4
0011: f
SAMPLING
=f
CK_INT
, N=8
0100: f
SAMPLING
=f
DTS
/2, N=6
0101: f
SAMPLING
=f
DTS
/2, N=8
0110: f
SAMPLING
=f
DTS
/4, N=6
0111: f
SAMPLING
=f
DTS
/4, N=8
1000: f
SAMPLING
=f
DTS
/8, N=6
1001: f
SAMPLING
=f
DTS
/8, N=8
1010: f
SAMPLING
=f
DTS
/16, N=5
1011: f
SAMPLING
=f
DTS
/16, N=6
1100: f
SAMPLING
=f
DTS
/16, N=8
1101: f
SAMPLING
=f
DTS
/32, N=5
1110: f
SAMPLING
=f
DTS
/32, N=6
1111: f
SAMPLING
=f
DTS
/32, N=8
Bit 7 MSM: Master/slave mode
0: No action
1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect
synchronization between the current timer and its slaves (through TRGO). It is useful if we
want to synchronize several timers on a single external event.
Bits 6:4 TS[2:0]: Trigger selection
This bit-field selects the trigger input to be used to synchronize the counter.
000: Internal Trigger 0 (ITR0)
001: Internal Trigger 1 (ITR1)
010: Internal Trigger 2 (ITR2)
011: Internal Trigger 3 (ITR3)
100: TI1 Edge Detector (TI1F_ED)
101: Filtered Timer Input 1 (TI1FP1)
110: Filtered Timer Input 2 (TI2FP2)
111: External Trigger input (ETRF)
See Table 82: TIMx Internal trigger connection on page 328 for more details on ITRx meaning
for each Timer.
Note: These bits must be changed only when they are not used (e.g. when SMS=000) to
avoid wrong edge detections at the transition.
Bit 3 Reserved, must be kept at reset value.

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14.4.4 TIM1&TIM8 DMA/interrupt enable register (TIMx_DIER)
Address offset: 0x0C
Reset value: 0x0000

Bits 2:0 SMS: Slave mode selection
When external signals are selected the active edge of the trigger signal (TRGI) is linked to
the polarity selected on the external input (see Input Control register and Control Register
description.
000: Slave mode disabled - if CEN = 1 then the prescaler is clocked directly by the internal
clock.
001: Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1
level.
010: Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2
level.
011: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges
depending on the level of the other input.
100: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter
and generates an update of the registers.
101: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The
counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of
the counter are controlled.
110: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not
reset). Only the start of the counter is controlled.
111: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
Note: The gated mode must not be used if TI1F_ED is selected as the trigger input
(TS=100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the
gated mode checks the level of the trigger signal.
Table 82. TIMx Internal trigger connection
(1)
1. When a timer is not present in the product, the corresponding trigger ITRx is not available.
Slave TIM ITR0 (TS = 000) ITR1 (TS = 001) ITR2 (TS = 010) ITR3 (TS = 011)
TIM1 TIM5 TIM2 TIM3 TIM4
TIM8 TIM1 TIM2 TIM4 TIM5
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res.
TDE COMDE CC4DE CC3DE CC2DE CC1DE UDE BIE TIE COMIE CC4IE CC3IE CC2IE CC1IE UIE
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bit 15 Reserved, must be kept at reset value.
Bit 14 TDE: Trigger DMA request enable
0: Trigger DMA request disabled
1: Trigger DMA request enabled
Bit 13 COMDE: COM DMA request enable
0: COM DMA request disabled
1: COM DMA request enabled
RM0008 Advanced-control timers (TIM1&TIM8)
Doc ID 13902 Rev 13 329/1093

Bit 12 CC4DE: Capture/Compare 4 DMA request enable
0: CC4 DMA request disabled
1: CC4 DMA request enabled
Bit 11 CC3DE: Capture/Compare 3 DMA request enable
0: CC3 DMA request disabled
1: CC3 DMA request enabled
Bit 10 CC2DE: Capture/Compare 2 DMA request enable
0: CC2 DMA request disabled
1: CC2 DMA request enabled
Bit 9 CC1DE: Capture/Compare 1 DMA request enable
0: CC1 DMA request disabled
1: CC1 DMA request enabled
Bit 8 UDE: Update DMA request enable
0: Update DMA request disabled
1: Update DMA request enabled
Bit 7 BIE: Break interrupt enable
0: Break interrupt disabled
1: Break interrupt enabled
Bit 6 TIE: Trigger interrupt enable
0: Trigger interrupt disabled
1: Trigger interrupt enabled
Bit 5 COMIE: COM interrupt enable
0: COM interrupt disabled
1: COM interrupt enabled
Bit 4 CC4IE: Capture/Compare 4 interrupt enable
0: CC4 interrupt disabled
1: CC4 interrupt enabled
Bit 3 CC3IE: Capture/Compare 3 interrupt enable
0: CC3 interrupt disabled
1: CC3 interrupt enabled
Bit 2 CC2IE: Capture/Compare 2 interrupt enable
0: CC2 interrupt disabled
1: CC2 interrupt enabled
Bit 1 CC1IE: Capture/Compare 1 interrupt enable
0: CC1 interrupt disabled
1: CC1 interrupt enabled
Bit 0 UIE: Update interrupt enable
0: Update interrupt disabled
1: Update interrupt enabled

Advanced-control timers (TIM1&TIM8) RM0008
330/1093 Doc ID 13902 Rev 13
14.4.5 TIM1&TIM8 status register (TIMx_SR)
Address offset: 0x10
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
CC4OF CC3OF CC2OF CC1OF Res. BIF TIF COMIF CC4IF CC3IF CC2IF CC1IF UIF
rc_w0 rc_w0 rc_w0 rc_w0 Res. rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0
Bits 15:13 Reserved, must be kept at reset value.
Bit 12 CC4OF: Capture/Compare 4 overcapture flag
refer to CC1OF description
Bit 11 CC3OF: Capture/Compare 3 overcapture flag
refer to CC1OF description
Bit 10 CC2OF: Capture/Compare 2 overcapture flag
refer to CC1OF description
Bit 9 CC1OF: Capture/Compare 1 overcapture flag
This flag is set by hardware only when the corresponding channel is configured in input
capture mode. It is cleared by software by writing it to 0.
0: No overcapture has been detected.
1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was
already set
Bit 8 Reserved, must be kept at reset value.
Bit 7 BIF: Break interrupt flag
This flag is set by hardware as soon as the break input goes active. It can be cleared by
software if the break input is not active.
0: No break event occurred.
1: An active level has been detected on the break input.
Bit 6 TIF: Trigger interrupt flag
This flag is set by hardware on trigger event (active edge detected on TRGI input when the
slave mode controller is enabled in all modes but gated mode, both edges in case gated
mode is selected). It is cleared by software.
0: No trigger event occurred.
1: Trigger interrupt pending.
Bit 5 COMIF: COM interrupt flag
This flag is set by hardware on COM event (when Capture/compare Control bits - CCxE,
CCxNE, OCxM - have been updated). It is cleared by software.
0: No COM event occurred.
1: COM interrupt pending.
Bit 4 CC4IF: Capture/Compare 4 interrupt flag
refer to CC1IF description
Bit 3 CC3IF: Capture/Compare 3 interrupt flag
refer to CC1IF description
RM0008 Advanced-control timers (TIM1&TIM8)
Doc ID 13902 Rev 13 331/1093

14.4.6 TIM1&TIM8 event generation register (TIMx_EGR)
Address offset: 0x14
Reset value: 0x0000

Bit 2 CC2IF: Capture/Compare 2 interrupt flag
refer to CC1IF description
Bit 1 CC1IF: Capture/Compare 1 interrupt flag
If channel CC1 is configured as output:
This flag is set by hardware when the counter matches the compare value, with some
exception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register
description). It is cleared by software.
0: No match.
1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register.
When the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF
bit goes high on the counter overflow (in upcounting and up/down-counting modes) or
underflow (in downcounting mode)
If channel CC1 is configured as input:
This bit is set by hardware on a capture. It is cleared by software or by reading the
TIMx_CCR1 register.
0: No input capture occurred
1: The counter value has been captured in TIMx_CCR1 register (An edge has been
detected on IC1 which matches the selected polarity)
Bit 0 UIF: Update interrupt flag
This bit is set by hardware on an update event. It is cleared by software.
0: No update occurred.
1: Update interrupt pending. This bit is set by hardware when the registers are updated:
At overflow or underflow regarding the repetition counter value (update if repetition
counter = 0) and if the UDIS=0 in the TIMx_CR1 register.
When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0
and UDIS=0 in the TIMx_CR1 register.
When CNT is reinitialized by a trigger event (refer to Section 14.4.3: TIM1&TIM8 slave
mode control register (TIMx_SMCR)), if URS=0 and UDIS=0 in the TIMx_CR1 register.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
BG TG COMG CC4G CC3G CC2G CC1G UG
w w w w w w w w
Bits 15:8 Reserved, must be kept at reset value.
Bit 7 BG: Break generation
This bit is set by software in order to generate an event, it is automatically cleared by
hardware.
0: No action
1: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or
DMA transfer can occur if enabled.

Advanced-control timers (TIM1&TIM8) RM0008
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Bit 6 TG: Trigger generation
This bit is set by software in order to generate an event, it is automatically cleared by
hardware.
0: No action
1: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if
enabled.
Bit 5 COMG: Capture/Compare control update generation
This bit can be set by software, it is automatically cleared by hardware
0: No action
1: When CCPC bit is set, it allows to update CCxE, CCxNE and OCxM bits
Note: This bit acts only on channels having a complementary output.
Bit 4 CC4G: Capture/Compare 4 generation
refer to CC1G description
Bit 3 CC3G: Capture/Compare 3 generation
refer to CC1G description
Bit 2 CC2G: Capture/Compare 2 generation
refer to CC1G description
Bit 1 CC1G: Capture/Compare 1 generation
This bit is set by software in order to generate an event, it is automatically cleared by
hardware.
0: No action
1: A capture/compare event is generated on channel 1:
If channel CC1 is configured as output:
CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled.
If channel CC1 is configured as input:
The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set,
the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the
CC1IF flag was already high.
Bit 0 UG: Update generation
This bit can be set by software, it is automatically cleared by hardware.
0: No action
1: Reinitialize the counter and generates an update of the registers. Note that the prescaler
counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if
the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload
value (TIMx_ARR) if DIR=1 (downcounting).
RM0008 Advanced-control timers (TIM1&TIM8)
Doc ID 13902 Rev 13 333/1093

14.4.7 TIM1&TIM8 capture/compare mode register 1 (TIMx_CCMR1)
Address offset: 0x18
Reset value: 0x0000
The channels can be used in input (capture mode) or in output (compare mode). The
direction of a channel is defined by configuring the corresponding CCxS bits. All the other
bits of this register have a different function in input and in output mode. For a given bit,
OCxx describes its function when the channel is configured in output, ICxx describes its
function when the channel is configured in input. So you must take care that the same bit
can have a different meaning for the input stage and for the output stage.

Output compare mode:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC2
CE
OC2M[2:0]
OC2
PE
OC2
FE
CC2S[1:0]
OC1
CE
OC1M[2:0]
OC1
PE
OC1
FE
CC1S[1:0]
IC2F[3:0] IC2PSC[1:0] IC1F[3:0] IC1PSC[1:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bit 15 OC2CE: Output Compare 2 clear enable
Bits 14:12 OC2M[2:0]: Output Compare 2 mode
Bit 11 OC2PE: Output Compare 2 preload enable
Bit 10 OC2FE: Output Compare 2 fast enable
Bits 9:8 CC2S[1:0]: Capture/Compare 2 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC2 channel is configured as output
01: CC2 channel is configured as input, IC2 is mapped on TI2
10: CC2 channel is configured as input, IC2 is mapped on TI1
11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if
an internal trigger input is selected through the TS bit (TIMx_SMCR register)
Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER).
Bit 7 OC1CE: Output Compare 1 clear enable
OC1CE: Output Compare 1 Clear Enable
0: OC1Ref is not affected by the ETRF Input
1: OC1Ref is cleared as soon as a High level is detected on ETRF input

Advanced-control timers (TIM1&TIM8) RM0008
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Bits 6:4 OC1M: Output Compare 1 mode
These bits define the behavior of the output reference signal OC1REF from which OC1 and
OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on
CC1P and CC1NP bits.
000: Frozen - The comparison between the output compare register TIMx_CCR1 and the
counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing
base).
001: Set channel 1 to active level on match. OC1REF signal is forced high when the counter
TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the
counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
011: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.
100: Force inactive level - OC1REF is forced low.
101: Force active level - OC1REF is forced high.
110: PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNT<TIMx_CCR1
else inactive. In downcounting, channel 1 is inactive (OC1REF=0) as long as
TIMx_CNT>TIMx_CCR1 else active (OC1REF=1).
111: PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNT<TIMx_CCR1
else active. In downcounting, channel 1 is active as long as TIMx_CNT>TIMx_CCR1 else
inactive.
Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed
(LOCK bits in TIMx_BDTR register) and CC1S=00 (the channel is configured in
output).
2: In PWM mode 1 or 2, the OCREF level changes only when the result of the
comparison changes or when the output compare mode switches from frozen mode
to PWM mode.
Bit 3 OC1PE: Output Compare 1 preload enable
0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the
new value is taken in account immediately.
1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload
register. TIMx_CCR1 preload value is loaded in the active register at each update event.
Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed
(LOCK bits in TIMx_BDTR register) and CC1S=00 (the channel is configured in
output).
2: The PWM mode can be used without validating the preload register only in one
pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed.
Bit 2 OC1FE: Output Compare 1 fast enable
This bit is used to accelerate the effect of an event on the trigger in input on the CC output.
0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is
ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is
5 clock cycles.
1: An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is
set to the compare level independently from the result of the comparison. Delay to sample
the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if
the channel is configured in PWM1 or PWM2 mode.
RM0008 Advanced-control timers (TIM1&TIM8)
Doc ID 13902 Rev 13 335/1093

Input capture mode

Bits 1:0 CC1S: Capture/Compare 1 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC1 channel is configured as output
01: CC1 channel is configured as input, IC1 is mapped on TI1
10: CC1 channel is configured as input, IC1 is mapped on TI2
11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if