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Basic Processing Units

Is a carl hamacher’s computer organisation and architecture 5th edition text book

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CT Al-Azhar
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23 views15 pages

Basic Processing Units

Is a carl hamacher’s computer organisation and architecture 5th edition text book

Uploaded by

CT Al-Azhar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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CHAPTER 7 BASIC PROCESSING UNIT ‘Cuarrer Onsecrives nhs chaper you will am abot: 1+ How a processor executes instructions +The internal fnctional anit of a processor and how they ae imerconnectd + Hardware for generating inter! cont signals +The micropogramning aproach + Microporam opasizaton a am fenapren 7 + BascProcssnc Ut la this and the next chapter we fcus on the processing unit wich executes machine insintos and coon heaves of othe unis. Tis wt is ofen called he Instruction Set Procstor (ISP), o spy the poceror, We exaniz titra sruc- ture and how it performs te asks of fetching, decoding and exciting instructions of 1 program, The prcesing uit used obo cll the cena prcesing unit (CPU)- ‘The ter “cara” est appropri today because many madem compa ems inca several procesting Unis ‘The organization of proceso has evedaver the years driven by deveopents in techaoogy andthe nee to provide high performance. A common satey inthe development of bgh perfomance proceso iso make various funcional units p- crate in paral as mach as posible High peomance proceso have «pipelined ‘xtizaton where the excuon of oe insructn is are before te exzton of the preceding instruction i compete. In another approach, known s supercar op- eration, seve instrctins are etched and execated at the sume tine. Pipelining and supencalarabietures ar scsi Chapter 8Inthis chapter, we concentra 00 the basic ides that ae common tal proceso ‘Atypical eompsig tak consis of a sre of steps spied by a sequence of mactneinsttons that constitu a rogram. Amst i excited by crying ‘out «sequence of more raiment Operation. These opention ad the means by which thy are controled arth msi pi ofthis hap. 7.1 SOME FUNDAMENTAL CONCEPTS ‘To execute «program, the processor fetches one instruction at aime and performs the operations specified. Insructions are fetched from successive memory heatios until branch ora jmp instruction is encountered. Te procesor keeps tack ofthe adress ‘ofthe memory location containing the next instruction tobe fetched using the program ‘counter, PC, After etching an instruction, the contents ofthe PC ae updated o point {othe nex instruction inthe sequence Abrach instruction may lod diferent alae ito the PC. ‘Another key register in the processor isthe instruction register, IR. Suppose tht ‘ach nsructon comprises 4 bytes, and tha ts stored in one memory word. T exeeate ‘an intruction, the processor has to perform the following thee steps: 1, Fetch the contents ofthe memory location pointed toby the PC. The contents of this location ae interpreted as an instruction tobe exceed. Hence they are loaded it the IR. Symbolically, his canbe writen as Rec 2. Assuming thatthe memory is byte aldressbl, inerement the contents ofthe PC by 4 thats, Poe (PC +4 3. Cary out the actions specified by the instruction nthe TR. 7.4 Sena RONMENT CONCRETE Tn cases where an instruction occupis more than one word, tes 1 and 2 must be repeated as many times as necessary o fetch the complete instruction. These two steps are ually refered to asthe eck phase; step 3 constitutes the execution phase. ‘Tostudy these operations in detail, we fist need examine theinteal organization ofthe processor. The main building block of «processor were introduce in Figure 12. ‘They canbe organized and interconnected in vavey of ways. We will tart with a ‘very simple organization. Later in this chaper and in Chapter 8 we wil presen more ‘complex structures tht provide high performance. Figure 71 shows an organization aera pce on Figse 7.1 Sings organization ofthe dopa imide processor on enapran 7 + Rasc Poona UT in wich he artes nt logic uit (ALL) and al he egies are inrconected ‘via a single common bs. Ths busi intemal oth procesor and should not be Confused with he extra bs th comets he processor to the memory and 10 devices. The data anaes ins ofthe eteral memory bs ae shown ia Figure 7.1 onneie othe intl processor bas vi the memory daa reir, MDR, and the memory adress eit, MAR, respec. Register MDR as two ips an two puts. Datamay be loud into MDR ete fom the memory bs or rom the internal eovestor but. The ata toed in MD may be placed on ther is. Thenput of MAR ‘is connected to he intemal us, and its utp is connected to the exe bus. The Coot ines ofthe memory bs ae cone ohe instctio decor an contol Jogicblack. This uit responsible forisuing the signals that cota te operation of all hunts siete proceso nd fr neracting with he memory bas ‘The number and wse of the processor repistrs RO through Rin ~ 1) vary consi exaly fom one processor to another. Reiter maybe provided for genera purpose tse by the progamer Some may be dedicated at special-purpose reps, sch at index eisers stack pit. Tre register YZ, nd TEMP in Fir 71, ave ‘oc teen mentioned before. Tes reies ae tansparet othe programme, th is the programmer need nt be concerned with them because they ae ever refereed explicitly by ay ixruton. They ae uted by the processor for temporary stage caring ckecuon of some instructions. These reser ae never sed fo ring data secrtd by ve instruction frat wse by anche istration. “The mukiplenex MUX select eter th ouput of riser ¥ o constant ae 410 be provided ak input A of the ALU. The constant is wed 1 increment he contents ofthe program coun. We wile tothetwo posible vale ofthe MUX conto apt Select a Select® and Select for sling the constant $c eisterY, respectively. ‘As instcton execution progrese, data ar transfered fom one registro an- cir, oftenpssng through the ALU o perform some citmetc olgc operation ‘The insti decndr and contra gi nit i responsible for iplerenig thea ons specif by the isoucton loaded in th IR restr. The decir gees he conto signals needed to select the registers valved and dec the transfer of dat. The regis, the ALU, andthe nteconecig bus ar cllectively refed tom the daupath ; ‘With few exceptions, an instruction canbe executed by performing one or more of the following operations in some pete sequence: 1+ Teatfer word of da fom oe prosstor registro aor or tthe ALU + Perform an armetic or & lope operation and sore there in a procesar reginer + Pech th content fa ten memory lotion and load them iat «procesar reir + Stare a word of data from processor register into given memory estion We now consider in detail how each of these operons i implemented, sig the simple processor mode in Figur 7. 7.4) Some RNDwaeTAL CONCH TaaNsrrRs Insruction exeetion involves a sequence of steps in which data are transfered from ‘one register to another. Fo each register, two contol signals ae used to place the contents ofthat register on the bus or 10 load the data on the bus into the register. ‘This is represented symbolically in Figure 72. The input and orp of register Ri are connected tothe bus va switches controlled bythe signals Rij and Ria spectively When Ris is set oI, the data on the bus are loaded into Ri. Similarly, when Rig it {eto | the contents of rps Ri ae placed on the bus. While Ri equal 10, the ts canbe used for transferring data from othe epses. ‘Suppose that we wish to tansfr the contents of register Rl to register RA, This «can be accomplished as follows: ‘+ Enable the ouput of register RI by setting Rly to 1. This places the contents of RI on the processor bus. + Enable the input of register RA by setting R6y to 1. This loads data from the rocestor bs into register R& ‘Alloprtons an data tanfer within processor ake place within ime prods

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