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Digital Systems Design Lab Experiments

This document summarizes 6 experiments conducted as part of a digital systems design lab course. The experiments involve verifying logic gates, designing and testing half adders, full adders using half adders, and half and full subtractors in ModelSim. For each experiment, the student provides the aim, truth table, logic diagram, Verilog code, and output verified with test benches.

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dhruv.kumar2021a
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192 views19 pages

Digital Systems Design Lab Experiments

This document summarizes 6 experiments conducted as part of a digital systems design lab course. The experiments involve verifying logic gates, designing and testing half adders, full adders using half adders, and half and full subtractors in ModelSim. For each experiment, the student provides the aim, truth table, logic diagram, Verilog code, and output verified with test benches.

Uploaded by

dhruv.kumar2021a
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd

NAME: DHRUV KUMAR

REG. NO.: 21BCE0923


BECE102P DIGITAL SYSTEMS DESIGN LAB
ASSESSMENT 1
EXPERIMENT 1 LOGIC GATE VERIFICATION
DATE: 10/8/2022
AIM: To verify all logic gates using ModelSim by forcing values (by clocking) and by using
test benches).
Truth Table:

Logic diagram and Boolean expression:

Verilog Code:
module LogicGates(ya,yo,yna,ynb,yx,a,b);
input a,b;
output ya,yo,yna,ynb,yx;
and (ya,a,b);
or (yo,a,b);
not (yna,a);
not (ynb,b);
xor (yx,a,b);
endmodule
Test Bench:
module LgTb;
wire ya,yo,yna,ynb,yx;
reg a,b;
LogicGates lg1(ya,yo,yna,ynb,yx,a,b);
integer i;
initial
begin for (i=2'b0;i<4;i=i+1)
begin {a,b}=i; #10;
end end
endmodule

Verilog Output by forcing values (by clocking):


Verilog Output by testbench:

Verified Output:
EXPERIMENT 2 HALF ADDER
DATE: 24/8/2022
AIM: To make Half Adder using ModelSim and verify using test bench.
Truth Table and Boolean expression:

Logic diagram:

Verilog Code:
(A) Data flow
(B) Behavioural modelling
(c) Gate level

Verilog Output:
EXPERIMENT 3 FULL ADDER
DATE: 07/09/2022

AIM: To make Full Adder using ModelSim and verify using test bench.

Truth Table:

Logic diagram and Boolean expression:


Verilog Code:
(A) Data flow
(B) Behavioural modelling
(C) Gate level

Verilog Output:
EXPERIMENT 4 FULL ADDER using Half Adder
DATE: 14/09/2022

AIM: To make Full Adder using half adder using ModelSim and verify with test bench.

Truth Table:

Logic diagram and Boolean expression:


Verilog Code:
(A) Gate Level
(B) Behavioural modelling
(C) Data flow:

Verilog Output:
EXPERIMENT 5 HALF SUBTRACTOR
DATE: 21/9/2022

AIM: To make Half Subtractor using ModelSim and verify using test bench.

Truth Table and Boolean expression:

Logic diagram:
Verilog Code:

Verilog Output:
EXPERIMENT 6 FULL SUBTRACTOR
DATE: 21/9/2022

AIM: To make Full Subtractor using ModelSim and verify using test bench.

Truth Table:

Logic diagram and Boolean expression:


Verilog Code:

Verilog Output:

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