EC4066D Nanoelectronics
Dr. Venu Anand
Room No.202, ECED block I
venuanand@[Link]
Bringing atoms together
Splitting of energy levels
Band Theory of solids
Energy levels in nanoparticles
Nanostructures of Carbon
MoSFET and CMOS Technology
Moore’s law:
In 1965, Intel co-founder Gordon Moore predicted that the number of transistors on a chip would double roughly
every two years, with a minimal rise in cost. This prediction became known as Moore’s Law.
The more transistors or components on a device, the cost per device is reduced while the performance per device is
increased.
The Ubiquitous nature of Moore’s law:
Smil, V., 2022. Numbers Don't Lie: A Moore's Law-
for Bombs: The rising power of destructiveness is,
unfortunately, the most impressive metric of
modern technology. IEEE Spectrum, 59(7), pp.18-
18.
Dennard Scaling Law:
In semiconductor electronics, Dennard scaling, also known as MOSFET scaling, is a scaling law which states
roughly that, as transistors get smaller, their power density stays constant, so that the power use stays in proportion
with area; both voltage and current scale (downward) with length.
Dennard's model of MOSFET scaling implies that, with every technology generation:
[Link] dimensions could be scaled by −30% (0.7×). This has the following effects simultaneously:
1. The area of an individual device reduces by 50%, because area is length times width.
2. The capacitance associated with the device, C, is reduced by 30% (0.7×), because capacitance varies with
area over distance.
3. To keep the electric field unchanged, the voltage, V, is reduced by 30% (0.7×), because voltage is field times
length.
4. Characteristics such as current and transition time are likewise scaled down by 30%, due to their relationship
with capacitance and voltage.
5. Overall circuit delay is assumed to be dominated by transition time, so it too is reduced by 30%.
[Link] above effects lead to an increase in operating frequency, f, by about 40% (1.4×), because frequency varies with
one over delay.
[Link] consumption of an individual transistor decreases by 50%, because active power is CV2f.
Therefore, in every technology generation, the area and power consumption of individual transistors is
halved. In other words, if the transistor density doubles, power consumption (with twice the number of
transistors) stays the same.
Technology nodes
MOSFET scaling process nodes)
10 µm – 1971
6 µm – 1974
3 µm – 1977
1.5 µm – 1981
1 µm – 1984
800 nm – 1987
600 nm – 1990
350 nm – 1993
250 nm – 1996
180 nm – 1999
130 nm – 2001
90 nm – 2003
65 nm – 2005
45 nm – 2007
32 nm – 2009
22 nm – 2012
14 nm – 2014
10 nm – 2016
7 nm – 2018
5 nm – 2020
Future
3 nm ~ 2023
2 nm ~ 2024
Course Outcomes:
CO1: Illustrate challenges faced by present CMOS VLSI device design and fundamental limits of operation.
CO2: Explain novel MOS based silicon devices and various multi gate devices.
CO3: Develop knowledge about SOI devices.
CO4: Examine different nanoelectronic systems and 2D materials and Devices
Module 1: (10 hours)
Challenges going to sub-100 nm MOSFETs – Oxide layer thickness, tunneling, power density, non-uniform dopant
concentration, threshold voltage scaling, lithography, hot electron effects, sub-threshold current, velocity saturation,
interconnect issues, fundamental limits for MOS operation.
Module 2: (13 hours)
Novel MOS-based devices – Multiple gate MOSFETs, Silicon-on-insulator, FDSOI, vertical MOSFETs, strained Si
devices, FinFET, optoelectronic, and spintronics devices, Heterostructure based devices – Type I, II and III
heterojunctions, Si-Ge heterostructure, heterostructures of III-V and II-VI compounds – Resonant tunneling devices
(diodes & transistors)
Module 3: (16 hours)
Carbon nanotubes based devices – CNFET, characteristics, Hysteresis and device passivation, Single Electron
Memory, 2D materials and devices, Spintronics - Spin-based devices – SpinFET, characteristics
References
1. Robert F. Pierret Semiconductor Device Fundamentals, 2nd Ed., Addison-Wesley Publishing
Co, 1996 or next edition
2. Fundamentals of Electronic Devices, Achutan and K.N Bhat, McGraw Hill
3. Fundamentals of Modern VLSI Devices, Taur and Ning, Cambridge University Press
4. MOS (Metal Oxide Semiconductor) Physics and Technology, E.H Nicollian and J.R Brews,
Wiley Publishers
Evaluation policy
Evaluation Date Marks Mode
Interim test Sept 14th – 26th 30 Descriptive
Quiz Oct 30th 15 Descriptive
Assignment Nov 9th 15 Simulation/Report
End-sem Exam Nov 23rd - Dec 6th 40 Descriptive
Grading: Relative
• Attendance ~ 80%
• Course is designed for students who are interested in semiconductor devices and for those
who intend to do higher studies :
• Last date for course drop is 18th August (Friday)
• Self study is highly recommended
